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Small-Signal Analysis of CMOS Two-Stage Op Amp

■ Cascade two-port models of differential ampliÞer with current-mirror supply


(input stage) and common-source ampliÞer with current supply (second gain
stage)

vi+
+ + +

vd Gm1vd Rout1 vi2 Gm2vi2 Rout vo

vi− − − −

■ First stage:
polarity of Gm1 is inverted to reßect reversal of input terminals ... which is done
to make the overall gain positive for vd > 0
Gm1 = gm1
Rout1 = ro2 || ro4
■ Second stage:
Gm2 = gm5
Rout = ro5 || ro6

a vdo = ( Ð G m1 R out1 ) ( Ð G m2 R out )

a vdo = g m1 ( r o2 r o4 )g m5 ( r o5 r o6 )

EE 105 Spring 1997


Lecture 37
Two-Stage CMOS Design Example

■ Design constraints
Typical situation for an internal op amp: area and power are both limited.
SimpliÞed area constraint -- set Wmax = 150 µm
(for minimize channel-length modulation, set Lmin = 3 µm)
Set DC power budget at 1.25 mW (including reference current) for case where
we have symmetrical supplies: V+ = 2.5 V and V - = - 2.5 V.

■ Initial Transistor Sizing:


Make (W/L)1 = (150 µm / 3 µm) in order to maximize Gm1 and maximize
common-mode input voltage range
DC currents: assume IREF = 50 µA
Set DC bias current of differential ampliÞer = DC bias of common-source stage
= 100 µA each as a Þrst-cut --> total current drawn is 250 µA --> power spec. is
just met
Transistor dimensions: (W/L)5 = (150 µm / 3 µm) to maximize gm5
( W ⁄ L )5 Ð I D6 100 µA
---------------------------- = ------------ = ------------------- = 1
2 ( W ⁄ L ) 3, 4 I D7 100 µA

Therefore (W/L)3,4 = (W/L)5 /2 = 25 --> W3,4 = 75 µm since we use Lmin to save


area.
For symmetrical output swing, we set (W/L)6 = (W/L)5 = (150 µm / 3 µm)
To maximize common-mode input range, we also set (W/L)7 = (150 µm / 3 µm)

EE 105 Spring 1997


Lecture 37
First-Cut CMOS Two-Stage Op Amp

+2.5 V

M8 M7 M6
(75/3) 1 (150/3) (150/3)

2
_ + +
M1 M2 CL v
vI− (150/3) (150/3) vI+ Cc O

50 µA
4
M3 3 M4 M5
(75/3) (75/3) (150/3)

−2.5 V

n-channel MOSFET
µA
µnCox = 50 tox = 15 nm Cov = 0.5 fF/µm φBn = 0.95 V
V2
0.1(µm/V)
VTOn = 1.0 V λn = Cjno = 0.1 fF/µm2 mjn = 0.5
L
γn = 0.6 V1/2 2φp = −0.8 V Cjswno = 0.5 fF/µm mjswn = 0.33

p-channel MOSFET
µA
µpCox = 25 tox = 15 nm Cov = 0.5 fF/µm φBp = 0.95 V
V2
0.1(µm/V)
VTOp = −1.0 V λp = Cjpo = 0.3 fF/µm2 mjp = 0.5
L
γp = 0.6 V1/2 2φn = 0.8 V Cjswpo = 0.35 fF/µm mjswp = 0.33

EE 105 Spring 1997


Lecture 37
DC Bias Solution

■ Assume that the DC input voltages are VI+ = VI- = 0 V and VO = 0 V

■ Input common-mode voltage range

V IC,max = 2.5 V Ð ( Ð 1 V ) Ð 1.28 V Ð 1.4 V = 0.82 V

V IC,min = Ð 2.5 V + 1.28 V + ( Ð 1 V ) = Ð 2.22 V

room for improvement in the upper limit -- possible at the expense of increased
area (W/L) ratios must be increased.

■ Output voltage swing

V O,max = 2.5 V Ð 0.4 V = 2.1 V

V O,min = Ð 2.5 V + 0.28 V = Ð 2.22 V

output range in nearly symmetrical and adequate

EE 105 Spring 1997


Lecture 37
Small-Signal Performance

■ Small-signal parameters:
gm1 = gm2 = 357 µS
gm5 = 2 gm1 = 714 µS
ro2 = ro4 = 600 kΩ
ro5 = ro6 = 300 kΩ

■ Differential voltage gain:

4
a vdo = ( 0.357 ) ( 600 600 ) ( 714 ) ( 300 300 ) = 1.15 ×10

in decibels, |avdo|dB = 81 dB.

EE 105 Spring 1997


Lecture 37
Stability -- A Brief Introduction

■ Non-inverting, unity gain conÞguration

vs(t) +
_ Op Amp vo(t)

vs(t) = vssin(ωst)
Feedback is to negative terminal of op amp, which tends to stabilize the output
voltage vo(t) to be nearly equal to vs(t)
■ What happens when the phase of avd(jωs) = 180o?
... the sign of avd is ßipped! Consider + and - terminals to be reversed!
... if |avd(jωs)| > 1, then the output is destabilized if the input is perturbed.

EE 105 Spring 1997


Lecture 37
Ensuring Stability

■ If the gain of the op amp is less than 1 (in magnitude) when the phase is 180o,
then the unity-gain non-inverting configuation (worst-case) will be stable
■ One solution: locate the second pole of the op amp ω2 at approximately the unity
gain frequency

ω 2 ≈ a vdo ω 1

■ The second gain stage is responsible for both poles

C'c

+
+
Is C1 Vi2 R1 Gm2Vi2 Rout C'L Vo

Device capacitances are lumped together in the circuit:


C 1 = C gs5 + C gd4 + C db4 + C gd2 + C db2
C L ′ = C L + C db5 + C db6 + C gd6
C c ′ = C c + C gd5

The compensation capacitor Cc sets the dominant pole ω1 by the Miller effect:
Ð1
ω 1 ≈ R 1 C 1 + R 1 ( 1 + G m2 R out )C c ′
where R1 = Rout1

EE 105 Spring 1997


Lecture 37
Second Pole Location

■ Direct factoring of transfer function --> ÒexactÓ expression for ω2


For the case when C 1 Ç C c ′, C L ′

1
ω 2 ≈ G m2 ⁄ C L ′ = --------------------------------
( 1 ⁄ G m2 )C L ′

■ Interpretation:
At frequencies around ω2 (>> ω1), the impedance Zc = (1 / jω2 Cc) is small
enough that M5 can be considered diode-connected
Load capacitance sees a ThŽvenin resistance of 1 / gm5 -->

ω2 is set by the load capacitance in parallel with 1 / gm5


■ Adjusting compensation and load capacitors to satisfy ω 2 ≈ a vdo ω 1

G m2 ( G m1 R out1 ) ( G m2 R out ) ( G m1 R out1 ) ( G m2 R out )


ω 2 ≈ ----------- ≈ ------------------------------------------------------------------------- ≈ ----------------------------------------------------------
C L ′ R 1 C 1 + R 1 ( 1 + G m2 R out )C c ′ G m2 R 1 R C c ′
out

since Gm2Rout >> 1


 G m1
C c ′ ≈ C L ′  -----------
 G m2

EE 105 Spring 1997


Lecture 37
Capacitor Sizing

■ The load capacitor is set by system speciÞcations: CL = 7.5 pF


with parasitic capacitances --> C L ′ = C L + 350 fF = 7.85 pF

■ The compensation capacitor is approximately

357 µS
C c ′ ≈  ------------------ C L ′ = 3.9 pF
 714 µS

the ÒexactÓ result is signiÞcantly higher ... C c ′ = 5.3 pF

■ Area requirement with a 500 • thick oxide is less than 100 x 100 µm2 -->
not a signiÞcant addition to the op amp area

■ Pole locations:

ω 1 = 5.8 krad/s ω 2 = 67.2 Mrad/s

■ SPICE: must increase Cc to 20 pF in order to have ω 2 ≈ a vdo ω 1


ω 1 = 1.3 krad/s ω 2 = 10.4 Mrad/s

EE 105 Spring 1997


Lecture 37
EE 105 Spring 1997
Lecture 37