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U1 VDD
2 11
RA0/AN0/C1IN- RC0/T1OSO/T13CKI
3 12
RA1/AN1/C2IN- RC1/T1OSI/CCP2B U2
4 13
RA2/AN2/C2IN+/VREF-/CVREF RC2/CCP1
5 14 3 8 VS
RA3/AN3/C1IN+/VREF+ RC3/SCK/SCL SCK VOUTA A
6 15 2
RA4/T0CLKI/C1OUT RC4/SDI/SDA CS
7 16 4
RA5/AN4/SS/HLVDIN/C2OUT RC5/SDO SDI B
10 17 5 6
RA6/OSC2/CLKO RC6/TX/CK LDAC SHDN
9 18
RA7/OSC1/CLKI RC7/RX/DT C
MCP4821
21
RB0/AN12/INT0/FLT0 D
22
RB1/AN10/INT1
23
RB2/AN8/INT2
24
RB3/AN9/CCP2A
25
RB4/AN11/KBI0 VSS
26
RB5/KBI1/PGM
27
RB6//KBI2/PGC VDD
28 1
RB7/KBI3/PGD RE3/MCLR/VPP
PIC18F2620
R9
10k
R10
VDD
VSS VDD
VDD 10k
5
4
3
2
1
C2
100nF
J1 VSS
VSS
J4
1
VSS ICD2
C1 2
100nF
CONN-SIL2
VSS
VSS
void main(void)
{unsigned int a;
init_horloge_interne();
initSPI_emission();
while(1) // demo, generateur de rampes
{
for (a=0;a<=????;??)
{
emet_SPI(a);
}
}
}