IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO.
3, MAY 2000
A Single-Switch AC–DC Converter with Power
Factor Correction
Huai Wei, Issa Batarseh, Senior Member, IEEE, Guangyong Zhu, Member, IEEE, and Peter Kornetzky
Abstract—A new single-stage, single-switch power factor cor-
rection converter with output electrical isolation will be proposed
in this paper. The topology of this converter is derived by com-
bining a boost circuit and a forward circuit in one power stage. To
improve the performance of the ac–dc converter (i.e., good power
factor correction, low total harmonic distortion (THD) and low
dc bus voltage), two bulk storage capacitors are adopted. Its ex-
cellent line regulation capability makes the converter suitable for
universal input application. Due to its simplified power stage and
control circuit, this converter presents a better efficiency, lower
cost and higher reliability. Detailed steady state analysis and de-
sign procedure will be presented. To verify the performance of the
proposed converter, a design example along with P-simulation pro-
gram with integrated circuit emphasis (PSPICE) simulation and
experimental implementation will be given. The measured power
factor and efficiency are 99% and 87% at low line (i.e., 110 VAC)
operation, and 95% and 81% at high line (i.e., 220 VAC) operation,
respectively.
Index Terms—AC–DC converters, high frequency power conver-
sion, power factor correction, switching mode power supply.
NOMENCLATURE
Ac/dc average duty ratio.
Maximum duty ratio.
dDc input voltage.
Output voltage.
Output current.
Line voltage.
Line current.
Rectified line voltage.
Rectified line current.
Averaged (filtered) line current.
Rms value of line voltage.
Voltage across storage capacitor.
Switching frequency.
Switching period.
Transformer turn ratio.
Line period.
Load time constant.
Normalized load time constant.
Inductance ratio.
Manuscript received July 8, 1998; revised February 1, 2000. Recommended
by Associate Editor, M. E. Elbuluk.
H. Wei and I. Batarseh are with the Electrical and Computer Engineering
Department, University of Central Florida, Orlando, FL 32816 USA (e-mail:
batarseh@mail.ucf.edu).
G. Zhu is with International Power Devices, Inc., Orlando, FL 32816 USA.
P. Kornetzky is with the Department of Circuit Design and Measurement
Technology, Institute for Microelectronic and Mechatronic Systems, Ilmenau
D-98693, Germany.
Publisher Item Identifier S 0885-8993(00)03378-0.
0885–8993/00$10.00 © 2000 IEEE
421
Ac/dc conversion ratio.
Storage capacitor voltage to output voltage ratio.
I. INTRODUCTION
W ITH the development in advanced power semiconductor
devices, more and more switch-mode power supplies
(SMPS’s) and other power switching circuits are used in modern
power system. Due to the nonlinear behavior of power switched
circuits, distorted currents are normally drawn from the line, re-
sulting in low power factor (usually less than 0.67) and high total
harmonic distortion (THD). Declining power quality in many
power electronic systems has become an important issue as il-
lustrated by many recent surveys and industry reports [1]–[3].
Traditionally, to improve power factor of a given power elec-
tronic system, normally a power factor correction (PFC) cir-
cuit is designed and placed in front end of the system, which
in turn interfaced with the load. This PFC circuit may be an
independent unit followed by a dc–dc converter, or an insep-
arable part of circuit incorporated into the power supply of the
load, namely two-stage PFC power supply and single-stage PFC
power supply, respectively. Because the line voltage is normally
not distorted (near sinusoidal), the basic idea of PFC is design
circuits with certain means to force the line current to follow the
waveform of the line voltage.
Because of the nature of PFC, there exists an unbalance of
instantaneous power between the input power, which is an al-
ternative quantity with two times the line frequency, and its dc
output power. Therefore, power factor correction involves pro-
cessing the input power in certain way that it stores the excessive
input energy when the input power is larger than the dc output
power, and releases the stored energy when the input power is
less than the dc output power. To accomplish the above task, at
least one energy storage element must be included in the PFC
circuit.
In most PFC circuits, normally an input inductor is used in se-
ries with line bridge rectifier in order to smooth the line current.
The input inductor can operate in either continuous conduc-
tion mode (CCM) or discontinuous conduction mode (DCM).
In DCM, the input inductor is no longer a state variable since
its state in a given switching cycle is independent on the value
in the previous switching cycle [4]. The peak of the inductor
current is sampling the line voltage automatically, resulting in
sinusoidal-like average input current (line current). This is why
DCM input circuit is also called “voltage follower.” The benefit
of using DCM input circuit for PFC is that no line current con-
trol loop (feed-forward loop) is required. This is also the main
422
advantage over a CCM power factor correction circuit, in which-
multi-loop control strategy is essential. However, the input in-
ductor operating in DCM can not hold the excessive input en-
ergy because it must release all its stored energy before the end
of each switching cycle. As a result, a bulky capacitor is used to
balance the instantaneous power between the input and output.
In addition, if discontinuous conduction mode is applied, the
input current is normally a train of triangle pulses with nearly
constant duty ratio. In this case, an input filter is necessary for
smoothing the pulsating input current.
The DCM input circuit can be one of the basic dc–dc con-
verter topologies. However, when they are applied to the recti-
fied line voltage, they may draw different shapes of average line
current. In recent years, many switching circuits like the fly-
back and the boost using DCM input technique were reported
[5]–[10]. Several single-stage single-switch (S ) PFC circuits
have been reported [7]–[10]. These circuits are especially attrac-
tive in low power applications with increased efficiency and re-
duced cost. The difficulties in constructing an effective S ac–dc
converter topology are as follows.
1) The unavoidable leakage inductance of the power
transformer produces high voltage spike at switching
instances, resulting in decreased efficiency.
2) Because the power switch performs both PFC and load
and line regulations, the converter regulation capabilities
are limited, resulting in difficulty in using them in uni-
versal input application.
3) Under high current and low duty ratio condition, the bulk
capacitor voltage is high, as a result, high rating capacitor
and switching devices must be used which in turn results
in increased cost.
4) The input stage still draws considerably distorted line cur-
rent.
A new ac–dc converter will be presented in this paper, aimed at
overcoming the above difficulties. The proposed converter
utilizes a DCM boost circuit as an input stage to perform PFC
and a forward circuit as an output stage to provide electrical iso-
lation. Two storage capacitors have been employed to enhance
the PFC capability of the boost circuit and to relieve the voltage
spike produced by the power transformer. The voltages across
the storage capacitors are kept at lower levels. Theoretical anal-
ysis and experimental results show that the converter has enough
line regulation capability to be applied to universal input.
The power factor correction capability of the boost converter
is firstly discussed in the next section. The principle of opera-
tion and steady state analysis of the proposed converter will be
presented in Section III and IV, respectively. In Section V, the
design procedure of the proposed converter will be given. Fi-
nally, in Section VI, the simulation and experimental results are
provided to verify the converter operation. Conclusions will be
given in Section VII.
II. POWER FACTOR CORRECTION CAPABILITY OF THE BOOST
CONVERTER
It is well known that pure resistive load offers unity power
factor for the line. Since the I–V characteristic of a resistor is
a straight line passing through its origin. By investigating the
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 3, MAY 2000
I–V characteristics, the line current waveforms drawn by the
basic converter topologies can be examined. The basic boost
converter and its input current waveform are shown in Fig. 1(a)
and (b), respectively. Since switching frequency is much higher
than the line frequency, let's assume the line voltage is constant
in a switching cycle. In DCM, the input current is discrete and
the peak current is a function of the line voltage. From Fig. 1(b),
it is clear that the average input current over one switching cycle
may be obtained from the following relation:
(1)
where
(2)
Therefore
(3)
By plotting (3) and extending to the second-half line cycle, we
obtain the input I–V characteristic curve as given in Fig. 1(c).
The figure illustrates that as long as the peak value of the line
voltage is in a certain range (less than the output voltage ),
the relationship between and is nearly linear,
hence a near sinusoidal average input current is drawn form the
line.
One might notice from (1) and (2) that the main reason to
cause the nonlinearity of the I–V characteristic is the existence
of discharging time ratio , which is a function of and
. Ideally, if , the input I–V characteristic will
be linear. Equation (2) shows that to reduce , higher output
voltage must be obtained. In most S converter, the output
voltage is held by a bulk capacitor and serves as the input
voltage source of the output stage. The output stage of the ac–dc
converter is a step-down circuit so that a low voltage level dc
is obtained. Therefore, to avoid the converter operating at ex-
cessively low duty ratio, , which will cause difficulty in op-
timizing the control circuit and higher input switching noise,
lower voltage is desired. Such design trade off is especially
unfavorable to the design of a universal input converter.
The above difficulty can be avoided by designing a step-down
switched-capacitor network to buffer the input circuit and the
output circuit. In next section, we will propose a new ac–dc con-
verter, which incorporates a boost converter, a switched-capac-
itor network (formed by two bulk capacitors and a diode) and a
forward circuit. It will be shown that the proposed converter can
achieve good power factor and allows universal input operation
as well.
III. PROPOSED CONVERTER AND ITS CIRCUIT OPERATION
The proposed ac–dc converter is shown in Fig. 2. The input
circuit is a boost circuit (formed by choke inductor , diode
and switch ). The switched-capacitor network consists of ca-
pacitors and and diode , serving as a load to the input
circuit, and as a source to the output forward circuit (formed
by transformer Tr and diode ). The two primary windings of
WEI et al.: SINGLE-SWITCH AC/DC CONVERTER WITH POWER FACTOR CORRECTION
(a)
(b)
Fig. 1. Input I–V characteristic of basic boost converter operating in DCM. (a) Boost converter for PFC. (b) Input current i (t). (c) Input I–V characteristics.
Fig. 2. Basic circuit schematic of the proposed converter.
TABLE I
MODES OF OPERATION
the forward transformer is designed with the same turn ratio re-
ferring to the secondary winding . Inductances
and are the leakage inductances of the forward
transformer. It can be shown that, in steady state, the proposed
converter has four operation modes during one switching cycle.
Table I shows the four modes of operation and conducting de-
423
(c)
vices during their corresponding time intervals. The equivalent
circuits of the four operation topologies are shown in Fig. 3 and
converter key waveforms are shown in Fig. 4.
Notice that in one switching cycle, the line voltage can be
considered as a constant voltage, represented by in the equiv-
alent circuits. Capacitors and are designed to be large
and equal. Hence, in the steady state analysis, each capacitor
voltage is approximated by a dc source .
The four modes of operation are discussed as follows:
Mode 1 begins at when the power switch is turned
ON. With diode conducting, the source voltage is applied
to the input choke inductor , causing the current through the
inductor increasing linearly. During this mode, energy is trans-
ferring from the source to the choke inductor. On the other hand,
diode is blocked by the two capacitor voltages since the posi-
tive end of is grounded by the power switch. Thus, the diode
splits the primary sides of the forward transformer into two sym-
metrical branches with one storage capacitor in each. These ca-
pacitors (previously charged) feed the primary sides of the for-
ward transformer individually, which is equivalent to using ca-
pacitance to feed the transformer with voltage ,
resulting in the energy stored in the two capacitors being trans-
ferred to load during this mode. This mode ends at when
the power switch is turned OFF as shown in Fig. 3. During this
mode, we have
424 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 3, MAY 2000

(a) (b)

(c) (d)
Fig. 3. Equivalent topologies for the four operation modes: (a) M1, (b) M2, (c) M3, (d) M4.

During this operation Mode 2, the power switch is turned

OFF at and diode is turned ON due to a current
flowing through it. The equivalent topology is shown
in Fig. 3(b). Under the constraint of KCL, both the storage ca-
pacitors, and , are being charged by current
during this operation mode. With the inductor current de-
creasing linearly, magnetic energy stored in the choke is being
converted into electric energy and being stored into the storage
capacitors. Thus the energy loss of the storage capacitors during
Mode1 is being recovered. At the same time, the forward trans-
former is being demagnetized through its secondary windings,
and its magnetizing energy is fed back to capacitors and
. It should be noticed that seen by the output of the boost cir-
cuit, presents since the two bulk capacitors are charging in
serial. Compared with other types of ac–dc PFC converters with
the same amount of energy stored in bulk capacitance ,
the proposed converter has a higher voltage to de-energize the
choke inductor, resulting in better power factor and regulation
capabilities, as discussed in Section II. When the forward trans-
Fig. 4. Theoretical key waveforms of the proposed converter. former is completely demagnetized, i.e., and become
zero, the converter's operation enters Mode 3. Using Fig. 3(b),
the following expressions are obtained:
(4a)

The duration of this stage is

(4b)

where is the duty cycle. (5a)

WEI et al.: SINGLE-SWITCH AC/DC CONVERTER WITH POWER FACTOR CORRECTION 425

the practical design. In terms of energy flow, the input circuit

is an energy compensator for the storage capacitors to keep the
The time interval is given by average input power being equal to the output power. There-
fore, ac–dc steady state analysis can be approximated by dc–dc
(5b) steady state analysis with effective (i.e., rms) value of the line
voltage approximated as its dc input voltage [11]. Correspond-
In operation Mode 3, the choke inductor current, , con- ingly, the ac–dc conversion ratio can be defined as
tinues to decrease linearly. Owing to the existence of diode ,
the primaries of the transformer present very high impedance (8)
[Fig. 3(c)] with the currents through the windings can be negli-
gible. This mode ends when the choke inductor current reaches
zero. The key voltages and currents in this duration can be de-
A. AC–DC Conversion Ratio
scribed as follows:
In order to find out the conversion ratio, let's first find the
voltage across the storage capacitor. In steady operation, we
have , where is the average current
(6a)
through diode , which can be determined from the waveform
of (Fig. 4). By solving the equation for ,
we obtain
The time intervals are

(6b) (9)
where
Where, is average duty ratio in a line cycle,
(6c) is inductance ratio and is normalized load,
where .
The operation Mode 4 between and is known as a It can be shown from Fig. 4 that the filtered line current can
free wheeling stage, which is used for regulation purpose. Since be expressed as
the proposed converter has a shorter choke inductor discharging
period, a wider free wheeling margin is available for the duty
(10)
ratio variation to regulate the converter. When the power switch
is turned ON again at , the converter operation goes
into the next cycle. During this mode, we have Therefore the maximum line current is given by

(7a) (11)

Since we have nearly unity power factor, the line current is al-
The time interval is given by
most sinusoidal. So, the rms value of line current can be approx-
(7b) imated by

(12)
IV. STEADY STATE ANALYSIS
The input voltage of the ac–dc converter is a rectified sinu- Based on the assumption of lossless converter, we have
soidal voltage, therefore, the steady state analysis involves two , i.e., . Using this
operation frequencies, i.e. line frequency (50 Hz or 60 Hz) and relation in (12) for , we obtain
high switching frequency. However, due to the existence of bulk
capacitors between the input and output stages, ac–dc conver-
(13)
sion is performed by the input stage. Because only the feed-
back control from the dc output is applied, the control duty ratio
mainly depends on the output stage. Because the bulk capac- Where, is determined by (9).
itor voltages are relatively stable, the steady state duty ratio is From (9) and (13), a group of curves showing versus
almost constant. Therefore, we may use average duty ratio in under different 's, can be obtained as shown in Fig. 5. The
the steady state analysis. Traditionally, the conversion ratio ac–dc conversion characteristics of this converter can be investi-
of a dc–dc converter is defined as the voltage ratio of the dc gated by examining these curves. It can be seen that for a certain
output voltage to the dc input voltage. In ac–dc converter, since load range, ac–dc conversion ratio can be adjusted by changing
the input voltage is a rectified sinusoidal voltage and the output the duty ratio of its driving signal. We may note that at light load
is a dc voltage, the conversion ratio is a periodical time func- (low ), the proposed converter can operate as both boost and
tion. Obviously, the above definition of is not convenient for buck converter.
426 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 3, MAY 2000

Fig. 5. Ac/dc conversion characteristics of the converter. Fig. 7. Maximum duty cycle.

B. Maximum Duty Ratio and Regulation Capabilities

According to the key waveforms shown in Fig. 4, inequality
must be satisfied in the converter operation.
Substituting (4b) and (6c) into the above inequality, we obtain

(15)

with the maximum duty ratio being given by

(16)

The maximum duty ratio gives an upper limit of the

converter duty ratio. In practical design, the nominal operation

Fig. 6. Storage capacitor voltage of the converter (V = M V ). duty ratio must be set with enough margin so that the con-
verter has certain regulation capabilities. It should be noticed
from (14) that the voltage ratio is not a function of load
In order to investigate the bulk capacitor voltage variation in , therefore the maximum duty ratio is only determined by the
terms of line voltage and load, let's solve for in (9) and (13) conversion ratio and the converter parameters and . Fig. 7
to yield gives a plot of maximum duty ratio in term of transformer ratio
under different conversion ratios.
In order to study the line and load regulation capabilities, we
(14) express the duty ratio in terms of and as follows:

where
(17)

where

By plotting (14), a graph showing versus is given in From (16) and (17), characteristic curves for versus
Fig. 6 for and . The bulk capacitor voltage under different loads and versus under different conversion
can be determined by . It should be pointed out ratios are given in Figs. 8 and 9, respectively. These figures can
that the voltage ratio is independent on the load change. be used to examine the regulation capabilities of the converter.
Moreover, when conversion ratio higher than 0.2, the capac- Referring to Fig. 8, we can investigate the line regulation ca-
itor voltage is almost kept at low level . Such pability of the proposed ac–dc converter. For example, a con-
property of the proposed converter is especially favorable for verter with 50 V output dc voltage is designed with
universal application. 0.25 and 0.16. At load 0.5, the gain can change
WEI et al.: SINGLE-SWITCH AC/DC CONVERTER WITH POWER FACTOR CORRECTION
Fig. 8. Line regulation capability of the converter.
Fig. 9. Load regulation capability of the converter.
between 0.1 to 0.82, which means theoretically, the output can
be kept at 50 V while the input voltage is changing within the
range of 61 V–500 V. The duty ratio range is between 0.08 to its
maximum 0.8. In short, a % variation in the line voltage re-
quires the duty ratio change by 58% to maintain constant output.
Similarly, the load regulation capability can be examined by re-
ferring to Fig. 9. For the above converter example, if
( 110 V, 50 V), theoretically, can vary between
0.1 to 1.3 with the output voltage being kept at 50 V. For 50%
load change, to maintain a constant output, a duty ratio change
of 66% is required.
C. Voltage and Current Stresses
Through steady state analysis, the voltage and current stresses
on each switch were found as listed in Table II.
D. Output Voltage Ripple
By integrating the current through the output capacitor
the output voltage ripple is given by
(18)
427
TABLE II
VOLTAGE AND CURRENT STRESSES ON SWITCH AND DIODES
E. Critical Choke Inductance
The critical choke inductance was found as
(19)
To ensure the converter operating in DCM, the choke inductor
must be selected with a value smaller than the critical induc-
tance.
V. DESIGN GUIDELINE OF THE PROPOSED CONVERTER
To design a proposed converter with specifications , nom-
inal load , output voltage ripple , and switching fre-
quency , the following design principles can be applied:
a) Selection of transformer turn ratio and inductance
ratio :
Selection of transformer turn ratio should be based on the
trade off between regulation capabilities and voltage stresses on
the devices. According to (9), a low will result in high voltage
across the storage capacitors. Since all the voltage stresses on
the switches ( and – ) depend on , we prefer a higher
transformer turn ratio. However, a higher causes the maximum
duty cycle to be lower, reducing both the line and load regula-
tion capabilities. Hence, a lower transformer turn ratio is de-
sired in this case. In practical design, a proper value of should
be chosen so that it gives enough regulation capabilities and
lower voltage stresses as well. From Table II, it seems that to
relieve high current stresses, we should increase the inductance
. But the effect will be very weak because the storage capac-
itor voltage increases with the increasing of as it can
be seen in (14). In practical design, we prefer a small value of
so that the voltage stresses can be reduced.
b) Setting of nominal duty ratio and normalized load:
When and have been chosen, Fig. 7 can be generated. The
nominal duty ratio can be approximated by
(20)
In the above equation, we assumed that the minimum duty ratio
, is 0.1. In Fig. 9, corresponding to the nominal duty ratio, nor-
malized load can be found.
c) Selection of choke inductance:
For given , the value of choke inductance is given by
(21)
428 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 3, MAY 2000

(b) Selection of and TABLE III

For a given can be selected according to THEORETICAL SWITCH AND DIODES VOLTAGE AND CURRENT STRESSES

(22)

(c) Selection of the storage capacitance:

To design the storage capacitors, let's consider that due to the
missing of one line cycle, an average voltage drop of on
the storage capacitor is allowed, then by analysis we have
d) Leakage inductances and :
(23) We can select and as

H
where is the line period. The voltage stress on the storage
capacitor can be calculated by e) Bulk capacitor :
Suppose that due to one line cycle missing, an average voltage
(24) drop of on the storage capacitor is allowed, i.e.,
. From (23) and (24), we have F, and
where can be determined by Fig. 9.
V.
Based on (23) and (24), the storage capacitors can be selected.
Select F/250 V.
(d) Selection of output capacitor:
f) Output filter capacitor :
From (18), we get
By calculating (25), the output capacitance is F.
We select F/100 V.
(25) g) Switching devices and :
From Table II, we calculate the theoretical diode and switch
For a given design with specified ripple factor, we can find a voltage and current stresses as listed in Table III. Considering
output capacitance. Together with the output voltage, an output switching speed, we choose
capacitor can be chosen.
g) Selection of switches: BUZ91A and MUR850
The selection of switches should be based on their voltage
and current stresses, which can be calculated according to the
equations listed in Table II. VI. SIMULATION AND EXPERIMENTAL RESULTS
Design Example: Let us consider the following specifica- By using the above designed circuit parameters, the
tions as a design example: closed-loop PSPICE simulation of the proposed single-stage
single-switch converter schematic has been carried out and
Nominal input voltage: V Hz the simulation results are shown in Fig. 10. An experimental
Input voltage range (rms): V– V prototype of the converter was built up in the laboratory with
Output voltage: V % the same circuit parameters. The forward transformer was
Nominal load current: A created with a Philips ETD-PST39 core. To obtain the designed
Switching frequency: KHz transformer ratios , the primary windings and secondary
For a universal input converter, the design should be based on winding were built with inductance values 30 mH and 1.9 mH,
low line operation ( 110 V). Following the above design respectively. Pulse-width-modulation chip SG3525 was used
guidelines, we obtain the converter parameters as follows. to achieve closed-loop control. The experimental waveforms
a) Transformer turn ratio and inductance ratio : of filtered line current, and voltage and current at the switch,
To compromise between voltage stress and regulation capa- shown in Fig. 11, were recorded by using hp54542A oscillo-
bilities, let's select 0.25 and 0.16, which give a max- scope. Both the simulated and the experimental waveforms
imum duty ratio of 0.65 and 200 V at 0.455. agree well and show that the waveforms of the line current is
b) Nominal duty ratio : almost sinusoidal one, proving that a good power factor can be
The duty ratio at nominal input is determined by (20) achieved by this converter topology. Measured power factor and
efficiency are given in Figs. 12 and 13, respectively. It can be
seen that the proposed converter can maintain 99% power factor
and 87% efficiency at low line ( 110 V) operation and
95% power factor and 82% efficiency at high line (
From Fig. 9, using and 0.38, we obtain 220 V) operation, respectively. The line harmonics and THD
0.5. under 110 VAC input/50 W output and 220 VAC input/50 W
c) Choke inductance : output were measured with hp6841A harmonic/flicker test
The choke inductance is hence determined by system, shown in Figs. 14 and 15, respectively. In both 110
VAC and 220 VAC input cases, all the harmonics are lower than
H IEC1000-3-2 Class D restriction. The measured bulk capacitor
WEI et al.: SINGLE-SWITCH AC/DC CONVERTER WITH POWER FACTOR CORRECTION 429

(a)
(a)

(b)
Fig. 10. Simulation waveforms of the proposed converter (under 110 VAC
input/50 W output): (a) voltage (upper) and current (lower) at the switch
(displayed at peak line voltage) and (b) line voltage and filtered input current.
(b)
Fig. 11. Experimental waveforms of the proposed converter (under 110 VAC
input/50 W output): (a) voltage (upper, 200 V/div.) and current (lower, 1 A/div.)
at the switch (recorded at peak line voltage) and (b) line voltage (upper, 100
V/div.) and filtered input current (lower, 1 A/div.).

voltage is shown in Fig. 16. It is noticed that with the output

current changing from 0.5 A to 1.5 A, only small capacitor
voltage change can be seen.
Simulations regarding to the tolerances of leakage induc-
tances and the storage capacitors were performed. For 50%
leakage inductance tolerance ( H, H),
only less than 2 V difference in storage capacitor voltages were
found. For 10% storage capacitance tolerance, less than 0.5 V
difference in storage capacitor voltages occurred.

VII. CONCLUSION

A new single-stage, single-switch ac–dc converter with

output electrical isolation used for power factor correction has Fig. 12. Experimental input power factor.
been presented in this paper. The strategy of developing the
converter topology is combining a boost circuit and a forward storage capacitors can be used owing to the low level bulk
circuit. The proposed converter is featured with the utilization capacitor voltage.
of switched-capacitor network to improve its performance. As
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Huai Wei was born in 1961. He received the B.S.
degree from Chengdu University of Science and
Technology, China, in 1983, the Post Graduate
diploma from Chongqing University, China, in
1987, the M.S. degree from Hong Kong Polytechnic
University, Hong Kong, in 1997, all in electrical
engineering, and is currently pursuing the Ph.D.
degree in power electronics at the University of
Central Florida, Orlando.
From 1983 to 1985, he was an Assistant Engineer
with the Design Institute of Guiyang Hydraulic
Power, China. From 1987 to 1994, he was with the Department of Electrical
Engineering, Sichuan University, China. His research interests include PFC
circuits, soft-switching power conversion, and distributed power supply
systems.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 3, MAY 2000
Issa Batarseh (SM'93) received the B.S., M.S., and
Ph.D. degrees, all in electrical engineering, from the
University of Illinois, Urbana, in 1983, 1985, and
1990, respectively.
He is an Associate Professor in the School of
Electrical Engineering and Computer Science, Uni-
versity of Central Florida (UCF), Orlando. He was
a Visiting Assistant Professor at Purdue University,
West Lafayette, IN, from 1989 to 1990, before
joining UCF in 1991. His major research interests
is in power electronics. The objective of his research
is the development of high frequency power converters to improve power
density, power factor, efficiency, and performance. His research includes the
analysis and design of high frequency dc-to-dc resonant converter topologies;
low-voltage dc–dc converters, small signal modeling and control of PWM and
resonant converters; power factor correction techniques; and power electronic
circuits for distributed power systems applications.
Dr. Batarseh was a Chairman of the PE/AES/PEL Chapter, Orlando IEEE
Section, and is the Chairman of the IEEE-Orlando Section. He has served as a
Reviewer for the National Science Foundation and several IEEE TRANSACTIONS
and served on the Program Committees of IEEE-APEC, PESC, IECON, IAS,
and ISCAS. He is a registered Professional Engineer in Florida.
Guangyong Zhu (M'97) was born in 1964. He re-
ceived the B.S. degree from Hunan University, China,
in 1984, the M.S. degree from Tsinghua University,
China, in 1987, and the Ph.D. degree from the Univer-
sity of Central Florida, Orlando, in 1999, all in elec-
trical engineering.
Since 1987, he has been with the Department of
Electrical Engineering, Sichuan University, China,
for six years. From 1993 to 1995, he was a research
student at the Hong Kong Polytechnic University,
Hong Kong. His research interests include modeling,
dc/dc power conversion, PFC converter design, and distributed power systems.
He is now with International Power Devices, Inc., Orlando, FL.
Peter Kornetzky was born in 1961, Rudolstadt, Germany. He received the B.S.
and Ph.D. degrees from the Technical University of Ilmenau, Germany, in 1987
and 1990, respectively.
From 1990 to 1996, he was a Lecturer and Researcher with the Department
of Electrical and Computer Engineering, Technical University of Ilmenau. From
1995 to 1996, he was a Visiting Professor at the University of Central Florida,
Orlando. Since 1996, he has been a Scientific Manager of the Department of
Circuit Design and Measurement Technology, Institute for Microelectronic and
Mechatronic Systems, Ilmenau, Germany. He holds three patents and has pub-
lished more than ten papers.