Conditions Static CMOS Ratioed Circuit Dynamic Logic

(Pseudo-nMOS) (Dual-Rail Domino)

A>B Idd_max=1.826mA Idd=1.275mA Idd=3.855mA

Idd_avg=0.289mA Idd_avg=0.080 Idd_avg=0.402mA
Vdd=1.20V Vdd=1.20V Vdd=1.20V
V_max=1.224V V_max=1.20V V_max=1.20V
P=0.339mW VOL=0.301V VOL=0.00V
P=2.349mW P=0.482mW
From node input b0’ to From node input a0, b0
output A>B, t=0.200ns, From node input a0, b0 and b1 to output A>B,
F=5.00GHZ, Delay= 74ps and b1 to output A>B, t=0.200ns, F=5.00GHZ,
t=0.602ns, F=1.66GHZ, tdr= 13ps,tdr=15ps
From node input a0 and Delay= 21ps
a1 to output A>B,
t=0.200ns, F=5.00GHZ,
Delay= 77ps

A<B Idd=1.744mA Idd=1.275mA Idd=3.855mA

Idd_avg=0.295 Idd_avg=0.080 Idd_avg=0.402
Vdd=1.20V Vdd=1.20V Vdd=1.20V
V_max=1.224V V_max=1.087V V_max=1.084V
P=0.354mW VOL=0.301V VOL=0.116V
P=2.349mW P=0.482mW
From node input
INPUT_A<B_a0' to From node input a0, b0
output A<B, t=0.400ns, and b1 to output A=B,
F=2.50GHZ, Delay= 20ps t=0.2ns, F=5.02GHZ,
From node input a0, b0 Delay= tr=rise time
From node input and b1 to output A=B, delay =11ps and
INPUT_A<B_b0 and b1 t=0.602ns, F=1.66GHZ, fall time
to output A<B, Delay= 21ps delay=tpd=13ps
t=0.400ns, F=2.50GHZ, On every node delay is On every node delay is
Delay= 24ps no more than 21ps. And no more than 21ps. And
reduced to 9ps reduced to 9ps
A=B Idd=1.275mA Before applying correct Idd=2.568mA
Idd_avg=0.080mA sizes to pMOS and Idd_avg=0.134mA
Vdd=1.20V nMOS: Vdd=1.20V
V_max=1.224V Corrupted V_max=1.20V
P=99.58uW input/output: VOL=0.00V
Idd=2.110mA P=0.161mW
From node input a0, b0 Idd_avg=1.031mA
and b1 to output A=B, Vdd=1.20V From node input a0, b0
t=0.400ns, F=2.50GHZ, V_max=0.630V and b1 to output A=B,
Delay= 120ps VOL=0.301 t=0.639ns, F=1.56GHZ,
P=1.238mW delay:
From node input a1 to tdr=49ps and t=10ps
output A=B, t=0.400ns, VOH and VOL are too
F=2.50GHZ, Delay= 20ps close that delay is un-
noticeable.
From node input a0’,
b0’ and b1’ to output After defining sizes of
A=B, t=0.400ns, pMOS and nMOS:
F=2.50GHZ, Delay= Idd=2.110mA
116ps Idd_avg=1.031mA
Vdd=1.20V
From node input a1’ to V_max=1.084 V
output A=B, t=0.400ns, VOL=0.021
F=2.50GHZ, Delay= 16ps
P=2.139mW

For a0, a1,b0 and b1. At

t=10.250ns, f=97.7GHZ,
Delay=220ps, 330ps,
300ps respectively,
Firstly, delay for
starting/ initiating the
delay is 1000ps