Lect # 07, 08 Floyd, CH # 06 - Code Converter, Encoder, Decoder, MUX, DMUX PDF

Code converters
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Encoders
Encoder Design
An encoder accepts an active logic level on one of its
inputs and converts it to a coded output, such as BCD or
binary.
1
• The decimal to BCD is an encoder A0
with an input for each of the ten 2
3
decimal digits and four outputs A1
that represent the BCD code for
4
the active digit. The basic logic 5 A2
6
diagram is shown. 7
8
A3
• There is no zero input because the 9
outputs are all LOW when the
input is zero.
Summary
Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with
the red lines. Thus the output is 0011.
1 0 1
A0
2 0
1
3 1
A1
4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9
Functions of
Combinational Logic
Encoder – 8-to-3 line :
– An Octal-to-binary encoder has 8 inputs (one for each octal digit) and
3 outputs that generate corresponding binary number.
Logic Implementation
Steps:
1. Analyze o/p for HIGH, e.g. check “x”
2. Develop expression for each o/p by looking on i/p
3. From exp. create a logic circuit
Floyd, Digital Fundamentals, 10th ed ilani

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Functions of
Combinational Logic
Encoder : 10-to-4-line (Decimal-to-BCD) ?
Logic
Implementation
A0 = 1 + 3 + 5 + 7 + 9
A1 = 2 + 3 + 6 + 7
A2 = 4 + 5 + 6 + 7
A3 = 8 + 9
Floyd, Digital Fundamentals, 10th ed DLD©by2009
Dr.Muhammad Taha Jilani
Pearson Education, 5
Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Encoders
The 74HC147 is an example of an IC encoder. It is has ten
active-LOW inputs and converts the active input to an
V
active-LOW BCD output. CC
(16)
This device is offers additional (11)
HPRI/BCD
1
flexibility in that it is a priority (12)
2
(13) 3
encoder. This means that if more (1) 1 (9)
4 (7)
than one input is active, the one Decimal (2) 5
2
(6)
BCD
input (3) 4 output
with the highest order decimal 6
8 (14)
(4)
7
digit will be active. (5) 8
(10) 9
(8)
74HC147
The next slide shows an application … GND
4 to 2 Priority Encoder
4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs : A1 & A0.
https://www.geeksforgeeks.org/digital-logic-encoder/
Encoders
Applications
Keyboard Encoder
R7 R8 R9
7 8 9
1
R4 R5 R6 2
3 1
4 2
5 4
6 8
4 5 6 7
8
9
R1 R2 R3
1 2 3
R0
Summary
Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input. Two simple decoders that detect the
presence of the binary code 0011 are shown. The first has an active
HIGH output; the second has an active LOW output.
A0 A0
A1 X A1 X
A2 A2
A3 A3
Active HIGH decoder for 0011 Active LOW decoder for 0011
Summary
Decoders
Assume the output of the decoder shown is a

logic 1. What are the inputs to the decoder?
A0 = 0
A1 = 1
1
A2 = 0
A3 = 1
Summary
Decoders
IC decoders have multiple outputs to decode any
combination of inputs. For example the binary-to-decimal
decoder shown here has 16 outputs – one for each
combination of binary inputs.
Bin/Dec
0 1
For the input shown, 1 1
2 1
what is the output? 3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
Do practice with some other 13 1
14 1
combinations also ! 15 1
Summary
Decoders
X/Y
0
A specific integrated circuit 1
decoder is the 74HC154 (shown as 2
3
a 4-to-16 decoder). It includes two 4
active LOW chip select lines which A0 1
5
6
must be at the active level to enable A1 2 7
A2 4 8
the outputs. These lines can be used A3 8 9
to expand the decoder to larger 10
11
inputs. 12
13
14
CS1 & 15
CS2 EN
74HC154
Summary
BCD/DEC (1)
Decoders 0
(2)
1
(3)
2
(15) (4)
BCD-to-decimal decoders accept a binary A0 1 3
coded decimal input and activate one of ten A1 (14) 2 4
(5)
A2 (13) 4 5
(6)
possible decimal digit indications. (12) (7)
A3 8 6
(9)
7
Assume the inputs to the 74HC42 (10)
8
(11)
decoder are the sequence 0101, 0110, 9
0011, and 0010. Describe the output.
74HC42
All lines are HIGH except for one active output, which is
LOW. The active outputs are 5, 6, 3, and 2 in that order.
Summary
BCD Decoder/Driver
Here the 7447A is an connected to an LED seven segment
display. Notice the current limiting resistors, required to
prevent overdriving the LED display.
+5.0 V
1.0 kW
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330 W 3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5 RBI 11 10
c c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8
Summary
BCD Decoder/Driver
The 74LS47 features leading zero suppression, which
blanks unnecessary leading zeros but keeps significant
zeros as illustrated here. The BI/RBO output is connected
to the RBI input of the next decoder.
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0
RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1
74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO
Blanked Blanked Depending on the display type, current

limiting resistors may be required.
Summary
BCD Decoder/Driver
Trailing zero suppression blanks unnecessary trailing
zeros to the right of the decimal point as illustrated here.
The RBI input is connected to the BI/RBO output of the
following decoder.
0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0
RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1
74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO
1 0 0
Decimal Blanked Blanked

point
Introduction to Gray Codes
Binary Vs Gray Codes
Summary
Code converters
There are various code converters that

change one code to another.
Binary-to-Gray Converters
Gray-to-Binary Converters
Summary
Code converters
There are various code converters that change one code to

another. Two examples are the four bit binary-to-Gray
converter and the Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
0 1 LSB
1 0
LSB
0 1
1 0
1 1 1 1
0 0
0 MSB 0 MSB
Binary-to-Gray Gray-to-Binary
Summary
Multiplexers
A multiplexer (MUX) selects one data line from two
or more input lines and routes data from the selected
line to the output. The particular data line that is
selected is determined by the select inputs.
MUX
Two select lines are shown 0
S0 0
Data 1
here to choose any of the select S1 1
four data inputs.
D0 0 Data
D1 1 output
Data
D 2
inputs D2
3 3
Which data line is selected if

S1S0 = 10? D2
Multiplexers (MUX)
Multiplexers
Functions of
Combinational Logic
Multiplexer:
• 8:1 Mux
F = X’ Y’ Z’ I0 + X’ Y’ Z I1 + X’ Y Z’ I2 + X’ Y Z I3 + X Y’ Z’ I4 +X
Y’ Z I5 + X Y Z’ I6 + X Y Z I7
Floyd, Digital Fundamentals, 10th ed DLD by Dr.Muhammad Taha Jilani

© 2009 Pearson Education, Upper Saddle River, NJ26
07458. All Rights Reserved
Multiplexers
Functions of
Combinational Logic
Exercise:
• Implement a 4:1 MUX by using 2:1 MUXs ?

Functions of
Combinational Logic
Mux as a Logic Gates
Fixed i/p

Multiplexers
Demultiplexers Summary
A demultiplexer (DEMUX) performs the opposite function from a MUX. It switches

data from one input line to two or more data lines depending on the select inputs.
Summary
Demultiplexers
A demultiplexer (DEMUX) performs the opposite function
from a MUX. It switches data from one input line to two or
more data lines depending on the select inputs.
The 74LS138 was introduced
DEMUX
previously as a decoder but can also A0
Y0
Data
serve as a DEMUX. When select A1
Y1
Y2
connected as a DEMUX, data is lines A2 Data
Y3
applied to one of the enable inputs, Y4
outputs
and routed to the selected output Enable G1
Y5
G2A
line depending on the select inputs
G2B
Y6
variables. Note that the outputs are Y7
active-LOW as illustrated in the 74LS138

following example…
Summary A0
A1
Demultiplexers
A2
Determine the outputs, given the
inputs shown. G1
G2A LOW
The output logic is opposite to the input G2B LOW
because of the active-LOW convention. (Red
shows the selected line). Y0
DEMUX Y1
Y0
Data A0 Y2
Y1
select A1
lines Y2 Y3
A2 Data
Y3
Y4
outputs Y4
Enable G1
Y5
G2A Y5
inputs Y6
G2B Y6
Y7
74LS138 Y7
Summary
Parity Generators/Checkers
Parity is an error detection method that
uses an extra bit appended to a group of
bits to force them to be either odd or
even. In even parity, the total number of
ones is even; in odd parity the total
number of ones is odd.
The ASCII letter S is 1010011. Show the parity

bit for the letter S with odd and even parity.
S with odd parity = 11010011

S with even parity = 01010011
Summary
Parity Generators/Checkers
The 74LS280 can be used to generate a parity bit or to
check an incoming data stream for even or odd parity.
Checker: The 74LS280 can test codes with up
to 9 bits. The even output will normally be
HIGH if the data lines have even parity; (8)
A
otherwise it will be LOW. Likewise, the odd (9)
B
(10)
output will normally be HIGH if the data lines (11)
C
(5)
D
have odd parity; otherwise it will be LOW. Data (12) S Even
E (6)
inputs (13) S Odd
F
Generator: To generate even parity, the parity (1)
G
(2)
bit is taken from the odd parity output. To (4)
H
I
generate odd parity, the output is taken from
the even parity output. 74LS280
Selected Key Terms
Full-adder A digital circuit that adds two bits and an input

carry bit to produce a sum and an output carry.
Cascading Connecting two or more similar devices in a
manner that expands the capability of one device.
Ripple carry A method of binary addition in which the output
carry from each adder becomes the input carry of
the next higher order adder.
Look-ahead A method of binary addition whereby carries from
carry the preceding adder stages are anticipated, thus
eliminating carry propagation delays.
Selected Key Terms
Decoder A digital circuit that converts coded information into

a familiar or noncoded form.
Encoder A digital circuit that converts information into a
coded form.
Priority An encoder in which only the highest value input
encoder digit is encoded and any other active input is ignored.
Multiplexer A circuit that switches digital data from several input
(MUX) lines onto a single output line in a specified time
sequence.
Demultiplexer A circuit that switches digital data from one input line
(DEMUX) onto a several output lines in a specified time
th
Floyd, Digital Fundamentals, 10 ed
sequence. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
1. For the full-adder shown, assume the input bits are as
shown with A = 0, B = 0, Cin = 1. The Sum and Cout will be
a. Sum = 0 Cout = 0
S S Sum
b. Sum = 0 Cout = 1 0 A S A S
c. Sum = 1 Cout = 0 0 B Cout B Cout
d. Sum = 1 Cout = 1 1
Cout
© 2008 Pearson Education
2. The output will be LOW if
a. A < B A1
B1
b. A > B A2 Output
B2
c. both a and b are A3
correct B3
A4
d. A = B B4
3. If you expand two 4-bit comparators to accept two 8-bit
numbers, the output of the least significant comparator is
a. equal to the final output
b. connected to the cascading inputs of the most
significant comparator
c. connected to the output of the most significant

comparator
d. not used
4. Assume you want to decode the binary number 0011 with
an active-LOW decoder. The missing gate should be
a. an AND gate A0
A1 X
b. an OR gate ?
A2
c. a NAND gate
A3
d. a NOR gate
5. Assume you want to decode the binary number 0011 with
an active-HIGH decoder. The missing gate should be
a. an AND gate A0
A1 X
b. an OR gate ?
A2
c. a NAND gate
A3
d. a NOR gate
7. The decimal-to-binary encoder shown does not have a
zero input. This is because
1
a. when zero is the input, A0
all lines should be LOW 2
3
A1
b. zero is not important
4
5 A2
c. zero will produce 6
7
illegal logic levels 8
A3
9
d. another encoder is used
for zero
8. If the data select lines of the MUX are S1S0 = 11, the
output will be
a. LOW MUX
S0 0
b. HIGH Data
1
select S1
c. equal to D0 D0 0 Data
D1 1 output
Data
d. equal to D3 D 2
inputs D2
3 3
9. The 74138 decoder can also be used as
a. an encoder
b. a DEMUX
c. a MUX
d. none of the above
10. The 74LS280 can generate even or odd parity. It can
also be used as
a. an adder
b. a parity tester
c. a MUX
d. an encoder
Answers:
1. c 6. d
2. c 7. a
3. b 8. d
4. c 9. b
5. a 10. b

Lect # 07, 08 Floyd, CH # 06 - Code Converter, Encoder, Decoder, MUX, DMUX PDF

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Lect # 07, 08 Floyd, CH # 06 - Code Converter, Encoder, Decoder, MUX, DMUX PDF

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Code converters

Floyd, Digital Fundamentals, 10th ed ilani

Assume the output of the decoder shown is a

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

Blanked Blanked Depending on the display type, current

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

Decimal Blanked Blanked

Binary Vs Gray Codes

There are various code converters that

There are various code converters that change one code to

Which data line is selected if

Floyd, Digital Fundamentals, 10th ed DLD by Dr.Muhammad Taha Jilani

Floyd, Digital Fundamentals, 10th ed DLD by Dr.Muhammad Taha Jilani

Floyd, Digital Fundamentals, 10th ed DLD by Dr.Muhammad Taha Jilani

A demultiplexer (DEMUX) performs the opposite function from a MUX. It switches

active-LOW as illustrated in the 74LS138

The ASCII letter S is 1010011. Show the parity

S with odd parity = 11010011

Full-adder A digital circuit that adds two bits and an input

Decoder A digital circuit that converts coded information into

c. Sum = 1 Cout = 0 0 B Cout B Cout

c. connected to the output of the most significant

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