IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO.

1, FEBRUARY 2010 19

Digital Heart-Rate Variability Parameter

Monitoring and Assessment ASIC
Wansuree Massagram, Noah Hafner, Mingqi Chen, Luca Macchiarulo, Victor M. Lubecke, Senior Member, IEEE,
and Olga Boric-Lubecke, Senior Member, IEEE

Abstract—This paper describes experimental results for an intervals in internal memory, and calculates the RR interval his-
application-specific integrated circuit (ASIC), designed for digital togram. The very-high definition language (VHDL) simulation
heart rate variability (HRV) parameter monitoring and assess- in [9] showed that the design was able to detect R waves within
ment. This ASIC chip measures beat-to-beat (RR) intervals and
stores HRV parameters into its internal memory in real time. A millisecond accuracy after 2 s of initial setup time for ten se-
wide range of short-term and long-term ECG signals obtained lected electrocardiography (ECG) traces obtained from Phys-
from Physionet was used for testing. The system detects R peaks ionet’s PTB Diagnostic ECG Database [10]. This integrated cir-
with millisecond accuracy, and stores up to 2 min of continuous cuit (IC) was designed in a low-cost 0.5- m CMOS technology,
RR interval data and up to 4 min of RR interval histogram. with an area of less than 3 3 mm and a measured dynamic
mm
The prototype chip was fabricated in a 0.5- m complementary
metal–oxide semiconductor technology on a 3 3 2 die power consumption of 10 W. The chip’s measured leakage
area, with a measured dynamic power consumption of 10 W current is 2.62 nA. The advantages of using the ASIC include
and measured leakage current of 2.62 nA. The HRV monitoring significant power savings compared to even a low-powered mi-
system including this HRV ASIC, an analog-to-digital converter, crocontroller with similar functionality. An HRV monitoring
and a low complexity microcontroller was estimated to consume system, including an HRV ASIC, an ADC, and a low-com-
32.5 V, which is seven times lower power than a stand-alone
microcontroller performing the same functions. Compact size, low plexity microcontroller would use less power (by a factor of
cost, and low power consumption make this chip suitable for a seven) than one by using a low-power microcontroller for all
miniaturized portable HRV monitoring system. functions. This chip detected the RR intervals of more than 6
Index Terms—Biomedical measurements, biomedical mon-
ms accurately when tested against a wide range of signals from
itoring, electrocardiography, heart-rate variability (HRV), Physionet database. In addition, the RR intervals were correctly
beat-to-beat (RR) interval. sorted into histogram bins, thus providing a precise HRV trian-
gular index.
Sections II–VI present the HRV ASIC architectural design,
I. INTRODUCTION system power considerations, and experimental chip test results
by using short-term and long-term ECG data as well as Doppler
EART rate variability (HRV) is becoming an important radar data.
H diagnostic tool for a number of medical conditions, in-
cluding diabetes [1], sleep apnea [2], and cardiovascular disease II. HRV ASIC DESIGN
[3]. In addition, HRV has been used for psychological studies of
stress [4] and for the evaluation of impact of therapy [5]. HRV HRV time-domain measures, which can be simply calculated
measurements are traditionally calculated by using embedded from the RR interval data or the instantaneous heart rate, in-
software [6]–[8]. A compact, low-power, real-time HRV assess- clude the measures of the mean of RR intervals (mean RR),
ment system could further enable and expand HRV diagnostic the standard deviation of normal RR intervals (SDNN), and the
applications. An HRV ASIC chip design for heart-rate extrac- root-mean-square (rms) differences of successive RR intervals
tion was proposed in [9]. This ASIC extracts beat-to-beat (RR) (RMSDD) [1]. Another time-domain measure that proves to be
intervals by using a simple peak detection algorithm, stores RR useful to identify heart conditions is the triangular index, which
can be extracted on the basis of a histogram of RR interval
data. The design presented here focuses on this HRV param-
Manuscript received December 22, 2008; revised April 20, 2009. Current ver- eter extraction in real time. This chip could enable HRV system
sion published January 27, 2010. This work was supported in part by the Na-
tional Science Foundation under Grants #ECS0428975 and #ECS0702234. This miniaturization for ambulatory HRV monitoring, by processing
paper was recommended by Associate Editor T. Le. and storing RR intervals, or serve as a preprocessing front end
W. Massagram is with the Department of Computer Science and Informa-
tion Technology, Naresuan University, Phitsanulok 65000, Thailand (e-mail:
that could allow a higher capability microcontroller with clock-
wansureem@nu.ac.th). gated random-access memory (RAM) for data storage to spend
N. Hafner, L. Macchiarulo, V. M. Lubecke, and O. Boric-Lubecke are most of the time in a low-power sleep mode. Fig. 1 shows the
with the Electrical Engineering Department, University of Hawaii, Hon-
olulu, HI 96822 USA (e-mail: nmh+ieee@nomh.org; lucam@hawaii.edu;
proposed HRV monitoring system by using an ADC, an HRV
lubecke@ieee.org, olga@ieee.org). ASIC, and a low-complexity microcontroller. The ECG signal
M. Chen is with the Department of Electrical and Computer Engineering, is digitized into a 16-b signal and sent to the HRV ASIC. A
University of Florida, Gainesville, FL 32611 USA (e-mail: mingqi@ufl.edu). microcontroller manages the timing of the ADC, data transfer
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. from the chip, and output of the heart rate and derivative data
Digital Object Identifier 10.1109/TBCAS.2009.2035555 via a built-in display.
1932-4545/$26.00 © 2010 IEEE

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20 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 1, FEBRUARY 2010

A. Peak Detector and Interval Counter

The peak detector scans the ECG signal for R waves and con-
verts them into narrow square pulses in three following steps:
1) setup a threshold value to eliminate other peaks by comparing
the input data with the threshold value within a time window;
2) determine the position of the peak by looking for the max-
Fig. 1. System block diagram of the HRV ASIC with an ADC and microcon- imum value in this window; and 3) generate a square pulse after
troller with a seven-segment display. obtaining the position of the peak. The threshold value depends
on the dc level and amplitude of the input ECG and is thus un-
known at the time of the experiment. Therefore, the peak de-
tector must initialize an adjustable threshold to accommodate
variations in the input signals.
The initial threshold level is established from the sum
of three-quarter of maximum value and a quarter
of minimum value during the first two thousand
samples

(1)

A simple finite state machine determines R waves and updates

the threshold by adding the difference of the amplitude
between the current peak and the previous peak
to the current threshold :

sample (2)

This adjustment to the threshold allows the peak detector to

accommodate baseline drift in the input signal.

B. Beat-to-Beat Interval Memory

The interval memory consists of a 128 8 register files. With
a 1-kHz sampling rate, 11-b RF memory would provide enough
storage for an interval as long as 2047 ms, or approximately
30 b/min, with 1-ms resolution. However, by sacrificing the
three least-significant bits from 11-b memory, the 8-b memory
storage limits the interval accuracy within 7 ms, which is ade-
quate for typical HRV measurements [11].
Fig. 2. HRV ASIC block diagram. The chip detects the R peaks from the digi- The 128 intervals would contain slightly more than 2 min of
tized ECG signal, stores beat-to-beat interval data, and categorizes the interval interval data, assuming an average heart rate of 60 b/min. The
data into a histogram.
memory is designed to be continuously overwritten after it is
full. The memory is accessed through a simple protocol that
makes the all chip appear as a memory-mapped device. By using
The HRV ASIC is designed to process an output of the ECG a CMOS process with smaller gate length and memory genera-
digitized with 16 b. The chip was designed to operate with an tors, this design can be easily extended to record RR intervals
external clock frequency of 1 kHz, but is capable of operating over a 24-h period with 1-ms accuracy [12].
at other speeds. The chip performs the following four functions:
1) the peak detector receives a digitized ECG input and produces
C. Histogram Sorter and Memory
an output pulse length of one clock cycle each time it identi-
fies an R peak of a heart signal. This pulse is used to reset the The histogram sorter categorizes intervals into 16 different
counter to start a new interval computation; 2) the beat-to-beat groups: the first category represents the RR intervals of less than
interval counter counts the number of clock periods between two 0.4 s, the second and third categories represent the RR intervals
R peaks and writes the interval length into the 128 8 register from 0.4 to 0.6 and 0.6 to 0.7 s, the fourth through thirteenth
file (RF); 3) the comparator categorizes the interval data into 16 categories represent the RR intervals from 0.7 to 0.9 s with a
different histogram bins and increments the appropriate bin in 20-ms increment, the 14th and 15th categories represent the RR
the 16 8RF; and 4) the control unit manages the data transfer intervals from 0.9 to 1 and 1 to 1.2 s, and the last category rep-
after receiving an external command. A detailed block diagram resents the RR intervals of more than 1.2 s. The fourth through
of the digital HRV ASIC design is illustrated in Fig. 2. thirteenth categories have finer resolutions since we expect the

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MASSAGRAM et al.: DIGITAL HEART-RATE VARIABILITY PARAMETER MONITORING AND ASSESSMENT ASIC 21

RR intervals in these groups to vary the most. The triangular

index can be extracted from the histogram by dividing the total
number of RR intervals with the height of the histogram of all
intervals.
The classifications of the sorter are stored in the histogram
memory, consisting of 16 bins each with an 8-b counter. With a
60-b/min heart rate, the 1-Hz bin will overflow after 255 sam-
ples, or 4 min, 15 s. This results in each bin containing the total
number of beats in the appropriate range modulus 256. The his-
togram memory therefore does not contain all of the requisite in-
formation to recover the heart rate, but with periodic readouts,
the heart rate can be easily tracked. Comparing the histogram
and interval storage methods, the histogram is capable of storing
longer datasets, with somewhat reduced absolute accuracy—it
could be viewed as a simple form of lossy compression.
Comparing the two storage methods, the histogram memory
does not retain the time ordering of the samples and selectively
drops some of the accuracy while the interval memory retains
Fig. 3. Digital HRV ASIC fabricated in 0.5-m CMOS technology. The total
the ordering of the samples and drops 3 b of resolution from 2
area of the chip is 2.94 2.94 mm . The input pins are located on the top and
each interval. Considering that the histogram can store distribu- right, the output pins on the left, and the memory control pins are on the bottom
tion information more than twice the number of samples as the of the chip.
interval memory and it uses much less space, it is a compelling
compressing solution for this application. One possible example TABLE I
of this would be reconfiguring the 128 8 interval memory CHIP SPECIFICATIONS
storage for use instead of the histogram. Splitting 128 8 as
two smaller 64 8 areas and combining them for an effective
64 16 memory unit, the histogram could store about 18 h of
data, with a 60-b/min signal, before filling. Since the number
of bins would be increased fourfold, the accuracy would also
improve. The largest drawback to this is the lack of timing in-
formation. TABLE II
CURRENT CONSUMPTION OF FABRICATED ASICS AT MULTIPLE CLOCK SPEEDS
D. Control Unit
Data from both memories are transferred via the control unit.
A signal for requested memory; 0 for interval and 1 for his-
togram, along with memory address are sent externally to the
control unit to manage the exchange of data. The control unit
also resets the entire system when the reset signal is high.
operation was tested with the clock frequency from 250 Hz
to 100 kHz, to accommodate processing of prerecorded traces
III. ASIC IMPLEMENTATION
sampled at 250 Hz, and to speed up the testing of longer test
The photograph of the chip, fabricated in a 0.5- CMOS tech- signals.
nology, is shown in Fig. 3. An RTL implementation of the peak The power consumption of fabricated ASICs was measured
and HRV detection algorithm described before has been de- with a Keithley 2400 source meter and an Agilent 33220A
scribed in synthesizable VHDL. The gate-level standard cell de- function generator. The source meter was set to source voltage
sign was then generated by Synopsys Design Compiler by using V) to measure current (with a 10-mA limit). The function
a 0.5- m standard cell library [13] for an AMIS 0.5- m CMOS generator was first set to 1 kHz, then to 10 kHz and 100 kHz.
process. The placement and routing were performed by Cadence With other inputs grounded, each IC was connected to V,
Chip Encounter. The final GDS2 file was generated and checked ground, reset, and clock. Reset was normally connected to
by Cadence Virtuoso. The chip has 7222 gates in a core area ground, and switched to V when asserted. The clock was
of 2.32 2.32 mm and a total area of 2.94 2.94 mm . The set to 1 kHz, 10 kHz, and 100 kHz, and the power usage
chip was packaged in a DIP40 package. The interval memory was measured for each speed without an intervening power
is the largest component, taking approximately 72% of the core cycle/reset. Each IC was reset after the power was applied
area (slightly less than 1 mm for just the memory elements and before the first measurement. Table II shows the results
and about 3 mm used for addressing logic, routing, and place- from the power consumption tests for three fabricated ICs. The
ment). The chip leakage current was measured to be 2.62 nA indicated current at the normal operation clock of 1 kHz is
with the SMU2400 Keithley source meter [14]. While the chip approximately 2 A, corresponding to a power consumption of
was designed to operate with a clock frequency of 1 kHz, chip 10 W with a 5-V power supply.

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22 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 1, FEBRUARY 2010

IV. EXPERIMENTAL RESULTS

The HRV ASIC performance was verified by using a wide
range of ECG signals from the Physionet database [10]. Both
short-term (60-s) and long-term (24-h) signals were used to test
the chip functionality and accuracy. A PC-based test setup with
data-acquisition capability was developed to provide 16-b ECG
data at the input of the chip, and then read and display chip
outputs automatically.
The test setup, partially shown in 4(a), includes a computer
with a National Instrument data-acquisition card (NI PCI-6259),
two shield cables (NI SHC68-68-EPM) and terminal blocks (NI
CB-LPR), a 5-V power supply, and the HRV ASIC. The soft-
ware for testing this chip was written in LabVIEW. The soft-
ware read in the data from previously downloaded Physionet
ECG files, then converted each lead signal into 16-b unsigned
data to be sent to the chip. The software can also vary the system
clock frequency. The chip received the digitized input from the
computer, and processed and stored the HRV parameters. After
sending out the ECG data, the program read the memory con-
tents, and displayed the peak indicator, the interval data, and the
histogram data on the screen.
A typical test run involved the user selecting the data trace
and initiating the test. The software would then locate the file,
perform the file format and size check, read in the appropriate
data, and use the data to test the chip. The typical ECG input
voltage was 16 mV with compensated offset voltage up to 300
mV. The software converts inputs into 16-b (0 to 65535) num-
bers. After sending out the entire trace, the software would then
read the calculated data stored in the memory, and display the
test trace, the beat indicator, and the memory data. The graph-
ical user interface is shown in Fig. 4(b).
The test experiments were divided into two categories: 1)
short-term ECG tests and 2) long-term ECG tests. In short-term
ECG tests, 1-min PTB diagnostic traces [10], sampled at 1 kHz
with 16-b resolution, were used. The accuracy of the peak de-
tector and memories is discussed for short-term ECG tests. In
long-term ECG tests, due to the unavailability of high-resolu-
tion traces, the long-term ST database traces [10], which were
sampled at 250 Hz with 12-b resolution, were used. The tests
took one hour to run at a higher clock rate (24 h of 250-Hz data Fig. 4. Photograph of the terminal blocks and the HRV IC in the test system
setup. (a), Data acquisition graphical user interface of the digital HRV IC. (b)
at 6 kHz use 1 h).The results from the peak detector will be Custom-designed LabView software supplies 16-b ECG data to the chip, then
discussed. reads the calculated data stored in the memory, and displays the test trace, the
beat indicator, and the memory data.
A. Short-Term ECG Tests
Each PTB diagnostic ECG record [10] contains 15 simulta-
neously measured signals: 12 conventional leads (i, ii, iii, avr, with large dc variation. Test software reads in the peak indi-
avl, avf, v1, v2, v3, v4, v5, v6) and 3 Frank lead ECGs (vx, cator output (squares in Fig. 5) from the chip, showing that all
vy, vz). Each signal is digitized at 1000 samples/s, with 16-b R waves are detected correctly after the 2 000 samples of the
resolution over a range of 16.384 mV. The initial testing used initialization period. The peak detector indicated the R wave ap-
the first minute of the PTB traces. For the VHDL simulation peared precisely eight clock cycles after the peak was detected
in [9], one well-formed and low-noise signal from each ECG as illustrated in Fig. 6.
record was selected. For the experimental chip testing, since the The summary of the percentage of detected R peaks for ten
test system has greater and faster capability, more signals, in- analyzed ECG records is shown in Table III. In normal ECG
cluding some which are less well-formed and exhibited exces- recordings, traces “avr” and “v1” normally exhibit different
sive noise, were tested. Some of these traces contained a variety waveform patterns—typically, low PQRST complexes or an
of noise and baseline drift. The peak detector was able to tol- inverted signal. Since these patterns differ from those in the
erate the baseline drift due to its adjustable threshold algorithm. HRV that the ASIC algorithm was designed for, tests were not
Fig. 5 displays the ECG input from patient01/s0014lre/v3 [10] conducted with traces from these leads. Traces “iii” contained

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MASSAGRAM et al.: DIGITAL HEART-RATE VARIABILITY PARAMETER MONITORING AND ASSESSMENT ASIC 23

TABLE III
PERCENTAGE OF DETECTED R WAVES FROM TEN SHORT-TERM PTB DIAGNOSTIC ECG TRACES

TABLE IV
RMSE [MS] OF RR INTERVALS OF TEN SHORT-TERM PTB DIAGNOSTIC ECG
2
TRACES EXTRACTED FROM HRV IC 128 8 INTERVAL MEMORY

Fig. 5. Large dc variation ECG trace patient01/s0014lre/v3. The peak indicator

is the output from the chip which indicated where the R waves were.
on a computer. The rms error (RMSE) of the RR intervals for
each signal with 100% detection rate is indicated in Table IV.
The average RMSE of RR intervals in Table IV was 4.178 ms,
and the maximum RMSE was less than 6 ms.
The reference RR intervals were generated from the same
traces via a software peak detector and counter. The software,
implemented in MATLAB, would take as inputs: an ECG trace,
and an estimated period. It would then use the period to define
the window size while searching for the peak. The RMSE is
then calculated by comparing the RR interval output from the
chip with the reference.
An example of a histogram, shown in Fig. 7, was extracted
from the histogram memory data of patient03/s0017lre v4, v5,
v6, and vx signals. It indicates small discrepancy in v4, v5,
Fig. 6. Peak indicator appeared eight clock cycles after the R wave. This trace
was obtained from the PTB file patient01/s0014re/v3. v6, and vx due to the small variations of the R waves in each
signal. The HRV triangular index measurement is calculated
from the total number of RR intervals divided by the number
too much noise and more than one local maximum at R waves. of RR intervals in the maximum bin. The HRV chip has 16
The results are shown only for the cases where more than 95% bins, each with 8 b, which is equivalent to the total 128 b of
of the R peaks were detected. As indicated in Table III, each storage space. The differing bin widths allowed longer traces
patient’s record has at a minimum one trace and, on average, to be recorded since more bins would allow for less space in
four traces with a 100% detection rate. While the peak detector each bin. The calculated HRV triangular indexes of all ten ECG
was able to withstand large baseline drift and a high amount traces are shown in Table V. From the particular histogram of
of noise, it was not able to determine R peaks correctly for patient03/s0017lre data in Fig. 7, the difference in the 840–860
inverted waveforms (S wave amplitude larger than R wave bin (maximum) clearly translates to the triangular index (3.136
amplitude) or those without high PQRST complexes. versus 2.875). It is also evident that all of the signals are very
The intervals were stored using eight bits—the lowest three close to each other (max deviation of 2 samples per bin), even
from the counter were dropped. This is a source of inaccu- if they are not exactly the same. Table VI shows the percentage
racy—up to seven samples in the worst case. To this, the inter- accuracy in triangular indexes generated from the data down-
vals stored in memory were compared with intervals calculated loaded from the HRV chip compared with the triangular index

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24 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 1, FEBRUARY 2010

TABLE V
HRV TRIANGULAR INDEX MEASUREMENTS OF TEN SHORT-TERM PTB DIAGNOSTIC
ECG TRACES EXTRACTED FROM HRV IC HISTOGRAM MEMORY

of 60 b/min. Further memory tests were performed with artifi-

cial signals generated to have specific intervals and durations.
This allowed close inspection of the memory contents immedi-
ately before and after filling. Though the RR interval memory
was not saved after overwriting, it worked flawlessly by reusing
the same storage space. When the memory is filled up, it starts
overwriting again at address 0. The histogram memory was
tested in a similar manner. Each histogram bin correctly counts
up to 255 intervals.

B. Long-Term ECG Tests

The reliability of the peak detector was the main focus of the
long-term ECG tests. Two ECG traces from long-term ST data-
base traces [10]: s20011/ML2 and s20021/ML2 were tested.
Fig. 7. Histogram of ECG trace patient03/s0017lre/v4, v5, v6, and vx extracted
The peak detector accuracy for these is shown in Table VI.
from HRV-SoC histogram memory. The trace S20011/ML2 contains the highest detection rate of
99.78%.
TABLE VI The long-term tests would have taken an excessive amount of
PERCENTAGE ACCURACY IN THE TRIANGULAR INDEX OF TEN SHORT-TERM
PTB DIAGNOSTIC ECG TRACES EXTRACTED FROM HRV IC HISTOGRAM time to complete, if run in real time. The HRV chip worked with
MEMORY IN COMPARISON WITH THE TRIANGULAR INDEX REFERENCE signals sampled at 250 Hz even when the clock frequency was
raised to 10 kHz. This allowed long-term tests to run by using
2.5% of the time they would have otherwise required.

C. Doppler Radar Signal Tests

The ASIC was also tested with a prerecorded heart signal
obtained from a single-channel output of a Doppler radar de-
scribed in [15]. The subject’s heart signal was collected simul-
taneously with a finger-pulse sensor for reference. The sub-
ject held his breath for this 30-s-long trace. The HRV ASIC
was used to extract heart intervals from the band-pass filter
Doppler radar output, using the same setup as described before
TABLE VII
PERCENTAGE OF CORRECTLY DETECTED R WAVES IN ONE
[Fig. 4(a))]. Fig. 8 shows the screen capture of the test with
HOUR FROM THREE LONG-TERM ST ECG TRACES Doppler signal, with the squares indicating the timing of the
Doppler heart signal peaks. When compared to the finger-pulse
reference, the chip extracted the RR intervals with the RMSE of
40.23 ms.

generated from the MATLAB reference for each signal. The V. POWER CONSUMPTION CONSIDERATIONS
index generating software used the same parameters as the HRV In small portable systems, power consumption is a signifi-
chip. The average of the percentage accuracy (each calculated as cant concern because the available energy is limited due to size
) of histogram from these ECG traces and convenience. In this section, the estimated power consump-
was 96.44%. tion of the proposed ASIC-based HRV system will be compared
The interval memory has space for storing 127 inter- with a possible alternative solution based on a low-power mi-
vals—enough for about two minutes of recording at an average crocontroller. The two designs considered are a single-chip so-

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MASSAGRAM et al.: DIGITAL HEART-RATE VARIABILITY PARAMETER MONITORING AND ASSESSMENT ASIC 25

32.5 W to operate, which is a factor of seven less power

than using the microcontroller alone, and several orders of
magnitude less power than the field-programmable gate-array
(FPGA) implementation. The chip was tested using a short-term
PTB database and long-term ST database from Physionet. The
computer-based test system, using the PCI card and LabView
software, was developed to test chip functionality. Each of the
short-term 10 PTB ECG records has, at a minimum, one trace
and, on average, four traces with a 100% R peak detection. The
RMSE of each 100% detection signal is less than 6 ms. The
triangular indexes extracted from the histogram memory of
the chip have more than 95% accuracy. One-hour experiments
show that the chip can correctly detect the peaks with accuracy
Fig. 8. Doppler signal with detected peaks.
as high as 99.78%. It was also shown that this chip can be
used for accurate detection of much less “sharp” Doppler radar
heart signals. If this chip is implemented in a more advanced
lution using a microcontroller with a built-in analog-to-digital
CMOS process, 24-h memory could be fit onto the IC without
converter (ADC), and a multichip solution using a stand-alone
increasing the overall size. This HRV chip implementation
ADC, the HRV ASIC, and a microcontroller.
could enable future HRV system miniaturization.
Considering the power consumption for the one-chip solution
using a low-power microcontroller (Microchip 18LF4580 [16]), ACKNOWLEDGMENT
since the microcontroller would be constantly on, this system
The authors would like to thank the MOSIS service for pro-
would require 232 W to process the data; 180 W for its ADC
viding IC fabrication as well as J. Grad and J. E. Stine [13] for
and 52 W for the assessment algorithm. This power figure was
providing the standard cell libraries.
derived by writing a short code segment to help estimate the req-
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26 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 1, FEBRUARY 2010

[15] S. Yamada, M. Chen, and V. Lubecke, “Sub- signal power doppler W Victor M. Lubecke (S’86–M’86–SM’98) received
radar heart rate detection,” in Proc. Asia–Pacific Microw. Conf., 2006, the B.S.E.E. degree from the California Polytechnic
pp. 51–54. Institute, Pomona, in 1986, and the M.S. and Ph.D.
[16] Microchip 18lf4580. [Online]. Available: http://ww1.microchip.com/ degrees in electrical engineering from the California
downloads/en/devicedoc/39637c.pdf Institute of Technology, Pasadena, in 1990 and 1995,
[17] Analog Device 7467. [Online]. Available: http://www.analog.com/up- respectively.
loadedfiles/data sheets/ad7466 7467 7468.pdf Prior to joining the Department of Electrical Engi-
neering, University of Hawaii at Manoa, Honolulu, as
an Associate Professor in 2003, he was with Bell Lab-
oratories, Lucent Technologies, where his research
Wansuree Massagram received the B.S. and M.S. focused on sensing and monitoring technologies for
degrees in electrical and computer engineering from biomedical and industrial applications and on microelectromechanical systems
Carnegie Mellon University, Pittsburgh, PA, and the (MEMS) and 3-D wafer-scale integration technologies for wireless and optical
Ph.D. degree from the University of Hawaii at Manoa communications. Previously, he was with the NASA Jet Propulsion Laboratory
in 2008. from 1987 through 1996 and the Institute for Physical and Chemical Research
Her research topic was on the feasibility of (RIKEN), Sendai, Japan, from 1996 through 1998, where his research involved
long-term cardiopulmonary monitoring via Doppler remote sensing and space communications applications and related MEMS and
radar. She joined the Department of Computer terahertz technologies. His current research interests include sense-through-the-
Science and Information Technology at Naresuan wall and other remote sensing and imaging technologies, biomedical applica-
University, Thailand, in 2008. tions, sensor networks, MEMS, heterogeneous integration, and microwave/ter-
ahertz radio. He holds 4 U.S. patents, with several more pending.
Dr. Lubecke received the Microwave Prize for best paper at the Asia Pa-
cific Microwave Conference in 2000, and coauthored student competition pa-
pers which were selected for Honorable Mention at IMS-2001, Third Place at
Noah Hafner received the B.S. and M.S. degrees in EMBS-2001, First Place at IMS-2003, and competition finalist at RWS-2006.
electrical and computer engineering from Carnegie He was also co-recipient of the Emerging Technology Award at TechConnect
Mellon University, Pittsburgh, PA, in 2002 and 2003, 2007, and cofounded a related startup company which is now Kai Sensors. He
respectively. is a Distinguished Microwave Lecturer (2006–2008) of the IEEE Microwave
Prior to joining the doctoral program at the Theory and Techniques Society, and serves on the Technical and Steering Com-
University of Hawaii at Manoa, Honolulu, he served mittees for various IEEE and SPIE symposia.
as the Test Engineer at Akustica, Inc, a Pittsburgh,
PA-based startup where he developed hardware
and software for testing and characterizing the
microelectromechanical-systems microphones from
Olga Boric-Lubecke (S’90–M’90–SM’01) received
wafers to packaged units. Previously, he was with
the B.Sc. degree in electrical engineering from the
National Instruments, Inc, focusing on the development of improved SCC
University of Belgrade, Belgrade, Yugoslavia, in
hardware modules. His research areas include biological sensing and radar
1989, the M.S. degree in electrical engineering from
characterization as well as low-cost, mimo, multistatic, passive radar systems
the California Institute of Technology, Pasadena, in
and networked radar sensors.
1990, and the Ph.D. degree in electrical engineering
from the University of California at Los Angeles, in
1995.
Prior to joining the Department of Electrical Engi-
Mingqi Chen (S’05) received the B.S. degree neering, University of Hawaii at Manoa, Honolulu,
in electrical engineering from Peking University, where she is currently an Associate Professor, she
Beijing, China, in 2003, the M.S. degree in elec- was a Member of the Technical Staff at Bell Laboratories, Lucent Technolo-
trical engineering from University of Hawaii at gies, Murray Hill, NJ, where she conducted research in radio-frequency (RF)
Manoa, Honolulu, in 2006, and is currently pur- integrated-circuit (IC) technology and biomedical applications of wireless sys-
suing the Ph.D. degree at the University of Florida, tems. From 1996 to 1998, she was a Visiting Research Scientist with the Insti-
Gainesville, working on a 20-GHz ultrawideband tute of Physical and Chemical Research (RIKEN), Sendai, Japan. From 1995
receiver. to 1996, she was a Resident Research Associate with the National Aeronautics
In 2005, he held an internship position with Bell and Space Administration (NASA) Jet Propulsion Laboratory (JPL), Pasadena.
Laboratories, Murray Hill, NJ, where he worked on She has authored or coauthored many journal and conference papers, and her re-
the cellular RF signal inbuilding distribution system. search has been featured in various newspapers, magazines, and radio programs.
His main research interests include analog/RF and digital integrated-circuit Her current research interests include silicon RF ICs, high-frequency ICs, and
design. biomedical applications.
Prof. Boric-Lubecke serves on Technical Program and Steering Committees
for various IEEE and SPIE symposia. She coauthored student competition pa-
pers which were selected for Honorable Mention at IMS-2001, Third Place at
Luca Macchiarulo received the M.Sc. and Ph.D. de- EMBS-2001, First Place at IMS-2003, and competition finalist at RWS-2006.
grees from Politecnico di Torino, Torino, Italy. She was also co-recipient of the Emerging Technology Award at TechConnect
After a year of postdoctoral research at the Univer- 2007, and co-founded a related startup company which is now Kai Sensors.
sity of California at Santa Barbara, where he worked
on layout-logic synthesis for high throughput and
design, he went to Politecnico di Torino where he
was Researcher and Lecturer and worked in the
group on low-power design and layout synthesis,
and subsequently worked on injection techniques
and throughput-enhancing logic and physical design.

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