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1, FEBRUARY 2010 39

High-Power Integrated Stimulator Output Stages

With Floating Discharge Over a Wide Voltage
Range for Nerve Stimulation
Peter J. Langlois, Andreas Demosthenous, Senior Member, IEEE, Ioannis Pachnis, Member, IEEE, and
Nick Donaldson

Abstract—Two integrated nerve stimulator circuits are de- not been demonstrated for chronic use. Electrode cuffs have
scribed. Both generate passively charge-balanced biphasic been used in patients for chronic recording [4] and although
stimulating pulses of 1 to 16 mA with 10- s to 1-ms widths from the signal amplitudes are very small (microvolts), with careful
6- to 24-V supplies for implanted book electrodes. In both circuits,
the electrodes are floating during the passive discharge anywhere design of the amplifier and advanced signal processing, they
within the range of the power rails, which may be up to 24 V. The can be useful. Hansen et al. [5] have demonstrated a foot-drop
first circuit is used for stimulation only. It uses a floating depletion stimulator which can be synchronized to the gait cycle in stroke
transistor to enable continuous discharge of the electrodes, except patients from the signal recorded by a tripolar cuff on the sural
when stimulating, without using power. The second circuit also nerve.
allows neural signals to be recorded from the same tripole. It
uses a modified floating complementary metal–oxide semicon- We are working on devices that have electrodes on the lumbo-
ductor (CMOS) discharge switch capable of operating over a sacral nerve roots which can be used to restore lower-body func-
range beyond the gate-to-source voltage limits of its transistors. tion to paraplegics after spinal cord injury. Jezernik et al. [6]
It remains off for long periods using no power while recording. have suggested that in these patients, urinary incontinence can
A 0.6- m silicon-on-insulator CMOS technology has been used. be prevented by stimulation to inhibit bladder contractions when
The measured performance of the circuits has been verified using
multiple tripoles in saline. they are detected from the nerve signal (conditional neuromod-
ulation). With several tripoles in electrode books that trap nerve
Index Terms—Complementary metal–oxide semiconductor
roots in the cauda equine, the arrangement shown in Fig. 1(a)
(CMOS) switch, depletion transistor, floating discharge,
high-power stimulator, implantable circuits, neural recording, (only three tripoles shown) leads to crosstalk due to currents
passive discharge, silicon-on-insulator (SOI). flowing to the stimulating cathode from anodes of other tripoles
[7]. Therefore, it is necessary to have anode switches as well
as cathode switches as shown in Fig. 1(b). In this stimulation
I. INTRODUCTION arrangement, the two outer electrodes of each tripole, the an-
odes, are connected together and to stimulate current is passed
EURAL interfaces that can detect naturally occurring
N nerve activity or stimulate nerves are an obvious goal
in neuroprosthetics with application in rehabilitation. Nerve
from the anodes to the cathode. For recording, the same tripole
arrangement is often used; sometimes called the quasi-tripole
(QT) [8] because the outer electrodes are connected together
stimulation is well established as a feasible chronic method and, therefore, are not recording independent potentials. Ide-
for peripheral nerve and nerve roots using electrode cuffs or ally, the QT will be completely insensitive to sources outside
books in the spinal canal [1]. Nerve signal recording is not yet the cuff or slot, but actually will have small sensitivity due to
well established. There is a conflict between the invasiveness some asymmetry due to manufacturing tolerance or nonuniform
of the method and the proximity of the electrodes to the axons tissue growth after implantation [9]. Methods to balance the QT
or groups of axons, which bring greater specificity and greater for out-of-slot interference neutralization have been described
signal amplitude. Penetrating electrodes such as the Utah Slant in [10] and [11].
Array can give useful data in acute experiments [2], [3] but have We are developing a prototype implant [12] that could stimu-
late and record from one tripole as well as having several stimu-
Manuscript received March 25, 2009; revised July 08, 2009. First published lation-only channels. This paper describes the integrated-circuit
December 18, 2009; current version published January 27, 2010. This work (IC) design of the two types of stimulator output stage. Both
was supported in part by the U.K. Engineering and Physical Sciences Research
Council (EPSRC) under Grant EP/F009593/1 and in part by the European Com-
circuits generate charge-balanced stimulating pulses by active
mission under HEALTHY AIMS Project IST-2002-1-001837. This paper was charging and passive discharge [13]. In both applications, after
recommended by Associate Editor S. Carrara. stimulation, a discharge path must be switched across the elec-
P. J. Langlois, A. Demosthenous, and I. Pachnis are with the Department
of Electronic and Electrical Engineering, University College London, London
trodes which must remain floating over a wide voltage range
WC1E 7JE, U.K. (e-mail: which can be 24 V or higher. To minimize power consump-
N. Donaldson is with the Department of Medical Physics and Bioengineering, tion, both circuits do not draw any current most of the time.
University College London, London WC1E 6BT, U.K. The stimulation-only circuit uses a floating depletion transistor
Color versions of one or more of the figures in this paper are available online
at to allow continuous discharge (except when stimulating) of the
Digital Object Identifier 10.1109/TBCAS.2009.2034138 electrodes without consuming power. The other type of output
1932-4545/$26.00 © 2009 IEEE

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Fig. 2. Three-slot electrode book. Each slot is a tripole. The electrodes connect
to a helix Cooper cable. The ruler shows the dimensions. For this photo, the
book was placed on two blue paper clips for support. (Manufactured by Finetech
Medical Ltd., U.K.)

Fig. 1. (a) Tripoles with common anodes. (b) Isolated tripoles.

stage uses the same electrodes for stimulation and recording.

Here, the discharge path must only be temporarily switched
in, which involves the use of a CMOS switch. A conventional
CMOS switch (standard transmission gate) has a voltage range
limited to the maximum gate-to-source voltage ( ) of the tran-
sistors used. Even in dedicated high-voltage technology transis-
tors can only withstand high drain-to-source voltages ( 20 V)
but not high ( 20 V) [14]. A modified CMOS switch is pre-
sented which operates over a range well beyond this limit. The
Fig. 3. Short timescale waveform. Voltage across the electrodes (anodes and
circuits were implemented in a high-voltage 0.6- m silicon-on- cathode of a tripole) in saline solution when a 1-mA, 1–ms pulse is applied.
insulator (SOI) CMOS technology and tested with tripolar elec-
trode books in saline.
The remaining sections of this paper are organized as fol-
lows. Section II discusses the electrode load, the basic stimu-
lation circuit for isolated tripoles, and the specifications of both
stimulator types. Section III describes the circuit details of the
two stimulators and analyses the performance of the proposed
CMOS switch when “off.” Measured results and discussion are
presented in Sections IV and V, respectively, followed by con-
cluding remarks in Section VI.

II. ELECTRODE LOAD AND DRIVING SYSTEM Fig. 4. Approximate equivalent circuit of a tripole during a 1-mA, 1-ms pulse
based on the Fig. 2 waveform.
A. Response to Current Pulses
The electrode structure known as a “book” was used in these
experiments (Fig. 2). The three platinum (Pt) foil electrodes of approximately characterized by the sum of two exponentials due
each tripole lie in a slot, and there are one or more slots in to the Pt-saline interface. When the pulse is removed, there is a
each book. During the actual implantation of a book, the sur- step voltage drop at the electrodes due to the bulk resistance,
geon places nerve roots into these slots and traps them with a followed by a decaying voltage approximately characterized by
lid (not shown in the figure). In the experiments described here, several exponentials representing the medium and long time-
the book was immersed in saline (0.9% NaCl). scale effects.
Fig. 3 shows the short timescale voltage across the electrode Fig. 4 shows an approximate linear equivalent circuit of a typ-
load (i.e., across the anodes and cathode of a Pt tripole) in saline ical Pt tripole during the 1-ms pulse. The bulk saline resistance
when driven by a 1-mA, 1-ms pulse. There is a voltage step due is . The charge injected into the electrodes during the stim-
to the resistance of the bulk saline solution and a rising voltage ulating current pulse is stored in capacitances representing the

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in the electrode capacitances is removed passively by the dis-

charge of via resistor when switch is turned on. The
peak discharge current (see Fig. 6) is usually a fraction of the
stimulating current to avoid unwanted stimulation. and
can be replaced by a suitably dimensioned transistor to provide
some current limit. The electrodes must be floating even when
discharge is taking place, so must be suitably isolated from
its control.

C. Stimulator Specifications
For stimulating parasympathetic fibres in the nerve roots, a
relatively large pulse charge is required and for this design, the
specification is for pulsewidths up to 1 ms in fine steps (10 s)
Fig. 5. Basic stimulation circuit for isolated tripoles using a blocking capacitor and currents up to 16 mA (1, 4 or 16 mA). Experiments with
C . Switch S is added to allow the electrodes to float once the stimulation has Pt electrodes in saline and a 4.7- F blocking capacitor show
that supply voltages up to 24 V may be necessary at the highest
pulse current. This dictates the use of a high-voltage technology.
Two types of stimulators are now considered in more detail.
Pt-saline interface. Electrode load characteristics can vary con-
The first type is for the stimulation-only channels and only has
siderably either due to surface effects on the Pt foil or to local
two states: stimulation and discharge. The second type is for
variations in the saline solution.
stimulation and nerve sensing using the same electrodes. It has
B. Basic Stimulation Circuit three states: 1) stimulation; 2) discharge; and 3) open circuit
(high impedance).
Fig. 5 shows the basic circuit for generating charged-balanced 1) Type I: In the discharge state, there must be a permanent
biphasic stimulating currents by active charging and floating low resistance connected across the electrodes to ensure their
passive discharge [15]. As noted in Section II-A, the electrodes complete discharge; and the electrodes must be isolated from
have a capacitive nature and, hence, could drive the discharge the driving circuit so that the impedance from the electrodes to
phase, but in practice, a blocking capacitor is connected the supply rails is very high (less than 0.1- A leakage current).
in series with the electrodes as shown in Fig. 5. The blocking The circuit will usually be in the discharge state, so the switch
capacitor serves three purposes: 1) it prevents direct current should not require power.
flowing through the electrodes if there is a short-circuit fault 2) Type II: Immediately after the stimulating current pulse
in the semiconductor switches; 2) it ensures that no charge ac- has been applied, the electrodes must be open circuit and
cumulates on the electrodes—the charge may not be zero over floating. A load to discharge the electrodes is applied at some
each pulse period (charge and discharge), but will be zero over time after the pulse ends. It must operate when the electrodes
a whole train of pulses; and 3) it allows “slide back” of the op- are floating (i.e., when the switches for the current pulse are
erating potential range of the electrodes so that it tends to re- off) and must operate at any floating voltage between the
main in the “water window” [13]. The disadvantages of using supply rails. Once discharged, the electrodes can then be open
are the added voltage required from the driver during the circuited again and allowed to float. The switched discharge
stimulation pulse and its physical size which means that it has may be off for long periods while monitoring the nerve signals.
to be added as a discrete component1. The low leakage and In both types, the peak discharge current must be limited to
small physical size required dictate the use of tantalum capac- less than 20% of the stimulating current during the active phase.
itors. Fig. 6 shows the voltage across a Pt tripole when using Excessive peak reverse current can cause unwanted spurious
a blocking capacitor due to a 1-mA, 1-ms (1- C) current pulse stimulation. The circuits must operate from 3-V logic control
every 49 ms. signals and a supply voltage that may vary between 6 and 24 V
During the stimulation phase, the anodes are connected to the and, to minimize power losses, is set so that it is just sufficient
positive supply ( ) by the low-resistance switch , and the to drive the actual load impedance.
current generator is turned on to provide a pulse to the
electrodes (on an unselected tripole, is off and 0). III. CIRCUIT DESIGN
At the end of the pulse, switches off, 0 and the
electrodes are isolated from the driver. During the pulse, the A. Technology
charge will be built up in the electrodes and the blocking capac- The high voltages and floating nature of the discharge
itor . The current generator will have to handle the voltage switches for both type I and type II stimulators require floating
drops across , , and the electrode load. In the discharge wells for NMOS and PMOS transistors. These conditions
phase when and are off, the tripole is floating and may and the added bonus of insulation, rather than reverse biased
be at any voltage between the supply rails because it lies in the well-to-substrate diodes for isolation, led to the choice of
an SOI CMOS technology which also offered considerable
electric field produced by the active tripole. The charge built up flexibility. A disadvantage is the higher thermal resistance to
1An integrated implantable stimulator that is fail-safe without off-chip the base substrate which results in the use of relatively large
blocking capacitors has been recently described in [16]. transistors. In all of the high-voltage transistors that were used,

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In Fig. 5, the discharge path is shown as a resistor in se-

ries with a switch. In Fig. 7, the resistor is dispensed with,
and only the depletion transistor ( ) discharges the capaci-
tance. It is dimensioned to allow a maximum current discharge
of 1.6 mA. This enables more rapid removal of the charge for
a given maximum discharge current than the simple exponen-
tial decay. Once the discharge current drops below 1.6 mA, it
increasingly behaves like a discharge resistor of about 1 k .

C. Type II Stimulator Circuit

In Fig. 5, once and are switched off, the discharge

switch may be subjected to voltages over the range of the
Fig. 6. Typical waveforms from electrodes in saline solution when using a supply voltage due to weak coupling with nearby tripoles. If the
blocking capacitor as in the circuit of Fig. 5. The input pulse is 1 mA in 1 ms electrodes are to remain open circuit for long periods without
repeated every 49 ms. The timing of the discharge cycle is shown. The max- using power, the depletion transistor in Fig. 7 must be replaced
imum discharge current is limited to 0.2 mA by the adjustment of resistor R . by a CMOS switch. However, the maximum operational range
The lower trace shows the time when the discharge switch is on.
of a conventional CMOS switch is limited to the maximum
of the transistors used. In high-voltage transistors, the maximum
(e.g., here 18 V) is generally significantly lower than the
the sources were connected to the local isolated substrate. maximum drain-to-source voltage (e.g., here 30 V). In this ap-
Logic controls used 3-V levels and were translated to operate plication, the operational range is 24 V and the conventional
the high-voltage transistors. CMOS switch has been modified as shown in Fig. 8. Transistors
, , and provide the top high-voltage switch and cur-
B. Type I Stimulator Circuit rent generator as in Fig. 7. and comprise the CMOS
switch. Discharge current limits are provided by load resistors
Fig. 7 shows the type I stimulator circuit. Transistors , , and . The source voltages at the CMOS switches
and provide the top high-voltage switch and current gener- and are detected by source followers and which
ator ( and in Fig. 5). The depletion transistor (which isolate the electrodes from the driving circuit. The driving pulses
must have a floating well to ensure constant depletion charac- are generated as in the type I circuit. The timing waveforms
teristics) provides the discharge switch ( in Fig. 5). Since the for stimulation, discharge, and recording are depicted in Fig. 8.
supply voltage can vary between 6 and 24 V (in the final im- During phase (and ), the top switch and the cur-
plant [12], the power supply will be through a flywheel step-up rent pulse in and are switched on, and stimulation is
dc-to-dc converter fed from a 3-V battery), the switches and enabled. To turn on the CMOS switch, the tail currents of
are controlled by switched current mirrors supplying cur- and generated from current mirrors during phase ,
rent to gate-source resistors and . Current references are switched on and the resulting voltages across and
switch and on. The CMOS switch is turned on and
(10 ), (20 A), and (60 A) are mirrored from an ex-
is floating. When the tail currents are switched off, the voltage
ternal reference bias current. The current pulse in the cascoded across and drops to zero and and turn off.
pulse generator and is controlled by a current mirror During phase , the electrodes are connected to the external
input and shared with other stimulators (channels). Its recording amplifier, which will be used to detect naturally oc-
amplitude is controlled by switching in drain-to-gate connected curring neural activity (ENG signals). The amplifier design will
transistors and controlled by (digital) voltages be described in a future publication. In the implant [12], the con-
and and dimensioned to mirror 1 mA, 4 mA, and 16 mA into trol signals will be provided by a microcontroller.
. The current in is switched on and off by and .
ensures that is completely off by holding of to
zero. The transistors used in , , , , and D. Performance of the CMOS Switch When “Off”
are low-voltage models controlled by 3-V logic signals.
When there is no stimulation, and are closed. In Fig. 8 when the CMOS switch is “off,” and are
is closed, is open, and is then off. There is no current “off” but will have small drain currents. Fig. 9 shows the NMOS
in and so of and are zero. is off and part of the CMOS switch; similar considerations apply to the
the depletion transistor is on and can float. To generate a PMOS part. is the drain current of , and is the
voltage at which the electrodes are floating when the stimulator
stimulation pulse, and are switched on. There is current
is inactive ( 0). The degree to which of is for-
in , and switches on. The of is limited to the ward biased depends on the drain current of . Fig. 9 shows
voltage drop across due to the current mirror output of . the basic circuit when is weakly forward biased and a cur-
is switched on and is switched off to generate a current rent flows in . The voltage across can be ignored.
pulse. The cascoded current generator ( , ) causes current The resulting drain current in due to may be amplified
to flow in the electrode load, and the voltage on the drain of by , depending on the difference of the threshold voltages
rises to 4 V or above depending on the load. Since there is now of and . Both and will be operating in weak
steady current available in , of is held negative, and inversion (i.e., , where is the threshold
is switched off for the duration of the stimulation current. voltage), is the thermal voltage, and is a constant between

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Fig. 7. Type I stimulator circuit by using a depletion transistor for discharging. The high-voltage transistors are shown with a small rectangle in the drain

terminal. Control voltages , , and enable the stimulation and discharge cycles as depicted by the timing waveforms. The amplitude of the stimulus current
is set by the digital control bits and .

1 and 2. Here, for the purpose of simple analysis, is assumed cycle, is small and the CMOS switch operates in the linear
to be the same for NMOS and PMOS transistors. region and its resistance is of interest.
A model for the drain current that covers all regions of inver- 1) Switch in Saturation: When the transistor is saturated
sion (weak, moderate, and strong inversion) of MOS devices is and
given by [17]

In Fig. 9, assuming the voltage across is negligible, from

(4) it can be shown that

where (5)

(2) where and are the threshold voltages of the PMOS

and NMOS transistors. The exponential components can be a
is the gate–oxide capacitance per unit area, is the average multiplier or divider dependent on the relative magnitudes of
carrier mobility in the channel (denoted by for the N-type and . must be as low as possible and multiplication
channel, and is for the P-type channel), and are the must be low. Since is about 35 mV, the mismatch in
channel width and length, respectively, and is the drain-to- and could cause the exponential multiplier in (5) to be
source voltage. In weak inversion, both exponential terms in large.
(1) are small, and using the approximation for The potential extent of the mismatch can be observed in Fig.
, (1) is reduced to 10 which shows Monte Carlo simulations of the spread of
versus described approximately by (4) for the PMOS and
(3) NMOS transistors used in Fig. 9. The horizontal spread shows
the spread of the values of and which cause large
differences in the multiplication factor due to the exponential
After the end of the stimulation pulse and before the discharge in (4). The resulting spread of is shown in the histogram of
cycle, is large and the CMOS switch is in saturation and Fig. 11. The maximum value for is about 700 pA which is 18
leakage current is of interest. After the end of the discharge times larger than the typical mean model leakage of 40 pA.

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M M 8
8 8 
Fig. 8. Type II stimulator circuit using a modified CMOS switch ( and ) for discharging. During phase , the electrodes can be connected to the
external neural recording amplifier (not described here). Before this recording ( ), would be long enough to fully discharge the electrodes and the 4.7- F
capacitors. The amplifier employs a T-network of biasing resistors to improve the effective common-mode rejection ratio (see [11]).

Fig. 9. One-half of the CMOS switch in Fig. 8 when is “off” but of
is weakly forward biased.

2) Switch in Linear Region: From (3), when 0, the

transistor is in the linear region with a drain-to-source resistance
I (log scale) versus V
of Fig. 10. Monte Carlo results of of transistors used in
Fig. 9 showing the spread due to


In Fig. 9, from (3) and (6), the NMOS switch resistance is (7)

The exponential component can significantly multiply or divide

as in (5). The characteristics of the resulting histogram are

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pulses every 50 ms. Fig. 13(a) shows the response for a 4-mA
pulse. The discharge current is below the designed 1.6-mA drain
current limit for the depletion transistor so there is an approx-
imate exponential decay. Fig. 13(b) shows the response for a
16-mA pulse. The discharge current, which would have been
larger due to the larger charge injected into and the (capaci-
tive) electrode load, is limited to 1.6 mA by the depletion tran-
sistor dimensions. Once the voltage across the capacitors has
dropped sufficiently, the discharge reverts to an approximate ex-
ponential decay.
Fig. 14 shows waveforms similar to Fig. 13 but for 10- s
pulses. The delay between the control signal changing from
high to low (beginning of the pulse) and the output current
changing is about 0.5 s. The delay between the control signal
changing from low to high (end of the pulse) and the output
current changing is 0.2 s. The transient overswing is due
to the different response times of the switch and current
generator , (see Fig. 7). To minimize the transient
Fig. 11. Histogram of the spread of I in the switch in Fig. 9. overswing, is switched on before ( s) the current
generator (see the timing waveforms in Fig. 7). For these very
short pulses, the amplitude of the discharge current is very
small and is masked by the errors caused by the noise due to
the common-mode signals imposed on the differential signal
input to the oscilloscope.
Fig. 15 shows the current waveforms from a type II stimu-
lator using conditions similar to Fig. 13. The discharge is de-
layed after the end of the stimulator pulse. In this design, the
CMOS transistors act as switches and the discharge current is
limited by resistive loads. The discharge current therefore has
an exponential decay. The discharge time has been shortened to
show the turnoff point. The 10- s pulses of the type II stimu-
Fig. 12. Chip microphotograph. lator have very similar characteristics to the type I in Fig. 14.

B. Switch Performance at Different Floating Voltages

similar to Fig. 11. The minimum is 75 M and using the
typical mean model, is 1.2 G . The floating voltages at the terminals of the stimulators are
In the analysis for , the PMOS part of the switch (Fig. constrained to be within the range of the supply voltage due
8) uses (5) and (7) with N-type and P-type components inter- to the clamping action of the drain-to-substrate diodes of the
changed. In the technology used, for the PMOS part, is much driving transistors. After stimulation, a voltage across the load
lower, and is higher than the NMOS part. remains (which for the 16-mA pulses may be about 8 V) that
adds further constraints to the floating voltages. As the discharge
IV. MEASURED RESULTS progresses, the voltage across the load decays and the possible
floating range increases. To test the effect of the floating voltage
An IC implementation of the two types of stimulator output on the depletion transistor switch when the switch is “on” (i.e.,
stages described in Section III was fabricated in XFAB’s in the discharge phase), the stimulator lower output terminal was
0.6- m SOI CMOS technology [18]. The chip microphoto- connected to a variable dc supply via a 1-M resistor to gen-
graph is shown in Fig. 12. The chip contained four type I erate a floating voltage, and the switch resistance was measured
stimulators (stimulation-only channels) and one type II stim- by applying a small (20-mV) floating voltage across the switch.
ulator (stimulation and recording channel). The silicon area The same measurement was repeated for the CMOS switch in
occupation of type I and type II stimulators is 0.24 mm and stimulator type II. Fig. 16 shows the measured “on” resistances
0.31 mm , respectively. In total, 15 chips were fabricated with of the depletion switch and the CMOS switch over the 24-V
100% yield. supply-voltage range. The depletion transistor switch “on” re-
sistance remains constant at all floating voltages ( ). In the
A. Pulse Performance CMOS switch at the floating voltage extremes, the “on” resis-
The stimulators were tested with multiple tripoles in saline tance is doubled due to the split loads and in the circuit
(0.9% NaCl). The current waveforms in the electrode load were of Fig. 8. To avoid this, future designs will have a common re-
measured by observing the differential voltage across a small re- sistor.
sistor in series with the cathode electrode using 10-M probes Limited by the accuracy of the measurement equipment, the
and an Agilent 54835A oscilloscope. The subtract function on measured currents in or out of the output terminals when the
the oscilloscope was used to display the current through the re- stimulators were inactivated were less than 5 nA over the full
sistor. The control pulses were generated from a TTi TGA12104 floating range for both depletion and CMOS switches. The cur-
generator. rent into the CMOS switch when off was also less than 5 nA.
Fig. 13 shows the current waveforms from a type I stimulator These leakage currents are well below the specified limit for our
using a tripole with a 4.7- F blocking capacitor ( ) and 1-ms application.

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Fig. 13. Type I current waveforms in a tripole in saline solution for 1-ms, (a)
4-mA, and (b) 16-mA stimulating pulses. The blocking capacitor is 4.7 F. The Fig. 14. Type I current waveforms in a tripole in saline solution showing 10-S,
cycle time is about 50 ms. In (a), the maximum discharge current is below 1.6 (a) 4–mA, and (b) 16-mA stimulating pulses. The charge overswing is <1% for
mA, and the current decays approximately exponentially. In (b), the maximum the (a) 4-mA pulse and 3.8% for the 16-mA pulse. Due to the very short pulse,
discharge current has been restricted to 1.6 mA by the depletion transistor. the discharge currents are of the same order as the errors in the measurement

C. Demonstration of Floating Discharge

To test the stimulator under realistic conditions, two outputs In the type I stimulator, the depletion transistor was designed
(type I stimulators) were connected to electrodes in saline (Fig. to limit the maximum discharge current to 1.6 mA (i.e., 10%
17) and pulsed alternately at 50 Hz. Fig. 18 shows the electrode of the maximum stimulating pulse amplitude); this is indepen-
voltages and the electrode current for one tripole. The following dent of any load variations in the book. The equivalent expo-
features are of interest. nential discharge for the same charge removal time would re-
• When neither tripole is active, the impedance between all quire a maximum initial discharge current of about 25% of the
of the electrodes and the power rails is very high. Con-
sequently, their potential depends on abnormal connec- stimulating pulse amplitude. This is a useful reduction at the
tions—here, the oscilloscope probes and the 10-M vari- higher pulse amplitudes. At lower currents, there is an exponen-
able pull-up resistance. Without this pull-up resistance, the tial discharge similar to the CMOS switch design. Unlike the
voltage falls to 0 V. depletion transistor design, at the higher currents when using
• During stimulation by the left-hand tripole, the anode is the switch plus resistance design, any variations in the elec-
close to the positive supply rail ( drop through the top trode load will cause the maximum discharge current to vary.
switch) and the cathode potential is determined by the in- The maximum discharge current limit concerns apply only at
terelectrode impedance. the wider pulsewidths.
• During stimulation by the right-hand tripole, the electrodes For stimulation pulses in the region of 10- s width, the over-
of the left-hand tripole track the potential of the right-hand swing at the start of the current pulse causes an error in the total
anode because they are at the ends of the right-hand slot expected charge of less than 5%. By switching the top switch
and, therefore, determine the potential of the saline outside
that slot. on before the current pulse, there is a slow (3 s) risetime with
• The current waveform shows the pulse followed by the no overswing.
passive discharge except that there are small spikes at the When the CMOS switch is “off,” the mismatch of the NMOS
edges of the other pulse. These correspond to the potential and PMOS transistors in the source follower additions, particu-
steps at this tripole and are due to capacitance between the larly in their different values of , have been shown to cause
floating tripole circuit and the power rails. wide variations in “off” characteristics, see (5) and (7). The

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Fig. 17. Integrated stimulator was tested with two outputs connected to Pt
tripolar electrodes in two adjacent slots of an electrode book. The 470-
sistors were connected in series with the cathodes so that the current could be
observed. The dashed resistors represent the oscilloscope probes and a 10-M

variable resistor which is adjusted to set the interpulse voltage on the electrodes.

Fig. 15. Type II current waveforms in a tripole is saline solution for 1 ms, (a)
4-mA, and (b) 16-mA stimulating pulses. The blocking capacitor is 4.7 F. The
cycle time is about 50 ms. The discharge cycle has been switched off early to
show the discharge current turnoff.

Fig. 18. Oscillogram showing stimulation pulses for left then right tripole
shown in Fig. 17. Pulse widths are 1 ms and pulse current is 16 mA. The
traces show the anode and cathode voltages for the left-hand tripole when the
interpulse electrode potential has been set to 10 V. By moving the anode probe
to the left-hand end of the 470-
resistor, the current waveform is found by
subtraction (third trace). The D and D digital pulses are, respectively, the
control signals for activating the current pulse in the left (channel 1) and right
(channel 2) tripoles in Fig. 17.

V, the circuits have been tried successfully with supplies up to

30 V, the maximum of the high-voltage transistors used.

Fig. 16. Measured variation of the CMOS and depletion switch discharge re- Two types of high-power nerve stimulators have been suc-
sistances with floating voltage. cessfully designed and tested. Both provide current pulses of
1 to 16 mA with 10- s to 1-ms widths from 6- to 24-V sup-
plies. The use of SOI technology enabled the design of a stim-
simple analysis assumed the factor in (1) was the same in ulator using a floating depletion transistor to ensure continuous
NMOS and PMOS transistors. In practice, is different (here, discharge of tripoles in electrode books using no power except
1.6 for NMOS and 1.3 for PMOS) but the exponential when stimulating, and a stimulator for use with sensing cir-
nature of the effect of mismatch of remains. The resulting cuits with a modified floating CMOS switch operating over a
simulated drain currents, primarily due to the NMOS part of the voltage range exceeding the maximum of the switch tran-
switch, were less than 1 nA, well below the specified target. Al- sistors, and which remains off for long periods while nerve ac-
though the specification stated a maximum supply voltage of 24 tivity is sensed. A prototype implant for preventing incontinence

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to patients after spinal cord injury is being designed by using the transistor devices. He has designed and fabricated many devices through
stimulator circuits described here [12]. Comett and Europractice for graduate and postgraduate projects, some in
collaboration with industry, over the last ten years. He is currently an Honorary
Senior Research Associate with the Department of Electronic and Electrical
REFERENCES Engineering, University College London.
[1] G. S. Brindley, “The first 500 patients with sacral anterior root stim-
ulator implants: general description,” Paraplegia, vol. 32, no. 12, pp.
795–805, Dec. 1994.
[2] R. Normann, D. McDonnall, and G. G. Clark, “Control of skeletal Andreas Demosthenous (S’94–M’99–SM’05) was
muscle force with currents injected via an intrafascicular, microelec-
born in Nicosia, Cyprus, in 1969. He received the
trode array,” in Proc. 27th Int. Conf. IEEE-EMBS, Shanghai, China, B.Eng. degree in electrical and electronic engineering
Sep. 2005, pp. 7644–7647. from the University of Leicester, Leicester, U.K., in
[3] A. Branner and R. A. Normann, “A multielectrode array for intrafas-
1992, the M.Sc. degree in telecommunications tech-
cicular recording and stimulation in sciatic nerve of cats,” Brain Res. nology from Aston University, Birmingham, U.K., in
Bull., vol. 51, no. 4, pp. 293–306, Mar. 2000.
1994, and the Ph.D. degree in electronic and elec-
[4] J. J. Struijk, M. Thomsen, J. O. Larsen, and T. Sinkjaer, “Cuff elec- trical engineering from University College London
trodes for long-term recording of natural sensory information,” IEEE
(UCL), London, U.K., in 1998.
Eng. Med. Biol. Mag., vol. 18, pp. 91–98, May/Jun. 1999. From 1998 to 2000, he was a Postdoctoral Re-
[5] M. Hansen, M. Haugland, T. Sinkjaer, and N. Donaldson, “Real time
search Fellow with the Department of Electronic
drop foot correction using machine learning and natural sensors,” Neu- and Electrical Engineering, UCL. In 2000, he was appointed to the academic
romodulation, vol. 5, no. 1, pp. 41–53, Jan. 2002. faculty of the same department, where he is currently a Reader and leads the
[6] S. Jenernik, M. Craggs, W. M. Grill, G. Creasey, and N. J. Rijkhoff,
Analog and Biomedical Electronics Research Group. His main area of research
“Electrical stimulation for the treatment of bladder dysfunction: current is analog and mixed-signal integrated circuits for biomedical, communication,
status and future possibilities,” Neurol. Res., vol. 24, no. 5, pp. 413–30,
sensor and signal-processing applications. He has many collaborations for
Jul. 2002. interdisciplinary research grants and has published many articles in journals
[7] N. N. de Donaldson, D. N. Rushton, T. A. Perkins, D. E. Wood, J.
and international conference proceedings. He is an Associate Editor for the
Norton, and A. Krabbendam, “Recruitment by motor nerve root stim- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS and an
ulators: significance for implant design,” Med. Eng. Phys., vol. 25, no.
Associate Editor for the IEEE CASS Newsletter.
7, pp. 527–537, Sep. 2003. Dr. Demosthenous is a member of the Analog Signal Processing Technical
[8] R. Stein, C. Davis, A. Jhamanda, T. Mannard, and T. Nichols, “Princi- Committee (ASPTC) and the Biomedical Circuits and Systems (BioCAS) Tech-
ples underlying new methods for chronic neural recording,” Le Journal
nical Committee of the IEEE Circuits and Systems Society (CASS). He is also
Canadien des Sciences Neurologiques, vol. 2, pp. 235–244, 1975. a member of the U.K. Engineering and Physical Sciences Research Council
[9] I. F. Triantis, A. Demosthenous, and N. Donaldson, “On cuff imbalance
(EPSRC) Peer Review College. He is on the International Advisory Board for
and tripolar ENG amplifier configurations,” IEEE Trans Biomed. Eng., Physiological Measurement, Institute of Physics. He is a member of the Tech-
vol. 52, no. 2, pp. 314–320, Feb. 2005.
nical Programme Committee of various IEEE conferences, including ESSCIRC,
[10] M. Rahal, J. Winter, J. Taylor, and N. Donaldson, “An improved con- BioCAS, and ECCTD.
figuration for the reduction of EMG in electrode cuff recordings: a
theoretical approach,” IEEE Trans Biomed. Eng., vol. 47, no. 9, pp.
1281–1284, Sep. 2000.
[11] I. Pachnis, A. Demosthenous, and N. Donaldson, “Passive neutraliza-
tion of myoelectric interference from neural recording tripoles,” IEEE Ioannis Pachnis (S’06–M’09) was born in Athens,
Trans Biomed. Eng., vol. 54, no. 6, pt. 1, pp. 1067–1074, Jun. 2007. Greece, in 1979. He received the M.Eng. degree in
[12] N. Donaldson, T. Perkins, I. Pachnis, A. Vanhoest, and A. Demos- computer systems engineering from the University
thenous, “Design of an implant for preventing incontinence after spinal of Sheffield, Sheffield, U.K., in 2003 and the M.Sc.
cord injury,” Artif. Organs, vol. 32, no. 8, pp. 586–591, Aug. 2008. degree in analog and digital integrated circuit design
[13] N. N. de Donaldson and P. E. K. Donaldson, “When are actively-bal- from Imperial College London, London, U.K., in
anced biphasic (’Lilly’) stimulating pulses necessary in neurological 2005.
prostheses? Part I: Historical background; Pt resting potential; Q Currently, he is a Research Assistant in the Analog
studies,” Med. Biol. Eng. Comput., vol. 24, no. 1, pp. 41–49, Jan. 1986. and Biomedical Electronics Research Group, Depart-
[14] M. Ortmanns, “Charge balancing in functional electrical stimulators: ment of Electronic and Electrical Engineering, Uni-
A comparative study,” in Proc. IEEE Int. Symp. Circuits Syst., New versity College London, London, U.K. His research
Orleans, LA, May 2007, pp. 309–312. interests focus on neural signal recording and stimulation, modeling of metallic
[15] A. Vanhoestenberghe, “Implanted devices: Improved methods for electrodes, and analog integrated-circuit design for biomedical applications.
nerve root stimulation,” Ph.D. dissertation, Univ. College, London,
U.K., 2007.
[16] X. Liu, A. Demosthenous, and N. Donaldson, “An integrated
implantable stimulator that is fail-safe without off-chip blocking-ca- Nick Donaldson received the M.A. degree in engi-
pacitors,” IEEE Trans. Biomed. Circuits Syst., vol. 2, no. 3, pp. neering and electrical sciences from Cambridge Uni-
231–244, Sep. 2008. versity, Cambridge, U.K., in 1976.
[17] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. From 1977 to 1992, he was with the Medical
New York: McGraw-Hill, 1999, ch. 4. Research Council, Neurological Prostheses Unit,
[18] Germany, X-FAB Semiconductor Foundries AG. [Online]. Available: London, U.K. In that period, his main field of research was the technology and use of implanted
devices for the restoration of useful leg function
Peter J. Langlois received the B.Sc.(Eng) degree in to paraplegics. Since 1992, he has been Head of
electronic engineering and the M.Sc. degree in infor- the Implanted Devices Group at University College
mation engineering from Imperial College, London, London, London, U.K., where he is also a Professor.
U.K., in 1957 and 1960, respectively. He has been Principal Investigator for many projects related to implanted
He was a Project Manager for Standard Telecom- devices and functional electrical stimulation. His research interests include
munication Laboratories before joining Chelsea the development of implanted devices that use natural nerve signals as inputs,
College and then Kings College in London Univer- especially for preventing incontinence; stimulators of nerve roots; the use of
sity, London. His continuing interest has been in electrical stimulation for recreational exercise of paralyzed legs; and methods
analog circuit design, and lately in analog and digital to encourage functional neurological recovery after injury.
custom integrated circuits including RF circuits.
He also has an interest in heterojunction bipolar

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