Logic Family

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 3.1 Introduction
• Logic gates are electronic circuits  constructed out of
electronic components and fabricated as ICs.
• Resistor, diode, transistor(BJT), mosfet etc.
• Specific components used  circuit technology.
• Digital ICs may be classified into various logic families
according to the circuit technology :

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 1. Resistor – Transistor Logic (RTL)
2. Diode – Transistor Logic (DTL)
3. Transistor – Transistor Logic (TTL)
4. Emitter Coupled Logic (ECL)
5. MOS Logic
6. CMOS Logic
7. Integrated Injection Logic (I2L)

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 3.2 Characteristics of Logic families
1. Logic level
• Binary logic has only 2 values : High & Low (1 & 0)
• Two different analog voltages represent them.
• If higher value represents HIGH & lower one for LOW,
the system is positive logic. (eg. 5V for 1 & 0V for 0).
• If lower value represents HIGH & higher one for LOW,
the system is negative logic. (eg. 0V for 1 & 5V for 0).
• Eventhough logic levels are specific values, a voltage
range is practically used to represent logic 1 & 0.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 Logic 1
Logic 1 VOH
VIH [under Positive
logic concept]

VIL VOL
Logic 0 Logic 0

• VIH  minimum voltage required at the input to

be considered as logic 1.
• VIL  maximum voltage at the input upto which it
will be considered as logic 0.
• VOH  minimum voltage that may appear at the
output under logic 1 state.
• VOL  maximum voltage that may appear at the
output under logic 0 state.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 2. Noise immunity
• The ability of a logic circuit to withstand the noise
without affecting its output  i.e. how much noise
voltage it can accommodate.
• Noise margin is calculated considering both input side
and output side voltage ranges.

Logic 1 VNH
High state NM,
Logic 1
VNH = VOH – VIH
Low state NM,
VNL = VIL – VOL
VNL Logic 0
Logic 0
NM = min (VNH, VNL)

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 3 Propagation delay
• Time taken by the circuit to respond to a change in the
input  time difference between application of an
input and appearance of corresponding output.

tPLH  propagation delay in going from Low to High in

response to a change in input.
tPHL  propagation delay in going from High to Low in
response to a change in input.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 4 Fan-in
• Number of inputs of a logic gate  NOT gate has a fan-
in of 1, XOR has 2, 4 input OR has 4 etc.
• Higher the Fan-in, slower the gate operation.
• i.e. 4 input OR gate works slower than 2 input OR gate.
5 Fan-out
• Maximum number of gate inputs that the output of a
logic gate can drive maintaining the output levels.
• More and more current will be drawn through the
output terminal as the number of connected gate
inputs increases.
• Propagation delay also increases with each connected
input.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 6 Power dissipation
• Electrical energy consumed by the logic gate in a
specific period of time.
• Product of supply voltage and average current drawn
from the supply.
7 Speed-power product
• It is the product of propagation delay and power
dissipation of a logic gate  is a figure of merit.
• Smaller the product, better is the logic gate.
• It is expressed in Joules.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 3.3 TTL family
• Uses BJTs to perform logic operations & amplification.
• High switching speed, less noise and high current
capability.

• NAND gate is the basic building block.

• TTL gates can be constructed with different output
configurations :
1. Open collector, 2. Totem-pole, 3. Tristate
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 3.3.1 TTL NAND gate in open collector configuration
• Q1 is a multi-emitter transistor
& i/ps applied to its emitters.
• A resistor is to be externally
connected at the collector of Q3
to +Vcc  pull-up resistor.

• When both i/ps are high  Q1 OFF  high voltage at

its collector  Q2 is ON  high voltage across R3  Q3
is ON  low collector voltage  i.e. low output.
• When any one i/p is low  Q1 is ON  low voltage at
collector  Q2 is OFF  low voltage across R3  Q3 is
OFF  high collector voltage  i.e. high o/p.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 • Advantage  suitable for wired logic function.
• Disadvantage  pull-up resistor is in KΩ range 
causes slow switching operation.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 3.3.2 TTL NAND gate in totem-pole configuration
• External pull-up resistor replaced
by totem-pole connection of
Q3 & Q4  active pull-up.
• When both i/ps are high 
Q1 OFF  high voltage at
collector  Q2 is ON  low
collector voltage & high emitter
Voltage  Q4 OFF & Q3 ON  output Y is LOW.
• When any one i/p is low  Q1 ON  low voltage at
collector  Q2 is OFF  high collector voltage & low
emitter voltage  Q4 ON & Q3 OFF output Y is HIGH.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 • Advantage  low output impedance when output
is logic 1  faster switching.
• Disadvantage  decreased voltage level for logic 1
 not more than 3.5V.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 3.3.3 TTL NAND gate in tristate configuration
• Tristate gate  logic gate with three possible state
values  0, 1 & Z.
• Z means High Impedance state  neither 1 nor 0.
• Tristate TTL NAND gate has an additional enable
input  if enable = logic 1, output is 1 or 0
according to values of A & B  If enable = logic 0,
output is Z.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 • With e=1, D2 is disabled
 circuit behaves like a
totem-pole NAND gate.
• Then, If both A & B high,
o/p is low.
• If either or both of A &B
low, o/p is high.
• With e = 0, D2 is ON,
T3 & T4 OFF irrespective of A & B. Input Output
E A B Y
• Now, the gate circuit is logically 0 X X Z
disconnected from the output load 1 0 0 1
 it is in high impedance state. 1
1
0
1
1
0
1
1
1 1 1 0
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 3.4 MOSFET

MOSFET

Depletion Enhancement

NMOS PMOS NMOS PMOS

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 • NMOS  High input – Turn on, Low input – Turn off.
• PMOS  High input – Turn off, Low input – Turn on.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 3.5 CMOS logic family
• CMOS  connecting a p-channel & n-channel MOSFET
in series  drains tied together & the output is taken
at common drain  input applied to common gate.

• Reduced packing density, reduced speed but negligible

power consumption.
• Currently CMOS is the most popular for MSI & LSI areas
and is the only possible logic for VLSI devices.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 3.5.1 CMOS Inverter

• When A = 0 (i.e. Gnd), T1 turns ON and T2 turns OFF

 Drain voltage is high  output is 1.
• When A = 1 (i.e. VCC ), T1 is OFF & T2 is ON  low
drain voltage  output is 0.
• In either case, one of MOSFETs is OFF and only
small ID flows  low power dissipation.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 3.5.2 CMOS NAND gate

• T1 & T2 are PMOS and T3 & T4 are NMOS.

• If A is low, T1 is ON & T3 is OFF  If B is low, T2 is ON &
T4 is OFF  either case, output terminal is connected
to VCC & Q is HIGH.
• When both A & B are high, T1 & T2 are OFF and T3 & T4
are ON  output is connected to Gnd  Q is Low.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 3.5.3 CMOS NOR gate

• T1 & T2 are PMOS and T3 & T4 are NMOS.

• If A & B are low, T1 & T2 are ON and T3 & T4 are OFF 
o/p terminal is now connected to VCC & Q is HIGH.
• When A is high, T1 is OFF & T3 is ON  When B is high,
T2 is OFF & T4 is ON  either case, output terminal is
connected to Gnd  Q is Low.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 3.6 Comparison of logic families

• ECL  a non-saturated transistor logic family 

achieves very low propagation delay  useful for high
speed circuits  but very low noise margin & high
power dissipation.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
 3.7 TTL subfamilies
• TTL family ICs available in 74XX series  Modified TTL
have been developed to provide special characteristics:
 74 series : Standard TTL
 74H series : High speed TTL – lower resistor values
used to reduce propagation delay, but increases
power dissipation.
 74L series : Low power TTL – higher resistor values
used to reduce power dissipation, but propagation
delay increases.
 74S series : Schottky TTL – Prevent the transistors
from saturation – reduces propagation delay.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.
  74LS series : Low power Schottky TTL – sacrifices
some speed to have lesser power dissipation.
 74AS series : Advanced Schottky TTL – improvement
in propagation delay over 74S series and also lowers
power dissipation.
 74ALS series: Advanced Low power Schottky TTL –
lowest speed-power product and most efficient
 74F series : Fast TTL – fastest and best choice for
high speed circuits.

Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.

 • 74XX (commercial grade)  temp. range 00C to +700C.
• 54XX series  Military grade TTL  provide wider
temperature range  -550C to +1250C.
Prepared by : Sojan Francis P., Asst. Professor, ECE Dept., VAST.