MTB50N06V

Preferred Device

Power MOSFET
42 Amps, 60 Volts
N−Channel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
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speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
42 AMPERES
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage 60 VOLTS
transients. RDS(on) = 28 mΩ
• Avalanche Energy Specified
N−Channel
• IDSS and VDS(on) Specified at Elevated Temperature
D
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−Source Voltage VDSS 60 Vdc G
Drain−Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc
Gate−Source Voltage S
− Continuous VGS ± 20 Vdc
− Non−Repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk 4
Drain Current − Continuous @ 25°C ID 42 Adc
D2PAK
Drain Current − Continuous @ 100°C ID 30
CASE 418B
Drain Current − Single Pulse (tp ≤ 10 μs) IDM 147 Apk 1 2
STYLE 2
Total Power Dissipation @ 25°C PD 125 Watts 3
Derate above 25°C 0.83 W/°C
Total Power Dissipation @ TA = 25°C 3.0 Watts
(Note 1)
Operating and Storage Temperature TJ, Tstg − 55 to °C MARKING DIAGRAM
Range 175 & PIN ASSIGNMENT
4
Single Pulse Drain−to−Source Avalanche EAS 400 mJ
Drain
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 42 Apk, L = 0.454 μH, RG = 25 Ω)
Thermal Resistance °C/W MTB50N06V
− Junction−to−Case RθJC 1.2 AYWW
− Junction−to−Ambient RθJA 62.5
− Junction−to−Ambient (Note 1) RθJA 50
Maximum Lead Temperature for Soldering TL 260 °C 1 2 3
Purposes, 1/8″ from case for 10 sec Gate Drain Source
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended A = Assembly Location
Operating Conditions is not implied. Extended exposure to stresses above the Y = Year
Recommended Operating Conditions may affect device reliability. WW = Work Week
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
ORDERING INFORMATION

Device Package Shipping

MTB50N06V D2PAK 50 Units/Rail

MTB50N06VT4 D2PAK 800/Tape & Reel

Preferred devices are recommended choices for future use

and best overall value.

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

August, 2006 − Rev. 5 MTB50N06V/D
 MTB50N06V

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 − − Vdc
Temperature Coefficient (Positive) − 69 − mV/°C
Zero Gate Voltage Drain Current IDSS μAdc
(VDS = 60 Vdc, VGS = 0 Vdc) − − 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) − − 100
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS − − 100 nAdc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 μAdc) 2.0 2.7 4.0 Vdc
Temperature Coefficient (Negative) − 3.0 − mV/°C
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 21 Adc) RDS(on) − 0.025 0.028 Ohm
Drain−Source On−Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 42 Adc) − 1.4 1.7
(ID = 21 Adc, TJ = 150°C) − − 1.6
Forward Transconductance (VDS = 6.25 Vdc, ID = 20 Adc) gFS 16 23 − mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss − 1644 2320 pF
(VDS = 25 Vdc, VGS = 0 Vdc,
Output Capacitance Coss − 465 660
f = 1.0 MHz)
Reverse Transfer Capacitance Crss − 112 230

SWITCHING CHARACTERISTICS (Note 3)

Turn−On Delay Time td(on) − 12 20 ns
Rise Time (VDD = 25 Vdc, ID = 42 Adc, tr − 122 250
VGS = 10 Vdc,
Turn−Off Delay Time RG = 9.1 Ω) td(off) − 64 110
Fall Time tf − 54 90
Gate Charge QT − 47 70 nC
(See Figure 8)
(VDS = 48 Vdc, ID = 42 Adc, Q1 − 9 −
VGS = 10 Vdc) Q2 − 21 −
Q3 − 16 −
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 2) VSD Vdc
(IS = 42 Adc, VGS = 0 Vdc)
− 1.06 2.5
(IS = 42 Adc, VGS = 0 Vdc, TJ = 150°C)
− 0.99 −
Reverse Recovery Time trr − 84 − ns
(See Figure 14)
ta − 73 −
(IS = 42 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs) tb − 11 −
Reverse Recovery Stored QRR − 0.28 − μC
Charge

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance LD nH
(Measured from contact screw on tab to center of die) − 3.5 −
(Measured from the drain lead 0.25″ from package to center of die) − 4.5 −
Internal Source Inductance LS − 7.5 − nH
(Measured from the source lead 0.25″ from package to source bond pad)
2. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.

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 MTB50N06V

TYPICAL ELECTRICAL CHARACTERISTICS

100 100
TJ = 25°C VGS = 10 V 9V VDS ≥ 10 V
8V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

80 80 100°C
7V

25°C
60 60
TJ = − 55°C
6V
40 40

5V
20 20

0 0
0 0.8 1.6 2.4 3.2 4 1 2 3 4 5 6 7 8 9
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.04 0.033
VGS = 10 V TJ = 25°C

0.034
TJ = 100°C 0.03

0.028 25°C
0.027 VGS = 10 V
0.022

0.024 15 V
0.016
− 55°C

0.01 0.021
0 20 40 60 80 100 0 20 40 60 80 100
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current
and Temperature and Gate Voltage

2.5 1000
RDS(on) , DRAIN−TO−SOURCE RESISTANCE

VGS = 10 V VGS = 0 V
ID = 21 A TJ = 125°C
2
I DSS , LEAKAGE (nA)

100
(NORMALIZED)

1.5
100°C

1
10

0.5 25°C

0 1
− 50 − 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−To−Source Leakage

Temperature Current versus Voltage

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3

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
5000
C, CAPACITANCE (pF)
4000
3000
2000
1000
0
10
MTB50N06V
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
Crss
Ciss
Coss
Crss
5 0 5 10 15 20 25
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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 MTB50N06V

14 56 1000
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VDD = 25 V
12 48 ID = 42 A
VGS = 10 V
10 QT 40 TJ = 25°C
100 tr
VGS

t, TIME (ns)
8 32 tf
Q1 Q2 td(off)
6 ID = 42 A 24
TJ = 25°C 10 td(on)
4 16

2 8
Q3 VDS
0 0 1
0 10 20 30 40 50 1 10 100
QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

50
VGS = 0 V
TJ = 25°C
40
I S , SOURCE CURRENT (AMPS)

30

20

10

0
0.5 0.6 0.7 0.8 0.9 1 1.1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain−to−source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is
junction temperature and a case temperature (TC) of 25°C. to rate in terms of energy, avalanche energy capability is not
Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases non−linearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal temperature.
Resistance−General Data and Its Use.” Although many E−FETs can withstand the stress of
Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry
transition time (tr,tf) do not exceed 10 μs. In addition the total custom. The energy rating must be derated for temperature
power averaged over a complete switching cycle must not as shown in the accompanying graph (Figure 12). Maximum
exceed (TJ(MAX) − TC)/(RθJC). energy at currents below rated continuous ID can safely be
A Power MOSFET designated E−FET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

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 MTB50N06V

SAFE OPERATING AREA

1000 400
VGS = 20 V

EAS, SINGLE PULSE DRAIN−TO−SOURCE

ID = 42 A
SINGLE PULSE
I D , DRAIN CURRENT (AMPS)

TC = 25°C 320

AVALANCHE ENERGY (mJ)

100
240
10μs

160
10 100μs

RDS(on) LIMIT 1ms 80

THERMAL LIMIT dc 10ms
PACKAGE LIMIT
1 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2
0.1
0.05 P(pk)
0.1 RθJC(t) = r(t) RθJC
0.02
D CURVES APPLY FOR POWER
0.01 PULSE TRAIN SHOWN
SINGLE PULSE t1 READ TIME AT t1
t2 TJ(pk) − TC = P(pk) RθJC(t)
DUTY CYCLE, D = t1/t2
0.01
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

3
RθJA = 50°C/W
Board material = 0.065 mil FR−4
2.5 Mounted on the minimum recommended footprint
PD, POWER DISSIPATION (WATTS)

Collector/Drain Pad Size ≈ 450 mils x 350 mils

2.0
di/dt
IS 1.5

trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (°C)

Figure 14. Diode Reverse Recovery Waveform Figure 15. D2PAK Power Derating Curve

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 MTB50N06V

PACKAGE DIMENSIONS

D2PAK
CASE 418B−04
ISSUE J

NOTES:
C 1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
E 2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
V
−B− NEW STANDARD 418B−04.
W
4 INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
A C 0.160 0.190 4.06 4.83
S D 0.020 0.035 0.51 0.89
1 2 3 E 0.045 0.055 1.14 1.40
F 0.310 0.350 7.87 8.89
G 0.100 BSC 2.54 BSC
−T− H 0.080 0.110 2.03 2.79
K J 0.018 0.025 0.46 0.64
SEATING W K 0.090 0.110 2.29 2.79
PLANE
G J L 0.052 0.072 1.32 1.83
M 0.280 0.320 7.11 8.13
H N 0.197 REF 5.00 REF
D 3 PL P 0.079 REF 2.00 REF
R 0.039 REF 0.99 REF
0.13 (0.005) M T B M
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

SOLDERING FOOTPRINT*

8.38
0.33

10.66 1.016
5.08
0.42 0.04
0.20

3.05
0.12
17.02
0.67
SCALE 3:1 ǒinches
mm Ǔ

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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