Current

Mirrors

Ars Diavolo
Current Mirrors

iin vin iout

Diode Gain
connected stage
transistor

Basic circuit: Diode connected transistor + Gain stage

 Current Mirrors

BJT case

v in
vT v
VDD
iin = Is1 e (1 + Vin )
A
v in
Ibias
iin RL vT v out
iout = Is2 e (1 + VA
)
Iout

v
Q1 Q2
i out (1 + out ) A Q2
+ I VA
vin = s2
Is1 v
≈
i in A Q1
- (1 + in )
VA
 Current Mirrors

MOS case

iin =
µ n Cox  W 
2 L
 
(1 vin − vth)2 (1 + λ vin)
VDD

iin Ibias RL
iout =
µ n Cox  W 
2  L
 
(2 vin − vth)2 (1 + λ vout )
Iout
 W  W
  L
iout  L  2 (1 + λ vout )  2
M1
+
M2

iin
=
(1 + λ vin )
≈
v gs + vGS  W  W
 L  L
-
 1  1
Remarks:

- Despite of the fact that both devices are nonlinear, the large signal
current gain is linear.

- This is due to the principle of the inverse function, and similar to

the case of the gain stage loaded with a diode connected transistor.

- The early voltage introduces distortion in the BJT’s case.

- The body effect introduces distortion in the MOS transistors case.
 AC Analysis:

CL
RL
CS IS

Cµ 2 Iout
Iin

+
α
cπ1 + cπ2 + ccs1 Vπ gm1+ rπ1 + ro1+ rπ2 gm2 vπ rO2 Ccs2

Low frequency:
α α Low ≈ 20 Ω for BJT’s
Rin = gm1+ rπ1 + ro1+ rπ2
≈ gm1 1k Ω for MOS

1 1 Medium-high ≈ 100 kΩ for BJT’s and MOS

Rout = ro2 ≈ =
gds 2 λ I B2
W
− L
 2
 for MOS
W
L
iout Rs ro2 g m2 
≈ =
 1
= g R
iin R in + Rs m2 in ro2 + R L g 
 −
m1 A Q2
for BJT’s
A Q1
High frequency:


τ1 = (cµ 2 + cπ1 + cπ2 + ccs1 + cs ) (R in Rs ) ≈ cin 1

g m1
fo = 21π 1 ≈ 1 1
 τ1 + τ 2 2π τ 2

τ2 = (cµ 2 + cL + ccs2 ) (ro RL ) ≈ cout RL


.


- Cm2 does not play a role since current mirrors are used with low RL,
that is, the gain stage has low voltage gain and is not Miller amplified,

- None of the time constants is dominant, both of them are very short.

Then:
The fo of a current mirror is close to fT .
Errors in MOS current mirrors:

∆ Vt: Not the same threshold voltage in M1, M2

∆ (W/L): Due to local error variations since systematic and
global components can be mostly compensated.

iin =
µn Cox
2
 W 
   + ∆ W  
  L 1

 L 1 
(vin − vth )2 (1 + λ vin )


iout =
µ n Cox
2
 W  
( ) (
   + ∆ W   vin − vth 2 1 + λ vout
  L 2  L 2 
)


It can be shown, neglecting λ effects and assuming matched

transistors:
∆ID ∆( W L) ∆Vth
= W - 2
ID ( ) L
VGS - Vth
Example of calculations in simple current mirrors.

RL= 10 kΩ, CL = CS = Cin = 1 pF, VDD = 5V, VSS = -5V, σ ∆W = 0.2 µm

Ibias = 200 µA, σ Vt = 0.02 V, (W/L)1 = (W/L)2 = 10/2, λ n = 0.02

I bias 200
VinQ = + Vth = + 0.8 = 2.08 V ; Q
VGS − Vth = 1.28V
C 25 ∗ 5
µ ox W
2 L

Vout = VDD - ID RL = 5 - (-5) = 0

2I D 400 1
gm1,2 = = = 312.5µA / V r01,2 = = 250 kΩ
Q
VGS − Vth 1.28 λ IQD
R out = ro2 = 250 kΩ

1
R in = = 3.2 kΩ
gm

1 + λ v out
Q
ID 2 1 + 0.02 ∗ 0.8 1.16
= = = = 0.97
1+ λ v
Q
ID1 in 1 + 0.02 ∗ 2.08 1.42
Noise Analysis

in, Rs = 4 k T ∆f
2

Rs
VDD
2  
in, M1 = 2 k T  2 g3m  ∆f
Ibias Iout  
2  
in, M2 = 2 k T  2 3gm  ∆f
 
M1 M2 M1
+ 2  gm gm 
v gs + vGS in, out = 4 k T ∆f  R1s + 3
+ 3 
 
-

2 4 k T ∆f  R1s + g3m + gm 
3 
in, out   = 1 + 2 gmRs
NF = =
2 4 k T ∆f 3
in, Rs Rs
Distortion Analysis
Iin = kp W
L
(Vin − VT)2 ⇒ Vin = Iin
kp W
+ VT
L

If Iin= IB + iin and Vin= VB + vin

1+ iIin
Vin = kp W
B
+ VT − VB
IB L

Expanding in Taylor series:

 2 3 
Vin = 1 1 + 1  iin  − 1  iin  + 1  iin  + . . .  + V − V
 IB  T B
kp W
IB L  2  IB  8  IB  16
  
 

 A2 2 A3 3

Vin = kp W
1
1 + A
2 IB
sin ωt − 2 sin ωt + sin ωt + . . .  + VT − VB =
16 I3B
IB L  8 IB

If iin = A sin ωt
 A2 3 
= 1
kp W 1 + A
2 IB
sin ωt − 2 { 1 + cos 2ωt } + 64AI3 { 3 cos ωt + cos 3ωt } + . . .  + VT − VB =
IB L  16 IB B  A2
HD2= 8 IB
 
= 1
kp W
1 − A2
 16 IB2
  A
 +  2 IB +
 

3 A3 
3  sin ωt
64 IB 
− A2
2
16 IB
cos 2ωt + A3
64 I3B
cos 3ωt + . . .  + VT − VB

⇒ A3
IB L
   HD3= 32 IB
Distortion Analysis

Iout = kp W
L
(Vin − VT)2

If Vin= VB + vin

Iout + iout = kp W
L
(VB + vin − VT)2

A2
2 HD2=
⇒
2 2 (VB - VT)
   
iout = 1 + vin  − 1 = 2 vin + 1  2 vin 
VB − VT VB − VT 4 VB − VT
   
HD3= 0

Total Distortion

HD2, tot = HD2 FD1 + HD1 FD2 =

1 1
= A + A
gm VB 2 (VB − VT)
x(t)
HD2 + FD2 +
y(t)
2
HD3, tot = HD3 FD1 = A
2 2
HD3 0 32 gm VB
MOS Transistor: Nonidealities caused by channel length modulation

If only VDS is different in both transistors:

(1 + λ v DS2 )
iout = i ≈ - iin - λ ( v DS2 − v DS1 ) iin
(1 + λ v DS1 ) in

i in
v DS1 ≈VDS +
gm
If we define the drain-source voltages as:
i in
v DS1 ≈VDS +∆VDS + α
gm

iout = - i in ( 1 + λ v DS1 ) - iin2 λ ( 1 − α )

gm

Thus:

H D 2 (λ ) = λ iˆ ( 1 − α ) = m gds 1 − α
2 gm gm 2

In terms of harmonic distortion, the second order component is:

MOS Transistor: Nonidealities due to the threshold voltage mismatch

If the difference between threshold voltages is given by:

∆ VTH ≈ VTH2 − VTH1

β
= -by
the output current iisoutgiven i inthe 2
- expression:
∆VTH - VTH 2 β ( i in + i B )
2

β
ioff (VTH ) = - ∆VTH
2
- ∆VTH 2β iB
2
Which has a offset current component given by:

( i in + i B ) = ( 2

in
3
i B 1 + 2iini B − 8iiin2 + 16iini 3 − 128
5 i in
in i 4 +
4
7 i in
256 i 2
in
+ ...
2

in
)
Using Taylor Series:

iin = iˆ sin( ω t ) = m i B sin( ω t )

If we assume that the input signal is:

( i in + i B ) ≈ (
i B 1 + m2 sinω t + m16
2
sin 2ω t − m
2 3

64 sin 3ω t
3 5m
− 1024
4
sin 4ω t +
4 7m5 5
4094 sin 5ω t + ... )
the harmonics are given by:
Solving the current gain as a function of the threshold voltages mismatch:
β ∆VTH
Ai ( ∆VTH ) ≈ 1 - ∆VTH = 1-
2 iB VGS - VTH

and the second harmonicH

component m
is given ∆VTH
by the expression:
D 2 ( ∆VTH ) ≈
8 VGS - VTH

2 ∆VTH
H D 3 ( ∆VTH ) ≈ m
While the third harmonic component is: 32 VGS - VTH
Degenerated Current Mirror

Ib Iout Iout
iin

1/gm

M1 M2 +
gm Vgs rO2
RS Vgs
Vx Vy
_
R R

R
vx = ( Ib + iin ) R = ia R

vy = ( Ib + iin ) 1
gm
= ia 1
gm

ia = kp W
L
(vin − vx − VT)2 ve = R iout
ia ia
vin − vx = kp W
+ VT = ia R + kp W
+ VT iout + gmve = (vout − ve) / ro2
L L

iout1 + gm R + rRo2  = vout

2
 
W 
vout = kp L  ia R + ia
kp W
+ VT − iout R − VT    ro2
 L 
 
Zout = vout = ro2 + gm R ro2 + R
iout R + iout
kp W
= ia R + ia
kp W
iout
L L
Noise Analysis
2 4 k T ∆f
i n , Rs =
Rs
Rs
Iout

2 4 k T ∆f
in, R =
M1 M2 R

in, M 1 = 2 k T
2
( ) ∆f
2 gm
3

= 2 k T ( ) ∆f
R R 2 2 gm
in, M 2 3

= 4 k T ∆f ( + )
2
in ,out 1
Rs
gm
3 + g3m + R1 + 1
R

NF =
in ,out
2

=
4 k T ∆f ( 1
Rs+ g3m + g3m + R1 + 1
R ) = 1+ 2 g m Rs
+
2 Rs
i n , Rs
2
4 k T ∆f 3 R
Rs
Cascode Current Mirror
VDD
Iout

iin Ib +
α gm4 vπ3
Iout Vπ 3 rO4
gm2
_

+ vx
α
M3 M4 gm1
Vπ 1 rO2
_

≈
M1 M2

v x = ro 2 iout
iin = k p W
L (v x − VT )2 (1 + λ v x ) iout + g m v x = (vout − v x ) / ro 4

iout = k p W
L (v x − VT )2 (1 + λ v y ) (
iout 1 + g m ro 2 + ro 2
ro 4 ) = vr
out

o4
if v x ≈ v y
vout
⇒ iout = iin Z out =
iout
= ro 4 + g m ro 2 ro 4 + ro 2
 CL
CS IS RS RL CL
CS IS RS RL

Iout
Iout

⇒
Iin Iin
Cgd4

+ +
α gm4 vx3 rO4 Cdb4 α
cgs3+ cgs4 + cdb3 Vx3 + rgs3+ ro3+ rgs4 cgs3+ cgs4 + cdb3+cgd4 Vx3 gm4 vx3 rO4 Cdb4+Cdb4
gm3 gm3
_ Cgd2 _

+ +
α +r +r +r α Cdb2+Cdb2
cgs1+ cgs2 + cdb1 gm2 vx1 rO2 Cdb2 cgs1+ cgs2 + cdb1+cgd2 gm2 vx1 rO2
Vx1 gm1 gs1 o1 gs2 Vx1 gm1
_ _


τ1 = 

c gd2 + c gs1 + c gs2 + c db1
2
+ cs  ( g2
 m
Rs ) ≈ c s
2
g m1

 fo = 21π τ +1 τ ≈ 21π τ1
 1 2 2

τ2 = (
c gd2 + c db2
2
+ c L ) (ro RL) ≈ c L RL .

 VDD

2 4 k T ∆f
i n ,R s =
iRs
Iout
Rs
2
i n ,M 1 = 2 k T ( 2 gm
3 ) ∆f
M4

= 2k T( ) ∆f
M3
2 2 gm
i n ,M 2 3

= 2k T( ) ∆f
M1 M2 2 2 gm
i n ,M 3 3

= 2k T( ) ∆f
2 2 gm
i n ,M 4 3

2
i n ,out = 4 k T ∆f ( 1
Rs + 4 g3m )

NF =
i n ,out
2

=
(
4 k T ∆f R1s + 4 g3m )
4g R
= 1+ m s
i n ,R s
2
4 k T ∆f 3
Rs
Wilson Current Mirror

VDD

iin Ib
Iout

M3 M4

M1 M2

- Uses shunt-series feedback to increase the output impedance.

-It has only a half of the cascode output impedance.
- M3 maintains the same drain-source voltages in M1 and M2
 Iout

Rs +
1
vx gm3
- gm4 vx rO4

gm1 vy rO1 vy
1 i out
gm2
vy =
g m2

   
 1  g m1  1  i
- v x = − g m1 v y  ≈−

1
+ 1
 g m2  1
+ 1  out

r01 1 +R
gm3 s
  r01 Rs 

( v out − v y )  g g  1  1  v out
i out = g m4 v x + ⇒ i out  1+ m1 m 4  1 1  + g r  =
ro4 
 m 2 o 4  ro 4
gm2
  r01 + R s

If gm1= gm2= gm3= gm4

Z out = ro 4  1 + g m (ro1 R s ) +
1  ≈ r  g mro1 
g m 2ro 4  o4  
   2 
 vin

Iin

Rs +
1
vx gm3
-
vz
vy

gm1 vy rO1
1
gm4 vx rO4 gm2

g m4 g m4
vy ≈ - vx = - i in
g m2 g m3 g m2

vz v
i in = g m1 v x + ⇒ i out  1+ g m1 g m 4  = z
ro4  g m 3 g m 2  ro4

If gm1= gm2= gm3= gm4

(
Z out = ro4 2ro 4 + 1
gm3
) ≈ 2r o4
 CL
CS IS RS RL
CS IS RS CL
RL
Iout

⇒
Iout
Iin
Cgd4 Iin

+
α gm4 vx3 rO4 Cdb4 +
Vx3 α
cgs3+ cgs4 + cdb3 gm3 Vx3 gm4 vx3 rO4 Cgd3+Cdb4
_ Cgd1 gm3
_
Cgd3+cgs3+ cgs4 + cdb3
+
Cdb1 α +
gm1 vx1 rO1 Vx1 gm2 Cgd1+Cdb1 gm1 vx1 r α
cgs1+ cgs2 + cdb1 O1 Vx1
_ gm2 Cgd1+cgs1+ cgs2 + cdb1
_


τ1 = ([(c gd3 + c gs3 + c gs 4 + c db3 ) ↔ (c gd1 + c db1 ) ] )

c s  (ro1 + g 1
 m

R s )

≈ Rs cs 
 fo = 21π τ +1 τ ≈ 21π τ1

1 2 2

τ 2 = (( c gd1 + c gs1 + c gs 2 + c db1 ) ↔ ( c gd3 + c db4 ) c L )) ((ro + 1

gm2
) RL ) ≈ c L RL .

Low Voltage Current Mirror

VDD

iin Ib
1
Iout
Z in =
V bias
g m1
M3 M4

M1 M2 Z out = g m4 ro1 ro4

- Only requires 0.1 to 0.3 volts to operate.

- Often used for low power applications.
 CL
CS IS RS RL
CS IS RS CL
RL
Iout

⇒
Iout
Iin
Cgd4 Iin

rO3 rO4 Cdb4 +

cgs3+ cgs4 + cdb3
Cgd1 Vx3 rO3 rO4 Cdb4+Cgd4
Cgs1+Cgs2+Cdb3+Cgd3
_
+ gm2 vin
α
Cdb1 Vx1 gm1 vin rO2 +
gm1
_ cgs1+ cgs2 + cdb1 Vx1
Csb3+Cgs3+Cgd1+Cdb1 rO2 gm2 vin Cgs4+csb4+ cgd2 + cdb2
gm1 vin rO1
_


(
τ 1 = ( c sb3 + c gs3 + c gd 1 + c db1 ) (c gs1 + c gs2 + c gd3 + c db3 ) )
c s (ro1 ro1 Rs ) ≈ Cs R s 
 fo = 21π τ +1 τ ≈ 21π τ1

1 2 2

( ) ≈ c RL

τ 2 = ( c gs4 + c sb4 + c gd 2 + c db2 + c gd1 ) (c db4 + c gd3 ) c L (ro4 ro2 RL ) L .
Low Voltage Current Mirror: High Frequency effects.

VDD

iin Ib
Iout The large signal output current is given by:
i out = - i in + iC in = - i in + C in 2 β d
Vbias
i in + i b
dt
M3 M4

H D 2 (C in ) ω<ω ≈ - iˆ ω
Using Taylor series, and substituting iin1=î sin( ωt), we can
Cd1
M1 M2
Cd2
obtain the harmonic distortion component
0 ω0 order:
4 ofi bsecond
Cin
2
H D 3 (C in ) ω <ω ≈ 3  ˆ 
 i  ω
0 32  i b  ω0
and third order:

2i 2i m i cos (ω t)
= V
v inFor th + frequencies
signal
b
+ C1 iabove
β in ∫
in dt = the +
Vthcurrent
b
in −
imirror b
pole β ω C in
frequency the input voltage can be expressed as:

2 2 2 2
ω0 m i b ω0 m i b ω0 m i b
i out = cos (ω t) + cos ( 2ωt ) + + ib
ω 8ω
2
8ω
2

since iout=β /2 (vin-Vth)2:

Low Voltage Current Mirror: High Frequency effects.

So, we only have a second order component:

H D 2 (C in ) ω >ω ≈ 1 iˆ ω0
0 8 ib ω

Combining with the low frequency harmonic  distortion

-1
 H (Ccomponent:
-1
 = 1 iˆ ω ω0
H D 2 (C in ) ≈  H D 2 (C in )  +  ) 
 ω < ω0  
D2 in
ω > ω0  4 i b 2ω 2 + ω02

2 2
ˆ  Vth   ω ω0 
H D2 = 1 i   +
 2 

8 ib 2
 VGS − Vth   2ω + ω0 
If it is now combined with the threshold mismatch harmonic distortion, we obtain:

2 2 2
 ˆ   ∆Vth   3 ω 
H D3 = 1 i    +
 

8  ib   VGS − Vth   ω0 
And the third harmonic as:
Simulated and theoretical harmonic distortion .
 True Low Voltage Current Mirror rO1

Iout
VDD
gm1 v1

_ +
RB Ib Iout
Vbias
V1 V2
rO3 gm3 v2
M1 Iin Rs C1 C2 rOB _
+
RS

Iin M3
where
M2
C1=CGS1+CSB1+CDB2+Cin
and
C2=CGS2+CGS3+CDB1+CB

 G s +g +g +s C −g o 1   v1  i 
 =  in 
o1 m1 1
  


−g o 1 −g m 1 g o 1 +G B +s C 2  v 2 
  0 
 

1
i out gm3
( g o1 + g m1 )
=
i in ( G s + g o 1 + g m 1 + sC 1 )( g 01 + G B + sC 2 ) − g 01 ( g o 1 + g m 1 )

i out 1 1 1
H(s) = = ≈ +
i in 
1 + g 1 s 
1 + g 2 s 
  1 + g 1 s 
  1 + g 2 s 
C C C C
 m1  B   m1   B


Dominant pole
AC Analysis rO1 DC Analysis
Iin
gm1 v1

_ + rO1

V1 V2
rO3 gm3 v2 Iin
Iin Rs C1 C2 rOB _ gm1 v1
+
_
+

V1 V2 gm3 v2
rO3
Iin Rs _ rOB
+

g +g +s C − g o1   v in   i 
  =  in 
o1 m1 1
 
 − g o 1 − g m 1 g o 1 + G B + s C 2   v 2   0 
 g o1 + g m1 − go1   v in   i 
    =  in 
v in ( g o1 + g m1 ) − g −
 o 1 m 1g g o1
+ G B   v 2   0 
=
i in ( g o 1 + g m 1 + sC 1 )( g 01 + G B + sC 2 ) − g 01 ( g o 1 + g m 1 )
v in ( g o1 + g m1 )
=
v in g m1 i in ( g o 1 + g m 1 )( g 01 + G B ) − g 01 ( g o 1 + g m 1 )
Z in ( s ) = =
i in ( G B + C 1 s )( g m 1 + C 2 s )
v in g m1
Z in = =
i in G B ( g m 1 + g o 1 )
AC Analysis DC Analysis
rO1

Iout
rO1
gm1 v1

_
gm1 v1 +
Iout
_ V1 V2
Rs rO2 RL gm2 v2
_ rOB
V1 +
C2 RB CL+Cgd3 rO3 RL gm2 v2
Rs C1
+

v
(
Z out ( s ) = out = R L ro 2 ) 1 ≈

RL Z out =
v out
i out
( )
= R L ro 2 ≈ R L
i out  ( C gd 3 + C L ) s  1+ s R LCL
Wide Swing Current Mirror
VDD

Iout
Ibias iin

M5 M4 M1

W/L W/L W/L

(n+1)2 n2 n2

M3 M2

W/L W/L

Main idea: Biasing M2 and M3 to be close to the minimum possible,

at the edge of triode region.

M3 and M4 act as a diode connected transistor.

M1 and M4 matches the drain-source voltages in M2 and M3 .

Ibias is set to the largest expected value of Iin

To determine the bias voltages, if Veff is the gate-source voltage for M2 and M3, and
the drain currents are equal, we have:
2 I D2
Veff = Veff 2 = Veff 3 =
µ n Cox WL

For current scaling the gate-source voltages in M1 and M4 are given by :

Veff 5 = (n + 1)Veff Veff 1 = Veff 4 = nVeff

So :
VG 5 = VG 4 = VG 1 = (n + 1)Veff + VT

Furthermore:
VDS 2 = VDS 3 = VG 5 − VGS 1 = VG 5 − (nVeff + VT ) = Veff

That puts M2 and M3 at the edge of triode region.

Vout > Veff 1 + Veff 2 = (n + 1) Veff

If n=1 (a common choice)

Vout > 2 Veff
To assure all transistors operating in active region, we need:
VDS > 2 Veff 4 = nVeff

to assure M4 in the active region. To find VDS4

VDS 4 = VG 3 − VDS 3 = ( Veff − VT ) − Veff = VT

To assure M4 in the active region:

VT > nVeff for M 4

- Due to VDS2 and VDS3 will be larger than necessary, except when Iin is
maximum, some swing will be lost

- A common modification is to choose M2 and M3 a little larger than

the minimum allowable gate length, but M1 and M4 will have larger
lengths.

- This topology is very popular in CMOS analog design.

Accurate Current Mirror Topologies for Large Signal Amplitudes
VDD

Maximum current swing can be extended by using

Ib modified transistor-biasing schemes.

R
Iout

iin A modified low voltage cascode with self-adjusting cascode

M3 M4 bias is shown.

M1 M2

Drawbacks:
- R need to be large.
- MOS in triode resistors cause large parasitic
capacitances.
- The bandwidth of the mirror is reduced.
- High frequency distortion may increase.
Accurate Current Mirror Topologies for Large Signal Amplitudes

Iout
Iin

+
A
M3
-

M1 M2

The only way to render the mirror insensitive to channel

length modulation is to force the drain voltage of the output
mirror transistors M2 to follow the input voltage.
Accurate Current Mirror Topologies for Large Signal Amplitudes
VDD

Ibias

Ibias Ibias

iin
M7 Iout
C

M4 M4

M1 M6 M2

An alternative method is toassure saturation region operation is to use a level

shifter to increase the mirror input voltage

The Wilson-mirror like input isolates M1, M2 and M6 transistors from the input
node. That reduce the input capacitances of those transistors
Low Voltage Current Mirror Topologies

Active-input Current Mirror

Iin Iout
The OPAMP allows a level shifting, reducing the
Vref requirements of at least to have a VGS at the input
-
Aact
voltage.
+
The input impedance is reduced, and the internal node
has a very low resistance associated with the M1 and M2
gate capacitors.
M1 M2
It has been used for high precision applications.
Low Voltage Current Mirror Topologies

Active-input Regulated Cascode Current Mirror

Iout
The second OPAMP increase the output
Vref impedance of the mirror, without degradation of
Iin
+ the output voltage swing.
MC
-
The extra devices can be OPAMPs or common
-
source voltage-gin stag..
+
It has been used for high precision applications.

M1 Mm
Low Voltage Current Mirror Topologies

Active-input Regulated Cascode Current Mirror

Iin Iout
Vref
The second OPAMP increase the output
+ + impedance of the mirror, without degradation of
MC
M2
- -
the output voltage swing.

The extra devices can be OPAMPs or common

source voltage-gin stag..

Mm
It has been used for high precision applications.
M1
Low Voltage Current Mirror Topologies

High swing current mirror with input current injected to the source of M3

IB

IB
Vcas
M2
Iout
Iin

M3
M1

- The output requirement is only a Vdsat

Low Voltage Current Mirror Topologies

Podranov´s structure

Iout
IB IB
M5

Vcas
M2 M4

Iin

M3
M1

- M1 and M3 operate in the ohmic region

- Extremely low input voltage drop due to ohmic region operation.
- It is more sensitive to mismatches.
Low Voltage Current Mirror Topologies

Itakura structure

Iin Iout
Vref

M2 M4

-
X

M1 M3

- Force to M1 and M3 to have the same Vds, which operate in the triode region
- A lower output compliance voltage is achieved.
- The price for a low voltage operation is a slightly degraded frequency response
Low Voltage Current Mirror Topologies

Ramirez current mirror with input level shift

IB1
Iin Vshift

⇒
Iin Iout
-+
M3 M4

M1 M2
M1 M2

IB2

- A level shifter is used to have a low input voltage Vgs - Vshift

- Set the minimum input voltage in a Vds.
Low Voltage Current Mirror Topologies

You ´s structure

ROB Iin

Iout

-
AFB

M1 M2

- A negative output impedance is used to implement a LV current tail

( W )
ro = − ROB W L M1

( L) M2
Enhanced Output Impedance Current Mirror

VDD

Iout
iin Ib2 Ib2

M4 M1

M6 M3

M5 M2

g m1 g m 3 rds1 rds 2 rds 3

R out =
2
Wide Swing Current Mirror With Enhanced Output
Impedance VDD

Iout
iin~ 7 Ibias 4 Ibias Ibias Ibias 4 Ibias

M5=70 M1=70

M8=10
M7=10 M3=10
M4=10

M2=80
M6=80
A Modified Wide Swing Current Mirror With Enhanced
Output Impedance
VDD

Iout
iin Ibias 4 I bias

Vcas M6=70 M1=70

M4=10
M3=10

M7=70 M2=70
M5=10