Chap05 (7 5 06)

Chapter 5 – Introduction (7/5/06) Page 5.0-1.
CHAPTER 5 – CMOS AMPLIFIERS

INTRODUCTION
Objective
Illustrate the analysis and design of amplifiers using CMOS technology.
Topics
• Introduction and Characterization
• Inverting Amplifiers
• Differential Amplifiers
• Cascode Amplifiers
Functional blocks or circuits
• Current Amplifiers (Perform a complex function)
• Output Amplifiers
Blocks or circuits
Chapter 5 (Combination of primitives, independent)
Sub-blocks or subcircuits
(A primitive, not independent)
Fig. 5.0-1
CMOS Analog Circuit Design © P.E. Allen - 2006
Types of Amplifiers
Type of Amplifier Output Ideal Input Ideal Output

Gain = Input Resistance Resistance
Voltage Output Voltage Infinite Zero
Av = Input Voltage
Current Output Current Zero Infinite

Ai = Input Current
Transconductance Output Current Infinite Infinite

Gm = Input Voltage
Transresistance Output Voltage Zero Zero

Rm = Input Current
Most CMOS amplifiers fit naturally into the transconductance amplifier category as they
have large input resistance and fairly large output resistance.
If the load resistance is high, the CMOS transconductance amplifier is essentially a
voltage amplifier.

Characterization of an Amplifier
1.) Large signal static characterization:
• Plot of output versus input (transfer curve)
• Large signal gain
• Output and input swing limits
2.) Small signal static characterization:
• AC gain
• AC input resistance
• AC output resistance
3.) Small signal dynamic characterization:
• Bandwidth
• Noise
• Power supply rejection
4.) Large signal dynamic characterization:
• Slew rate
• Nonlinearity
Components of a CMOS Voltage/Transconductance Amplifier

1.) A transconductance stage that converts the input voltage to current.
2.) A transresistance stage (load) that converts the current from the transconductance
stage back to voltage.
Transconductance Transresistance
Stage Stage
Input Output Input Output
Voltage Voltage Voltage Voltage Voltage-to Current Current-to Voltage
Amplifier Current Voltage
Conversion Conversion
Voltage Amplifier 060607-01

Illustration of Voltage Amplifier Components

VDD VCC
+ + VEB + +
VT+VON - VEB +
VT+ -
2VON VEC(sat)
- -
IBias IBias
MOS Loads BJT Loads
IBias IBias
+ +
VBE +
VT+ VCE(sat)
2VON -
+ +
- VT+V O N VBE
- -
MOS Transconductors BJT Transconductors Fig320-01
Transconductance stages are in the lower two shaded boxes

Transresistance stages (loads) are in the upper two shaded boxes (actually, the
transconductance output also serves as a part of the load or transresistance stage)
Amplifier Notation
Input Output VDD Input Output

Voltage Voltage Voltage Voltage Voltage Voltage
Amplifier Amplifier VDD
VSS
060607-02 Split Power Supplies Single Power Supply
Simpler notation:
VDD VDD
Input Output Input Output
Voltage Voltage Voltage Voltage Voltage Voltage
Amplifier Amplifier
VSS
060607-03 Split Power Supplies Single Power Supply

Inverting and Noninverting Amplifiers

The types of amplifiers are based on the various configurations of the actual transistors.
If we assume that one terminal of the transistor is grounded, then three possibilities
result:
VDD VDD VDD
Load Load vin


 vout  vout vout
  
vin vin
Load
Common Common Common

060608-01 Source Gate Drain
Note that there are two categories of amplifiers:

1.) Noninverting - Those whose input and output are in phase (common gate and
common drain)
2.) Inverting - Those whose input and output are out of phase (common source)
Chapter 5 – Section 1 (7/5/06) Page 5.1-1.
SECTION 5.1 – INVERTING AMPLIFIERS

Types of Inverting Amplifiers
The inverting amplifier or common source amplifier differs only by the type of load.
Possible types of inverting amplifiers are shown below:
VDD VDD VDD VDD
VPBias1
M2 M2 M2
Load
vin vout
vout vout vout
vin vin M1 vin M1 M1
060608-02 Class A Amplifiers Push-Pull Amplifier

Class A amplifiers – The current in the load transistor (M2) flows during the entire period
of a sinusoidal input.
Push-Pull (Class B and Class AB) amplifiers – The current flows in each transistor (M1
and M2) for less than the entire period of a sinusoidal input. Class B is 180° and Class
AB is between 180° and 360°.
ACTIVE LOAD INVERTER

Voltage Transfer Characteristic of the Active Load Inverter
vIN=5.0V vIN=4.5V
vIN=4.0V
0.5 5V
KJ vIN=3.5V
I vIN
=2.5V W2 = 1m
0.4 H vIN=3.0V
G
L2 1m
F I
M2 D
0.3
ID (mA)
M1 +
0.2
E vIN=2.0V vOUT
M2 + W1 = 2m
vIN
0.1 L1 1m
vIN
=1.5V - -
D
C A,B vIN=1.0V
0.0 0 1 2 3 4 5
vOUT 5
AB M2 cutoff
4 M2 saturated
C
3
vOUT
D
2
E
F
1 G H IJK
Fig. 320-02 0
0 1 2v 3 4 5
IN
The boundary between active and saturation operation for M1 is

vDS1  vGS1 - VTN  vOUT  vIN - 0.7V
Large-Signal Voltage Swing Limits of the Active Load Inverter

Maximum output voltage, vOUT(max):
vOUT(max)  VDD - |VTP|
(ignores subthreshold current influence on the MOSFET)
Minimum output voltage, vOUT(min):
Assume that M1 is nonsaturated and that VT1 = |VT2| = VT.
vDS1  vGS1 - VTN  vOUT  vIN - 0.7V
The current through M1 is
 

 vDS 1   (vOUT)2
and the 1rent
iD cur (vGS1through M2is
 VT)vDS1 2   1 (V DD  VT)(vOUT )  2 

2 2 2
iD  2 (vSG2  VT)2  2 (VDD  vOUT  VT)2  2 (vOUT  VT  VDD)2
Equating these currents gives the minimum vOUT as,
VDD  VT
vOUT(min)  VDD  VT  1  ( / )
2 1

Small-Signal Midband Performance of the Active Load Inverter

The development of the small-signal model for the active load inverter is shown below:
VDD
S2=B2
M2 gm2vgs2
rds2 Rout
ID vOUT G1
D1=D2=G2
+ + + +
vIN vin gm1vgs1 vout vin g vout
M1 rds1 m1vin rds1 gm2vout rds2
- - - -
S1=B1 Fig. 320-03
Sum the currents at the output node to get,
gm1vin + gds1vout + gm2vout + gds2vout = 0
Solving for the voltage gain, vout/vin, gives
K' W L 
vout gm1 gm1  N 1 2

vin gds1  gds2  gm2   gm2   
 PL W
K' 
1 2
The small-signal output resistance can also be found from the above by letting vin = 0 to
get,
1 1
Rout  gds1  gds2  gm2  gm2
Frequency Response of the MOS Diode Load Inverter

Incorporation of the parasitic Cgs2 VDD
capacitors into the small-signal
model: M2
Cbd2 CM
If we assume the input voltage has a Vout + +
small source resistance, then we can Cgd1 Cbd1 Vin gmVin Vout
Rout Cout
write the following: CL - -
Vin M1
sCM(Vout-Vin) + gmVin
Cgs1
+ GoutVout + sCoutVout = 0 Fig. 320-04
 Vout(Gout + sCM + sCout) = - (gm – sCM)Vin

 sCM  
 s 
 1- g  gmR out 1
  - z1

Vout -(gm – sCM) m  
Vin = Gout+ sCM + sCout = -gmRout 1+ sRout(CM + Cout) = s
1 - p1
1 gm1
where gm  gm1, p1  Rout(Cout+CM  and z1 = C M
1
and Rout  [gds1gds2gm2]-1  gm2 , CM = Cgd1 , and Cout  Cbd1Cbd2Cgs2CL

Frequency Response of the MOS Diode Load Inverter - Continued

If |p1| < z1, then the -3dB frequency is approximately equal to [Rout(Cout+CM)]-1.
dB
20log10(gmRout)
z1
0dB log10
|p1|  -3dB
0512-06-02.EPS
Observation:
The poles in a MOSFET circuit can be found by summing the capacitance
connected to a node and multiplying this capacitance times the equivalent resistance from
this node to ground and inverting the product.
(See Appendix 5A for details on frequency response and Bode plots)
Example 5.1-1 - Performance of an Active Resistor-Load Inverter

Calculate the output-voltage swing limits for VDD = 5 volts, the small-signal gain,
the output resistance, and the -3 dB frequency of active load inverter if (W1/L1) is 2 μm/1
μm and W2/L2 = 1 μm/1 μm, Cgd1 = 100fF, Cbd1 = 200fF, Cbd2 = 100fF, Cgs2 = 200fF,
CL = 1 pF, and ID1 = ID2 = 100μA, using the parameters in Table 3.1-2.
Solution
From the above results we find that:
vOUT(max) = 4.3 volts
vOUT(min) = 0.418 volts
Small-signal voltage gain = -1.92V/V
Rout = 9.17 k including gds1 and gds2 and 10 k ignoring gds1 and gds2
z1 = 2.10x109 rads/sec
p1 = -64.1x106 rads/sec.
Thus, the -3 dB frequency is 10.2 MHz.

CURRENT SOURCE INVERTER

Voltage Transfer Characteristic of the Current Source Inverter
vIN=5.0V vIN=4.5V
vIN=4.0V
0.5 5V
vIN=3.5V
0.4 vIN=3.0V vIN=2.5V W22 m 
=
L2 1m
2.5V M2 ID
0.3
ID (mA) KJIH F E vIN=2.0V M1 +
0.2 vOUT
G M2 + W1 = 2m
vIN L1 1m
0.1 D
vIN=1.5V --
C
A,B vIN=1.0V
0.00 1 2 3 4 5 5
vOUT A B C
D
4
M2 active
3 M2 saturated
vOUT
2
E
1 F
GH IJK
0
IN
0 1 2v 3 4 5 Fig. 5.1-5
Regions of operation for the transistors:
M1: vDS1  vGS1 -VTn  vOUT  vIN - 0.7V
M2: vSD2  vSG2 - |VTp|  VDD-vOUT VDD -VGG2 - |VTp|  vOUT  3.2V
Large-Signal Voltage Swing Limits of the Current Source Load Inverter

vOUT (max)  VDD
Assume that M1 is nonsaturated. The minimum output voltage is,
    V DD- VGG- | VT2|2
vOUT(min)  v  2 
- 1  
OUT(min) = (VDD - VT1) 1 - 1 VDD - VT1  
This result assumes that vIN is taken to VDD.

Small-Signal Midband Performance of the Current Source Load Inverter

Small-Signal Model:
VDD
S2=B2
M2 rds2
Rout
VGG2 ID vOUT G1 D1=D2
+ + + +
vIN vin gm1vgs1 vout vin g vout
M1 rds1 m1vin rds1 rds2
- - - -
S1=B1=G2 Fig. 5.1-5B
Midband Performance:
gm1 2K' W   
vout N 1    1  1 1 1
 
vin gds1  gds2  L1ID 
 
 1    
2 D !!! and R out  gds1  gds2  DI ( 1  ) 2
vout
vin Strong Inversion
Weak
Invers-
ion
log(IBias)
 1μA 060614-01
Frequency Response of the Current Source Load Inverter

Incorporation of the parasitic VDD
capacitors into the small-signal Cgs2
model (x is connected to VGG2): x M2

Cbd2 CM
Cgd2 Vout
If we assume the input voltage + +
Cgd1 Cbd1 Vin gmVin Vout
has a small source resistance, Rout Cout
CL - -
then we can write the following: Vin M1
s 

 Fig. 5.1-4
Vout(s) gmR
out 1 - z 1


Vin(s)  s
1 - p1
1 gm
where gm  gm1, p1  Rout(Cout+CM  and z1 = CM
1
and Rout  gds1 + gds2 and Cout  Cgd2  Cbd1  Cbd2  CL CM = Cgd1
Therefore, if |p1|<|z1|, then the 3 dB frequency response can be expressed as
gds1  gds2
-3dB  1  Cgd1  Cgd2  Cbd1  Cbd2  CL

Example 5.1-2 - Performance of a Current-Sink Inverter VDD

+
A current-sink inverter is shown in Fig. 5.1-7. Assume VSG1
-
that W1  2 m, L1  1 m, W2  1 m, L2  1m, VDD  5 vIN M1
ID vOUT
volts, VGG1 = 3 volts, and the parameters of Table 3.1-2
M2
describe M1 and M2. Use the capacitor values of Example VGG1
5.1-1 (Cgd1  Cgd2). Calculate the output-swing limits and the
small-signal performance. Figure 5.1-7 Current sink CMOS inverter.
Solution
To attain the output signal-swing limitations, we treat Fig. 5.1-7 as a current source
CMOS inverter with PMOS parameters for the NMOS and NMOS parameters for the
PMOS and use NMOS equations. Using a prime notation to designate the results of the
current source CMOS inverter that exchanges the PMOS and NMOS model parameters,
 
 
3-0.7 2 

110·1
vOUT(max)’ = 5V and vOUT(min)’ = (5-0.7)1 - 1 -  50·2 5-0-0.7   = 0.74V
In terms of the current sink CMOS inverter, these limits are subtracted from 5V to get
vOUT(max) = 4.26V and v OUT (min) = 0V.
To find the small signal performance,
110·1 first calculate the dc current. The dc current, ID, is
K ’W
I = N 1 (V -V ) =2 (3-0.7)2 = 291μA
D 2L1 GG1 TN 2·1
vout/vin = 9.2V/V, Rout = 38.1 k and f-3dB = 2.78 MHz.
PUSH-PULL INVERTER
Voltage Transfer Characteristic of the Push-Pull Inverter
v =4.5V
vIN=5.0V IN vIN
=4.0V vIN=3.5V
1.0 5V
vIN=0.5V
vIN=1.0V W2 = 2m
0.8
vIN=1.5V L2 1m
vIN=2.0V vIN=3.0V
M2 ID
0.6
vIN=2.5V + M1 +
ID (mA)
0.4 vIN=2.5V vOUT

F vIN W1 =1m
G vIN=3.0V E L1 1m
0.2 vIN=2.0V
H
- -
vIN=3.5V vIN=4.5V D vIN=1.5V
I
0.0 vIN=1.0V
0 1 2 3 4 C
J,K vOUT A,B 5
ABC D
E
4 Note
the rail-
3 to-rail
output
2
vOUT
F voltage
swing
1
G
H IJK
0
0 1 2v 3 4 5 Fig. 5.1-8
IN
Regions of operation for M1 and M2:
M1: vDS1  vGS1 - VT1  vOUT  vIN - 0.7V
M2: vSD2  vSG2-|VT2|  VDD -vOUT  VDD -vIN-|VT2|  vOUT  vIN + 0.7V
Small-Signal Performance of the Push-Pull Amplifier

5V
CM
+ +
M2
vin gm1vin rds1 gm2vin rds2 vout
+ + Cout
M1 - -
vin vout
Fig. 5.1-9
- -
Small-signal analysis gives the following results:


vout (gm1  gm2)  K'N(W1/L1)  K'P(W2/L2)
  (2/I ) 
vin  gds1  gds2 D
 1  2 
1
Rout  gds1 + gds2
gm1+gm2 gm1+gm2 g  gds2)
z = CM = Cgd1+Cgd2 and p1  Cgd1  Cgd2 ds1
Cbd1  Cbd2  CL
If z1 > |p1|, then
gds1  gds2
-3dB  Cgd1  Cgd2  Cbd1  Cbd2  CL
Example 5.1-3 - Performance of a Push-Pull Inverter

The performance of a push-pull CMOS inverter is to be examined. Assume that W1 
1 m, L1  1 m, W2  2 m, L2  1m, VDD  5 volts, and use the parameters of Table
3.1-2 to model M1 and M2. Use the capacitor values of Example 5.1-1 (Cgd1  Cgd2).
Calculate the output-swing limits and the small-signal performance assuming that ID1 =
ID2 = 300μA.
Solution
The output swing is seen to be from 0V to 5V. In order to find the small signal
performance, we will make the important assumption that both transistors are operating
in the saturation region. Therefore:
vout -257μS - 245μS
vin = 12μS + 15μS = -18.6V/V
Rout = 37 k
f-3dB = 2.86 MHz
and
z1 = 399 MHz

NOISE ANALYSIS OF INVERTING AMPLIFIERS

Noise Analysis of Inverting Amplifiers
Noise model:
VDD Noise VDD Noise
en22 Free Free
MOSFETs MOSFETs
* M2 M2
eout2 eout2
en12 eeq2
vin vin
* M1 * M1
Fig. 5.1-10
Approach:
1.) Assume a mean-square input-voltage-noise spectral density en2 in series with the gate
of each MOSFET.
(This step assumes that the MOSFET is the common source configuration.)
2.) Calculate the output-voltage-noise spectral density, eout2 (Assume all sources are
additive).
3.) Refer the output-voltage-noise spectral density back to the input to get equivalent
input noise eeq2.
4.) Substitute the type of noise source, 1/f or thermal.
Noise Analysis of the Active Load Inverter

1.) See model to the right. VDD VDD
Noise Noise
g  Free Free
 m12 en2
2
2  
2.) e out = e n1 gm2 + en22
2 MOSFETs MOSFETs
* M2 M2
  m2 eout

2 eout 2
 g e 2n22  en12 eeq2
3.) eeq 2 = e 2
1+ g     
n1  e
 m1  n1  vin
* M1 vin
* M1
Up to now, the type of noise is not defined. Fig. 5.1-10
1/f Noise
KF B
Substituting en2= 2fC WLK’ = fWL , into the above gives,
ox
 B
1      2K'
2B  1L 


1  1/2 
B
   
K'2B2 L 1 1/2


eeq(1/f) = fW1L1
2
1

 
K'1B1

  L2
 
 
 eeq(1/f)  fW1L1  1 K'1B1 L2 
To minimize 1/f noise, 1.) Make L2>>L1, 2.) increase the value of W1 and 3.) choose M1
as a PMOS.
Thermal Noise
8kT
Substituting en2= 3g into the above gives,
m

   W L K'  1/2

8kT   L 2 W 1K'12 1/2 

eeq(th) 3[2K'1(W/L)1I1]1/2 1 2 1 



To minimize thermal noise, maximize the gain of the inverter.

Noise Analysis of the Active Load Inverter - Continued

When calculating the contribution of en22 to eout2, it was assumed that the gain was
unity. To verify this assumption consider the following model:
en22
* + +
vgs2 gm2vgs2 rds1 rds2 eout2
- _
Fig. 5.1-11
We can show that,
eout2  gm2(rds1||rds2)  2
en22 = 1 + gm2(rds1||rds2) = 1
Noise Analysis of the Current Source Load Inverting Amplifier

Model:
VDD Noise VDD Noise
en22 Free Free
MOSFETs MOSFETs
* M2 M2
VGG2
eout2 eout2
en12 eeq2
vin vin
* M1 * M1
Fig. 5.1-12.
The output-voltage-noise spectral density of this inverter can be written as,
eout2 = (gm1rout)2en12 + (gm2rout)2en22
or
(gm2rout)2  g  en2 2
  m22 
e n12 + (gm1rout) 2en2 = en1 1 + gm1 en12 
eeq2 = 2 2
This result is identical with the active load inverter.

Thus the noise performance of the two circuits are equivalent although the small-signal
voltage gain is significantly different.

Noise Analysis of the Push-Pull Amplifier

Model:
VDD Noise
en22 Free
MOSFETs
* M2
vin eout2
en12
* M1
Fig. 5.1-13.
The equivalent input-voltage-noise spectral density of the push-pull inverter can be found
as
 g e   g e 
m1 n1  2 m2 n2  2
eeq =   
+ gm1 + gm  
gm1 + gm2 2
If the two transconductances are balanced (gm1 = gm2), then the noise contribution of
each device is divided by two.
The total noise contribution can only be reduced by reducing the noise contribution of
each device.
(Basically, both M1 and M2 act like the “load” transistor and “input” transistor, so there
is no defined input transistor that can cause the noise of the load transistor to be
insignificant.)
Summary of CMOS Inverting Amplifiers
AC Voltage AC Output Equivalent,

Inverter Bandwidth (CGB=0) input-referred,mean-
Gain Resistance
square noise voltage
p-channel -gm1 1 gm2
 g
CBD1+CGS1+CGS2+CBD2 m22
active load gm2 gm2 2+ e
en1 n2 gm1
2

inverter
Current -gm1 1 gds1+gds2
 g
CBD1+CGD1+CDG2+CBD2 m22
source load gds1+gds2 gds1+gds2 2+ e
en1 n2 g m1
2

inverter
Push-Pull -(gm1+gm2) 1 gds1+gds2 
g m1 en1 2  e 2
 gm1 n1
inverter CBD1+CGD1+CGS2+CBD2  +
  
gds1+gds2 gds1+gds2 + +
gm1 gm2 g m1 gm2 

SECTION 5.2 – DIFFERENTIAL AMPLIFIERS

CHARACTERIZATION OF A DIFFERENTIAL AMPLIFIER
What is a Differential Amplifier?
A differential amplifier is an amplifier that amplifies the difference between two
voltages and rejects the average or common mode value of the two voltages.
Differential and common mode voltages:
v1 and v2 are called single-ended voltages. They are voltages referenced to ac
ground.
The differential-mode input voltage, vID, is the voltage difference between v1 and v2.
The common-mode input voltage, vIC, is the average value of v1 and v2 .
v1+v2
 vID = v1 - v2 and vIC = 2  v1 = vIC + 0.5vID and v2 = vIC - 0.5vID
vID 
v+v 
 1 2
 
2 + vOUT = AVDvID ± AVCvIC = AVD(v1 - v2) ± A VC 2 
vID - + where
vIC vOUT AVD = differential-mode voltage gain
2
- AVC = common-mode voltage gain
Fig. 5.2-1B
Differential Amplifier Definitions

• Common mode rejection rato (CMRR)
A 
 VD
CMRR = AVC
CMRR is a measure of how well the differential amplifier rejects the common-mode
input voltage in favor of the differential-input voltage.
• Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over which
the differential amplifier continues to sense and amplify the difference signal with the
same gain.
Typically, the ICMR is defined by the common-mode voltage range over which all
MOSFETs remain in the saturation region.
• Output offset voltage (VOS(out))
The output offset voltage is the voltage which appears at the output of the differential
amplifier when the input terminals are connected together.
• Input offset voltage (VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the
differential voltage gain.
VOS(out)
VOS = AVD
Transconductance Characteristic of the Differential Amplifier

Consider the following n-channel differential VDD
amplifier (sometimes called a source-coupled
pair): iD1 iD2 M2 v
vG1 M1 G2
+ +
vID vGS1 vGS2
IBias - -
Where should bulk be connected? Consider a M4 M3 ISS
p-well, CMOS technology, VBulk
D1 G1 S1 S2 G2 D2 VDD
Fig. 5.2-2
n+ n+ p+ n+ n+ n+
p-well
n-substrate
Fig. 5.2-3
1.) Bulks connected to the sources: No modulation of VT but large common mode
parasitic capacitance.
2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but
modulation of VT.
If the technology is n-well CMOS, there is no choice. The bulks must be connected to
ground.
Transconductance Characteristic of the Differential Amplifier - Continued

Defining equations:
2i  2i  
 D11/2  D2 1/2
vID  vGS1  vGS2        and ISS  iD1  iD2
Solution:
 2
ISS ISS v ID 2vID1/2
4 4
2v 
2

ISS ISS vID  ID1/2
iD1  2  2  ISS  2  and iD2  2  2  ISS  2 
4ISS 
4ISS
which are valid for vID  2(ISS/)1/2.
Illustration of the result:
iD/ISS
1.0
0.8
iD1
0.6
0.4 iD2
Differentiating iD1 (or iD2) 0.2
vID
with respect to vID and -2.0 -1.414 0.0 1.414 2.0 (ISS/ß)0.5 Fig. 5.2-4
setting VID =0V gives
diD1 K' I W 
 1 SS 1 1/2
gm dvID (VID  0)  (ISS/4)1/2   4L1  (half the gm of an inverting amplifier)

Voltage Transfer Characteristic of the Differential Amplifier

In order to obtain the voltage transfer characteristic, a load for the differential amplifier
must be defined. We will select a current mirror load as illustrated below.
VDD
2m 2m
1m 1m
M3 M4
iD3 iD4 iOUT
2m 2m +
1m iD1 iD2
1m
V DD
+v M1 M2 + 2
GS1 vGS2 vOUT
- -
vG1 2m ISS vG2
1m
M5
- - -
VBias
Fig. 5.2-5
Note that output signal to ground is equivalent to the differential output signal due to the
current mirror.
The short-circuit, transconductance is given as
diOUT  
K'
 1I SSW 11/2
gm dvID (VID  0)  (ISS) 1/2   L1 

Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load
VDD = 5V
5
2μm 2μm
1μm 1μm M4 active
M4 iD4 iOUT 4
iD3 M3 M4 saturated
vOUT (Volts)
2μm 2μm +
1μm iD1 iD2 3
1μm
VIC = 2V
+ M1 M2 +
vGS1 - - vGS2 vOUT 2
2μm M2 saturated
vG1 1μm ISS vG2 1 M2 active
M5
- - -
VBias 0
-1 -0.5 0 0.5 1
vID (Volts) 060705-01
Regions of operation of the transistors:

M2 is saturated when,
vDS2  vGS2-VTN  vOUT-VS1  VIC-0.5vID-VS1-VTN  vOUT  VIC-VTN
where we have assumed that the region of transition for M2 is close to vID = 0V.
M4 is saturated when,
vSD4  vSG4 - |VTP|  VDD-vOUT  VSG4-|VTP|  vOUT  VDD-VSG4+|VTP|
The regions of operations shown on the voltage transfer function assume ISS = 100μA.
2·50
Note: VSG4 = 50·2 +|VTP| = 1 + |VTP|  vOUT  5 - 1 - 0.7 + 0.7 = 4V
Differential Amplifier Using p-channel Input MOSFETs

VDD
M5
VBias IDD
- -
vSG 1 vSG2
+ M1 +
M2
+ +
iD1 iD2 iOUT
iD3 iD4 +
vG1 vG2
M3 vOUT
M4
- - -
Fig. 5.2-7
Input Common Mode Range (ICMR) VDD

2m 2m
ICMR is found by setting vID = 0 and varying vIC 1m 1m
M3 M4
until one of the transistors leaves the saturation.
iD3 iD4 iOUT
Highest Common Mode Voltage 2m
1m iD1 2m iD2 +
Path from G1 through M1 and M3 to V DD: 1m
VDD
+ M1 M2 2
VIC(max) =VG1(max) =VG2(max) vGS1 vGS2 +
vOUT
- -
=VDD -VSG3 -VDS1(sat) +VGS1 vG1 2m
1m ISS vG2
or M5
- - -
VIC(max) = V DD - VSG3 + VTN1 VBias
Fig. 330-02
Path from G2 through M2 and M4 to VDD:
VIC(max)’ =VDD -VSD4(sat) -VDS2(sat) +VGS2
=VDD -VSD4(sat) + VTN2
 VIC(max) = VDD - VSG3 + VTN1
Lowest Common Mode Voltage (Assume a VSS for generality)
VIC(min)  VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
where we have assumed that VGS1 = VGS2 during changes in the input common mode
voltage.

Example 5.2-1 - Small-Signal Analysis of the Differential-Mode of the Diff. Amp

A requirement for differential-mode operation is that the differential amplifier is
balanced†.
VDD
M4 D1=G3=D3=G4 C3
M3
iD3 iD4 iout G1 v G2 rds1 S1=S2 rds2 D2=D4
+ id -
+ + +
iD1 iD2 + i3
vg1 vg2 1 rds5 i3 vout
M1 M2 C1
gm3 rds3 gm1vgs1 gm2vgs2 rds4 C2
- - -
vid vout S3 S4
M5 iout'
ISS G1 G2 D1=G3=D3=G4 D2=D4
VBias - + vid -
+ + +
vgs1 vgs2 i3 C3
1 vout
gm1vgs1 C1 g m2vgs2 i3 rds2 rds4 C2
- - rds1 rds3 gm3 -
S1=S2=S3=S4 Fig. 330-03
Differential Transconductance:
Assume that the output of the differential amplifier is an ac short.
gm1gm3rp1
iout’  1  gm3rp1 vgs1  gm2vgs2  gm1vgs1  gm2vgs2  gmdvid
where gm1  gm2  gmd, rp1  rds1rds3 and i'out designates the output current into a short
circuit.
†
It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to
use the assumption regardless.
Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - Continued

Output Resistance: Differential Voltage Gain:
1 vout gmd
rout  gds2 =grds4 ||r
ds2 ds4 A v  
vid gds2  gds4
If we assume that all transistors are in saturation and replace the small signal parameters
of gm and rds in terms of their large-signal model equivalents, we achieve
vout (K'1ISSW1/L1)1/2 2 K'1W 11/2 1
Av  vid  (2  4)(ISS/2)  2  4  ISSL 1   I
SS
Note that the small-signal gain is inversely vout
proportional to the square root of the bias vin Strong Inversion
current! Weak
Invers-
Example:
ion
If W1/L1 = 2μm/1μm and ISS = 50μA log(IBias)
(10μA), then  1μA 060614-01
Av(n-channel) = 46.6V/V (104.23V/V)
Av(p-channel) = 31.4V/V (70.27V/V)
1 1
rout  gds2 =gds4 = 0.444M (2.22M
25μA·0.09V-1

Common Mode Analysis for the Current Mirror Load Differential Amplifier
The current mirror load differential amplifier is not a good example for common mode
analysis because the current mirror rejects the common mode signal.
VDD
M3 M4
+
M2
M1 M2 vout  0V
vic
+ -
VBias M5
- Fig. 5.2-8A
Total common  Common mode  Common mode

     
mode Output =  output due to  -  output due to 
 due to vic   
M1-M3-M4 path   M2 path 
Therefore:
• The common mode output voltage should ideally be zero.
• Any voltage that exists at the output is due to mismatches in the gain between the two
different paths.
Small-Signal Analysis of the Common-Mode of the Differential Amplifier

The common-mode gain of the differential amplifier with a current mirror load is ideally
zero.
To illustrate the common-mode gain, we need a different type of load so we will consider
the following:
VDD VDD VDD
M3 M4 M3 M4 M3 M4
vo1 vo2 vo1 vo2 vo1 vo2
v1 v2
M1 M2 M1 M2 M1 M2
ISS M5x12 ISS
vid vid ISS 2 2
2 2 vic vic
M5
VBias VBias
Differential-mode circuit General circuit Common-mode circuit

Fig. 330-05
Differential-Mode Analysis:
vo1 gm1 vo2 gm2
vid = -2gm3 and vid = + 2gm4
Note that these voltage gains are half of the active load inverter voltage gain.
Small-Signal Analysis of the Common-Mode of the Differential Amplifier – Cont’d

Common-Mode Analysis:
Assume that rds1 is large and can be + vgs1 - gm1vgs1

+ +
ignored (greatly simplifies the vic 2rds5 rds3 1 vo1
analysis). rds1 gm3
- -
 vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1
Fig. 330-06
Solving for vgs1 gives
vic
vgs1 = 1 + 2gm1rds5
The single-ended output voltage, vo1, as a function of vic can be written as
vo1 gm1[rds3||(1/gm3)] (gm1/gm3) gds5
vic = - 1 + 2g r
m1 ds5
 - 1 + 2g r
m1 ds5
 - 2g m3
Common-Mode Rejection Ratio (CMRR):

|vo1/vid| gm1/2gm3
CMRR = |vo1/vic| = gds5/2gm3 = gm1rds5
How could you easily increase the CMRR of this differential amplifier?
Frequency Response of the Differential Amplifier

Back to the current mirror load differential amplifier:
VDD
Cgs3+Cgs4
Cbd3 M3 M4 Cbd4
Cgd1 Cgd4 iout'

Cgd2 + G1 G2 D1=G3=D3=G4 D2=D4
Cbd1 v-
+ id
vout + + +
Cbd2 CL - vgs1 vgs2 i3 C3
vid 1 vout
gm1vgs1 C1 gm2vgs2 i3 rds2 rds4 C2
M1 M2 - - gm3 -
M5 S1=S2=S3=S4
VBias Fig. 330-07
Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4.
C1 = Cgd1+Cbd1+Cbd3+Cgs3+Cgs4, C2 = Cbd2 +Cbd4+Cgd2+CL and C3 = Cgd4
If C3  0, then we can write
gm1  gm3      gds2 + gds4
   2 
Vout(s)  g + gds4
ds2
  V
gm3 + sC1 gs1

(s) - Vgs2   s + 2
(s)   where  2 = C2
If we further assume that gm3/C1 >> (gds2+gds4)/C2 = 2
then the frequency response of the differential amplifier reduces to
Vout(s)  gm1   2 
Vid(s)  gds2  gds4 s  2 
 (A more detailed analysis will be made in Chapter 6)

AN INTUITIVE METHOD OF SMALL SIGNAL ANALYSIS

Simplification of Small Signal Analysis
Small signal analysis is used so often in analog circuit design that it becomes desirable to
find faster ways of performing this important analysis.
Intuitive Analysis (or Schematic Analysis)
Technique:
1.) Identify the transistor(s) that convert the input voltage to current (these transistors are
called transconductance transistors).
2.) Trace the currents to where they flow into an equivalent resistance to ground.
3.) Multiply this resistance by the current to get the voltage at this node to ground.
4.) Repeat this process until the output is reached.
Simple Example: VDD VDD
R1 M2
vo1 gm2vo1 vout
gm1vin
vin M1 R2
Fig. 5.2-10C
vo1 = -(gm1vin) R1  vout = -(gm2vo1)R2 

 vout = (gm1R1gm2R2)vin
Intuitive Analysis of the Current-Mirror Load Differential Amplifier

VDD
M3 M4
gm1vid gm1vid rout
2 2
+
M1 gm1vid gm2vid M2
2 2
+v
id vid- v
out
2- + 2
+ -
M5 v id
VBias
-
Fig. 5.2-11
1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid

2.) i3 = i1 = 0.5gm1vid
3.) i4 = i3 = 0.5gm1vid
1
4.) The resistance at the output node, rout, is rds2||rds4 or gds2 + gds4
gm1vin gm2vin vout gm1
5.)  vout = (0.5gm1vid+0.5gm2vid )rout =g +g  =
ds2 ds4 = gds2+gds4 vin gds2+gds4

Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis

1.) Approximate the output resistance of any cascode circuit as
Rout  (gm2rds2)rds1
where M1 is a transistor cascoded by M2.
2.) If there is a resistance, R, in series with the source of the transconductance transistor,
let the effective transconductance be
gm
gm(eff) = 1+gmR
Proof:
gm2(eff)vin gm2(eff)vin
gm2vgs2 iout
M2 M2 + vgs2 -
vin rds1
vin M1 vin
rds1
VBias Small-signal model
Fig. 5.2-11A
vin
 vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2  vgs2 = 1+g r
m2 ds1
gm2vin
Thus, iout = 1+gm2rds1 = gm2(eff) vin
FURTHER CONSIDERATIONS OF THE DIFFERENTIAL AMPLIFIER

Linearization of the Transconductance
Goal: i iout
out
ISS ISS
Linearization
vin vin
-ISS -ISS
060608-03
Method (degeneration):
VDD VDD
M3 M4 M3 M4
iout iout
M1 M2 M1 M2
 RS RS VDD  VDD
or
vin 2 2 2 vin RS 2
 
M5
VNBias1 M5 VNBias1 M6
060118-10

Linearization with Active Devices

VDD VDD
M3 M4 M3 M4
iout iout
M1 VBias M2 V M1 M2 V
 DD or  DD
vin M6 2 M6 2
vin
 M7
M5x1/2 
VNBias1 M5x1/2 M5
VNBias1 M6
M6 is in deep triode region 060608-05 M6 and M7 are in the triode region
Note that these transconductors on this slide and the last can all be adjusted by changing
the value of ISS.
Slew Rate of the Differential Amplifier

Slew Rate (SR) = Maximum output-voltage rate (either positive or negative)
dvOUT
It is caused by, iOUT = CL dt . When iOUT is a constant, the rate is a constant.
Consider the following current-mirror load, differential amplifiers:
VDD VDD
M5
M3 M4
VBias IDD
iD3 iD4 iOUT - -
vSG1 vSG2
iD1 iD2 + + M1 M2 + +
M1 M2 CL + iD1 i iOUT
+ + D2
vGS1 vGS2
- - iD3 iD4 +
vG1 ISS vG2 vOUT vG1 v
M3 M4 CL vOUT G2
M5
- - - - - -
VBias
Fig. 5.2-11B
Note that slew rate can only occur when the differential input signal is large enough to
cause ISS (IDD) to flow through only one of the differential input transistors.
ISS IDD
SR = CL = CL  If CL = 5pF and ISS = 10μA, the slew rate is SR = 2V/μs.
(For the BJT differential amplifier slewing occurs at ±100mV whereas for the
MOSFET differential amplifier it can be ±2V or more.)
Noise Analysis of the Differential Amplifier

VDD VDD
M5
M5 M5
VBias VBias
en12 en22 eeq2
* M1 M2 * * M1 M2
ito2 vOUT
en32 en42
M3 M4 Vout M3 M4
* *
Fig. 5.2-11C
Solve for the total output-noise current to get,

ito 2 = gm12en12 + g m22en22 + g m32en32 + g m42en42
This output-noise current can be expressed in terms of an equivalent input noise voltage,
eeq2, given as ito2 = gm1 2eeq 2
Equating the above two expressions for the total output-noise current gives,
 g
m3 2 2 
eeq 2 = en1 2 + en22 + gm1 e n3
2+ e
n4 
1/f Noise (en12en2 2and en3 2en4 ):2 Thermal Noise (en12en2 2and en3 2en4 ):2
2BP K’ B  L     W L K'  
 N N   12  16kT    3 1 31/2
eeq(1/f)= fW1L1 1 + K’PBP  L3 eeq(th)= 3[2K' (W/L) I ] 1/2 1 L3W1K'1 
1 11
DIFFERENTIAL AMPLIFIERS WITH DIFFERENTIAL OUTPUT

Current-Source Load Differential Amplifier
VDD
Gives a truly balanced differential amplifier.
M3 M4
X1
X1 X1
M7 I3 I4
Also, the upper input common-mode range is v3 v4
IBias v1 I1 I2 v2
extended.
M1 X1 X1 M2
M6 M5 I5
X1 X2
However, a problem occurs if I1 I3 or if I2  I4.
Fig. 5.2-12
Current Current
I1 I3
I3 I1
0 vDS1 0 vDS1
0 VDS1<VDS (sat) VDD 0 VSD3<VSD(sat) VDD
(a.) I1>I3. (b.) I3>I1. Fig. 5.2-13

A Differential-Output, Differential-Input Amplifier

Probably the best way to solve the current mismatch problem is through the use of
common-mode feedback.
Consider the following solution to the previous problem.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4
mode feed- Self-
back circuit resistances
MC2A of M1-M4
MC1
v1 v2
VCM M1 M2
MC2B
MC5 M5
MB
VSS Fig. 5.2-14
Operation:
• Common mode output voltages are sensed at the gates of MC2A and MC2B and
compared to VCM.
• The current in MC3 provides the negative feedback to drive the common mode output
voltage to the desired level.
• With large values of output voltage, this common mode feedback scheme has flaws.
Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - Continued

The following circuit avoids the large differential output signal swing problems.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4 RCM1
mode feed- Self-
back circuit resistances
RCM2
MC1 MC2 of M1-M4
v1 v2
VCM M1 M2
MC5 M5
MB
VSS Fig. 5.2-145
Note that RCM1 and RCM2 must not load the output of the differential amplifier.

DESIGNING DIFFERENTIAL AMPLIFIERS

Design of a CMOS Differential Amplifier with a Current Mirror Load
Design Considerations: VDD
Constraints Specifications
Power supply Small-signal gain
Technology Frequency response (CL) M3 M4
vout
Temperature ICMR
CL
Slew rate (CL) +
Power dissipation vin M2
M1
Relationships -
Av = gm1Rout I5
-3dB = 1/RoutCL
VBias M5
VIC(max) = VDD - VSG3 + VTN1
VSS
VIC(min)  VSS +VDS5(sat) + VGS1 = VSS ALA20
+VDS5(sat) + VGS2
SR = ISS/CL
Pdiss = (VDD+|VSS|)xAll dc currents flowing from VDD or to VSS
Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued
Max. ICMR Schematic-wise, the design procedure is illustrated as

V shown:
+ DD
VSG4
-
Procedure:
M3 M4 1.) Pick ISS to satisfy the slew rate knowing CL or
vout
the power dissipation
gm1Rout CL
2.) Check to see if Rout will satisfy the frequency
+
vin
M1 M2 response, if not change ISS or modify circuit
- 3.) Design W3/L3 (W4/L4) to satisfy the upper ICMR
Min. ICMR I5 = SR·CL, 4.) Design W1/L1 (W2/L2) to satisfy the gain
I5
+ -3dB, Pdiss
VBias
5.) Design W5/L5 to satisfy the lower ICMR
M5
- 6.) Iterate where necessary
VSS ALA20

Example 5.2-2 - Design of a MOS Differential Amp. with a Current Mirror Load
Design the currents and W/L values of the current mirror load MOS differential amplifier
to satisfy the following specifications: VDD = -VSS = 2.5V, SR  10V/μs (CL=5pF), f-
3dB  100kHz (CL=5pF), a small signal gain of 100V/V, -1.5VICMR2V and Pdiss
 mW. Use the parameters of KN’=110μA/V2, KP’=50μA/V2, VTN=0.7V, VTP=-0.7V,
N=0.04V-1 and P=0.05V-1.
Solution
1.) To meet the slew rate, ISS  50μA. For maximum Pdiss, ISS  200μA.
2

2.) f-3dB of 100kHz implies that Rout  318k Therefore Rout = (N+P)ISS  318k
 ISS  70μA Thus, pick ISS = 100μA
3.) VIC(max) = VDD - VSG3 + VTN1  2V = 2.5 - VSG3 + 0.7
2·50μA
VSG3 = 1.2V = 50μA/V2(W3/L3) + 0.7
W3 W4 2
 L3 = L4 = (0.5)2 = 8
gm1
2·110μA/V2(W1/L1) W1 W1 W2
4.) 100=gm1Rout=gds2+gds4 = (0.04+0.05) 50μA = 23.31 L1  L = L =18.4
1 2
Example 5.2-2 - Continued

2·50μA
5.) VIC(min)  VSS +VDS5(sat)+VGS1  -1.5 = -2.5+VDS5(sat)+ 110μA/V2(18.4) + 0.7
W5 2ISS
VDS5(sat) = 0.3 - 0.222 = 0.0777  L5 KN’VDS5(sat)2 = 150.6
=
We probably should increase W1/L1 to reduce VGS1. If we choose W1/L1 = 40, then
VDS5(sat) = 0.149V and W5/L5 = 41. (Larger than specified gain should be okay.)

SECTION 5.3 – CASCODE (COMMON GATE) AMPLIFIERS

VOLTAGE-DRIVEN COMMON GATE AMPLIFIER
Common Gate Amplifier VDD VDD
Circuit: VPBias1
R L M3
vOUT vOUT
VNBias2 VNBias2
M2
VNBias1
vIN IBias vIN M1
060609-01
Large Signal Characteristics: vOUT

VOUT(max) = VDD – VDS3(sat) VDD
VON3
VOUT(min) = VDS1(sat) + VDS2(sat)
Note VDS1(sat) = VON1
VON2
VON1+VON2
VT2
vIN
VNBias2
VON1
060609-02
Small Signal Performance of the Common Gate Amplifier

Small signal model:
rds2 rds2
Rin Rout Rin Rout
i1
 
vin rds1 vgs2 gm2vgs2 vout vin rds1 vs2 gm2vs2 vout
rds3 rds3
 
060609-03
 rds2  gm2rds2rds3 vout gm2rds2rds3

vout = gm2vs2r +r rds3 =  r +r v
ds2 ds3  ds2 ds3  in * Av = v = + rds2+rds3
in
Rin = Rin’||rds1, Rin’ is found as follows
vs2 = (i1 - gm2vs2)rds2 + i1rds3 = i1(rds2 + rds3) - gm2 rds2vs2
vs2 rds2 + rds3 rds2 + rds3
Rin' = i1 = 1 + gm2rds2 * Rin = rds1||1 + gm2rds2
Rout = rds2||rds3

Frequency Response of the Common Gate Amplifier

Circuit:
VDD
VPBias1 M3 rds2
Cgd3 Cbd3 vOUT
Cgd2 Cbd2
VNBias2 CL 
M2 rds1 Vs2 gm2Vs2
Vin Vout
rds3 Cout
VNBias1 
vIN M1
060609-04
The frequency response can be found by replacing rds3 in the previous slide with,
rds3
rds3* srds3Cout + 1 where Cout = Cgd2 + Cgd3 + Cbd2 + Cbd3 + CL
Vout gm2rds2rds31  gm2rds2rds3 1 
Av(s) = Vin = + rds2+rds3 rds2rds3Cout  = + rds2+rds3 
 s 
s   
 rds2+rds3 + 1  1 - p1
-1
where p1 = rds2rds3 Cout -3dB = |p1|
rds2+rds3
VOLTAGE-DRIVEN CASCODE AMPLIFIER

Cascode Amplifier
VDD
VPBias1
M3
vOUT
VNBias2
M2
M1
vIN
060609-05
Advantages of the cascode amplifier:

• Increases the output resistance and gain (if M3 is cascaded also)
• Eliminates the Miller effect when the input source resistance is large

Large-Signal Characteristics of the Cascode Amplifier

vIN=5.0V vIN=4.5V 5V
0.5 vIN=4.0V M3 W3 2m
vIN=3.5V =
L3 1m
0.4 vIN=3.0V
2.3V ID
vIN=2.5V M2 +
0.3
ID (mA)
K GF
W2 = 2m
JIH E L2 1m
0.2 vIN=2.0V 3.4V
M3 vOUT
M1
0.1 D W1 = 2m
vIN=1.5V + L1 1m
C vIN
A,B vIN=1.0V --
0.00
1 2 3 4 5 5
vOUT ABC
D
4
E
M3 active
3 M3 saturated M2 saturated
vOUT
M2 active
2
F
GH
1
M1 sat- M1 I JK
urated active
0
Fig. 5.3-2 0 1 2v
IN
3 4 5
M1 sat. when VGG2-VGS2  VGS1-VT  vIN  0.5(VGG2+VTN) where VGS1=VGS2
M2 sat. when VDS2VGS2-VTN  vOUT-VDS1VGG2-VDS1-VTN  vOUT VGG2-VTN
M3 is saturated when VDD-vOUT  VDD - VGG3 - |VTP|  vOUT  VGG3 + |VTP|
Large-Signal Voltage Swing Limits of the Cascode Amplifier

vOUT(max) = VDD
Referencing all potentials to the negative power supply (ground in this case), we may
express the current through each of the devices, M1 through M3, as
 2 
 vDS1
iD1 = 1(VDD - VT1)vDS1 - 2 = 1(VDD - VT1)vDS1
 (vOUT - vDS1 )2

iD2 = 2 (V GG2 - vDS1 - VT2 )(vOUT - vDS1 ) - 2


 2(VGG2 - vDS1 - VT2)(vOUT - vDS1)

and
3
iD3  (VDD  VGG3  VT3)2
2
where we have also assumed that both vDS1 and vOUT are small, and vIN = VDD.
Solving for vOUT by realizing that iD1 = iD2 = iD3 and 1 = 2 we get,
 
3 1

1 

vOUT(min)  22(V DD  VGG3  VT3) VGG2  VT2 VDD  VT1
2 

Example 5.3-1 - Calculation of the Min. Output Voltage for the Cascode Amplifier
(a.) Assume the values and parameters used for the cascode configuration plotted in the
previous slide on the voltage transfer function and calculate the value of vOUT(min).
(b.) Find the value of vOUT(max) and vOUT(min) where all transistors are in saturation.
Solution
(a.) Using the previous result gives,
vOUT(min) = 0.50 volts.
We note that simulation gives a value of about 0.75 volts. If we include the influence of
the channel modulation on M3 in the previous derivation, the calculated value is 0.62
volts which is closer. The difference is attributable to the assumption that both vDS1 and
vOUT are small.
(b.) The largest output voltage for which all transistors of the cascode amplifier are in
saturation is given as
vOUT(max) = VDD - VSD3(sat)
and the corresponding minimum output voltage is
vOUT(min) = VDS1(sat) + VDS2(sat) .
For the cascode amplifier of Fig. 5.3-2, these limits are 3.0V and 2.7V.
Consequently, the range over which all transistors are saturated is quite small for a 5V
power supply.
Small-Signal Midband Performance of the Cascode Amplifier

Small-signal model:
gm2vgs2= -gm2v1
G1 D1=S2 D2=D3
+ + rds2 +
vin = v1
vgs1 gm1vgs1 rds3 v out
rds1
- - S1=G2=G3 -
Small-signal model of cascode amplifier neglecting the bulk effect on M2.
C1 rds2
G1 D1=S2 D2=D3
+ + +
vin 1
gm1vin rds1 gm2 C2 v1 gm2v1 rds3 C3 vout
- - -
Simplified equivalent model of the above circuit. Fig. 5.3-3
Using nodal analysis, we can write,

[gds1  gds2  gm2]v1  gds2vout  gm1vin
[gds2  gm2]v1  (gds2  gds3)vout  0
Solving for vout/vin yields
vout  gm1(gds2  gm2) gm1 2K'1W1

vin gds1gds2  gds1gds3  gds2gds3  gds3gm2  gds3   L1ID23
The small-signal output resistance is,
rout  [rds1  rds2  gm2rds1rds2]rds3  rds3

Small-Signal Analysis of the Cascode Amplifier - Continued

It is of interest to examine the voltage gain of v1/vin. From the previous nodal equations,
v1 gm1(gds2gds3) g
 ds2
g ds3 
gm1 2gm1 W1L2
     2
vin gds1gds2gds1gds3gds2gds3gds3gm2  gds3   gm2  gm2
=  
L1W2
If the W/L ratios of M1 and M2 are equal and gds2  gds3, then v1/vin is approximately 2.
Why is this gain -2 instead of -1? gm2vs2
Consider the small-signal model looking into the Rs2 iA
i1 iB
source of M2:
The voltage loop is written as, vs2 rds3
rds2
vs2 = (i1 - gm2vs2)rds2 + i1rds3 Fig. 5.3-4
= i1(rds2 + rds3) - gm2 rds2vs2 Solving this equation for the ratio of vs2 to i1
gives
vs2 rds2 + rds3
Rs2 = i = 1 + gm2rds2
1
We see that Rs2 equals 2/gm2 if rds2  rds3. Thus, if gm1  gm2, the voltage gain v1/vin  -2.
Note that:
rds3 =0 that Rs21/gm2 or rds3=rds2 that Rs22/gm2 or rds3rds2gmrds that Rs2rds!!!
Principle: The small-signal resistance looking into the source of a MOSFET depends on
the resistance connected from the drain of the MOSFET to ac ground.
Frequency Response of the Cascode Amplifier

Small-signal model (RS = 0): C1 rds2
G1 D1=S2 D2=D3
where + + +
C1 = Cgd1, vin
gm1vin 1
C2 v1 gm2v1 rds3 C3 vout
rds1 gm2
C2 = Cbd1+Cbs2+Cgs2, and - - -
Fig. 5.3-4A
C3 = Cbd2+Cbd3+Cgd2+Cgd3+CL
The nodal equations now become:
(gm2  gds1  gds2  sC1  sC2)v1  gds2vout  (gm1  sC1)vin
and (gds2  gm2)v1  (gds2  gds3  sC3)vout  0
Solving for Vout(s)/Vin(s) gives,
Vout(s)   1  
(gm1  sC1)(gds2  gm2 ) 

Vin(s) 1  as  bs2  g ds1gds2  gds3 (gm2  gds1  gds2 )

where
C3(gds1  gds2  gm2)  C2(gds2  gds3)  C1(gds2  gds3)
a gds1gds2  gds3(gm2  gds1  gds2)
and
C3(C1  C2)
b  gds1gds2  gds3(gm2  gds1  gds2)

A Simplified Method of Finding an Algebraic Expression for the Two Poles

Assume that a general second-order polynomial can be written as:

 s  s  1
 1  s2
P(s)  1  as  bs  1  p 1
2 
  1 p 2
    1  s p1  p2 p1p2

Now if p2 >> p1, then P(s) can be simplified as

s s2
P(s) = 1  p1  p1p2
Therefore we may write p1 and p2 in terms of a and b as
1 a
p1  a and p2  b
Applying this to the previous problem gives,
[gds1gds2  gds3(gm2  gds1  gds2)] gds3
p1  C3(gds1  gds2  gm2)  C2(gds2  gds3)  C1(gds2  gds3)  C
3
The nondominant root p2 is given as
[C3(gds1  gds2  gm2)  C2(gds2  gds3)  C1(gds2  gds3)] gm2
p2  C3(C1  C2)  C1  C2
Assuming C1, C2, and C3 are the same order of magnitude, and gm2 is greater than gds3,
then p1 is smaller than p2. Therefore the approximation of p2 >> p1 is valid.
Note that there is a right-half plane zero at z1 = gm1/C1.
NON-VOLTAGE DRIVEN CASCODE AMPLIFIER – THE MILLER EFFECT

Miller Effect
Consider the following inverting amplifier:
CM
I1
-Av
 
Solve for the input impedance: V1 V2 = -AvV1
V1  
Zin(s) = I1 060610-03
I1 = sCM(V1 – V2) = sCM(V1 + AvV1) = sCM(1 + Av)V1

Therefore,
V1 V1 1 1
Zin(s) = I1 = sCM(1 + Av)V1 = sCM(1 + Av) = sCeq
The Miller effect can take Cgd = 5fF and make it look like a 0.5pF capacitor in parallel
with the input of the inverting amplifier (Av = -100).
If the source resistance is large, this creates a dominant pole at the input.

Simple Inverting Amplifier Driven with a High Source Resistance

Examine the frequency VDD C2
response of a current-source load VGG2

M2
Vin + +
vout V1 C3 V
inverter driven from a high Rs R s C 1
g V
R 3 out
- m1 1 -
resistance source: M1
vin R C1  Cgs1 C3 = Cbd1 + Cbd2 + Cgd2
Assuming the input is Iin, the Rs s
C2 = Cgd1 R3 = rds1||rds2 Fig. 5.3-5
nodal equations are,
[G1  s(C1  C2)]V1  sC2Vout  Iin and (gm1sC2)V1[G3s(C2C3)]Vout  0
where
G1 = Gs (=1/Rs), G3 = gds1  gds2, C1 = Cgs1, C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2.
Solving for Vout(s)/Vin(s) gives
Vout(s) (sC2gm1)G1 or,
Vin(s)  G1G3s[G3(C1C2)G1(C2C3)gm1C2](C1C2C1C3C2C3)s2
V (s) g  out m12
[1s(C /g )] m1
 
Vin(s) G3  1[R1(C1C2)R3(C2C3)gm1R1R3C2]s(C1C2C1C3C2C3)R1R23s

Assuming that the poles are split allows the use of the previous technique to get,
1 1 gm1C2
p1  R1(C1C2)R3(C2C3)gm1R1R3C2  gm1R1R3C2 and p2  C1C2C1C3C2C3
The Miller effect has caused the input pole, 1/R1C1, to be decreased by a value of gm1R3.
How Does the Cascode Amplifier Solve the Miller Effect?

Cascode amplifier:
VDD
VPBias1 M3

VNBias2 M2
Cgd1
Rs2
RS  vOUT
+ v1
vS vI N M1 
- 
060610-02
The Miller effect causes Cgs1 to be increased by the value of 1 + (v1/vin) and appear in
parallel with the gate-source of M1 causing a dominant pole to occur.
The cascode amplifier eliminates this problem by keeping the value of v1/vin small by
making the value of Rs2 approximately 2/gm2.

Comparison of the Inverting and Cascode Non-Voltage Driven Amplifiers

The dominant pole of the inverting amplifier with a large source resistance was found to
be
1
p1(inverter)  R1(C1C2)R3(C2C3)gm1R1R3C2
Now if a cascode amplifier is used, R3, can be approximated as 2/gm of the cascoding
transistor (assuming the drain sees an rds to ac ground).
1
 p1(cascode) = 2  
 2 
 
R1(C1C2) g (C2C3)gm1R1 gmC2
 m
1 1
=  
 R1(C 13C 2)
2
R1(C1C2) gm(C2C3)2R1C2


Thus we see that p1(cascode) >> p1(inverter).
High Gain and High Output Resistance Cascode Amplifier

V
If the load of the cascode M4 DD
VPBias1 D2=D3
amplifier is a cascode +
M3
current source, then both VPBias2
gm2v1 gmbs2v1 rds2 gm3v4 gmbs3v4 rds3
high output resistance vout
M2
and high voltage gain is VNBias2 Rout G1 D1=S2 D4=S3 vout
+ + +
achieved. vin M1
vin v1 rds1 v4 rds4
gm1vin
- - - -
G2=G3=G4=S1=S4 060609-07
The output resistance is,

-1.5
ID
rout  [gm2rds1rds2][gm3rds3rds4] = 1  2 3  4

2K'2(W/L)2 2K'3(W/L)3
Knowing rout, the gain is simply
-1
2K'1(W/L)1ID
Av  gm1rout  gm1{[gm2rds1rds2][gm3rds3rds4]}  1
2 3  4

2K'2(W/L)2 2K'3(W/L)3

Example 5.3-2 - Comparison of the Cascode Amplifier Performance

Calculate the small-signal voltage gain, output resistance, the dominant pole, and the
nondominant pole for the low-gain, cascode amplifier and the high-gain, cascode
amplifier. Assume that ID  200 microamperes, that all W/L ratios are 2m/1μm, and
that the parameters of Table 3.1-2 are valid. The capacitors are assumed to be: Cgd  3.5
fF, Cgs  30 fF, Cbsn  Cbdn  24 fF, Cbsp  Cbdp  12 fF, and CL  1 pF.
Solution
The low-gain, cascode amplifier has the following small-signal performance:
Av = 37.1V/V
Rout = 125k
p1  -gds3/C3  1.22 MHz
p2  gm2/(C1+C2)  605 MHz.
The high-gain, cascode amplifier has the following small-signal performance:
Av = 414V/V
Rout = 1.40 M
p1  1/RoutC3  108 kHz
p2  gm2/(C1+C2)  579 MHz
(Note at this frequency, the drain of M2 is shorted to ground by the load capacitance, CL)
Designing Cascode Amplifiers

Pertinent design equations for the simple cascode amplifier.
vOUT(max) = VDD - VSD3(sat)

2I
VDD =VDD -
K PW 3 KP(W3 /L3)
I= 2
2L3 (VDD - VGG3-|VTP|)
M3
VGG3 vOUT(min) =VDS1(sat) + VDS2(sat)
+ = 2I 2I
+
K N(W/L1 ) 1 K N /L(W
)2 2
M2
VGG2 vOUT
I
I = Pdiss = (SR)·Cout
M1 VDD
VGG2 = VDS1(sat) + VGS2 +
vI N
- -
g 2KN(W1/L1)
|Av| = gm1 =
Fig. 5.3-7
ds3  P2 I

Example 5.3-3 - Design of a Cascode Amplifier

The specs for a cascode amplifier are Av = -50V/V, vOUT(max) = 4V, vOUT(min) = 1.5V,
VDD=5V, and Pdiss=1mW. The slew rate with a 10pF load should be 10V/μs or greater.
Solution
The slew rate requires a current greater than 100μA while the power dissipation
requires a current less than 200μA. Compromise with 150μA. Beginning with M3,
W3 2I 2·150
L3 KP[VDD-vOUT(max)] 50(1)2 = 6
= 2 =
2I 2·150
From this find VGG3: VGG3 = VDD - |VTP| - KP(W3/L3) = 5 - 1 - 50·6 = 3V
W1 (Av)2I (50·0.05)2(150)
Next, L1 = 2KN = 2·110 = 2.73
To design W2/L2, we will first calculate VDS1(sat) and use the vOUT(min) specification to
2I 2·150
define VDS2(sat). VDS1(sat) = KN(W1/L1) = 110·4.26 = 0.8V
Subtracting this value from 1.5V gives VDS2(sat) = 0.7V.
W2 2I 2·150
 L2 = KNVDS2(sat)2 = 110·0.72 = 5.57
2I
Finally, VGG2 = VDS1(sat) + KN(W2/L2) + VTN = 0.8V+ 0.7V + 0.7V = 2.2V
SECTION 5.4 – CURRENT AMPLIFIERS

What is a Current Amplifier?
• An amplifier that has a defined output-input current relationship
• Low input resistance
• High output resistance
Application of current amplifiers:
ii
ii io io
Ai iS RS ii Ai
iS RS Current RL Current RL
Amplifier Amplifier
Single-ended input. Differential input. Fig. 5.4-1
RS >> Rin and Rout >> RL
Advantages of current amplifiers:

• Currents are not restricted by the power supply voltages so that wider dynamic
ranges are possible with lower power supply voltages.
• -3dB bandwidth of a current amplifier using negative feedback is independent of the
closed loop gain.

Frequency Response of a Current Amplifier with Current Feedback

Consider the following current amplifier with resistive i2 R2
io
negative feedback applied. R1 i1 Ai vout
vin
Assuming that the small-signal resistance looking into Fig. 5.4-2
the current amplifier is much less than R1 or R2,
 
vin
 
io= A (i
i 1-i2) = A i R 1 - io


Solving for io gives


 A i v in R2  A i 
io= 1+A R1  vout = R2i o= R 1+A  vin
i 1 i
Ao
If Ai(s) = s , then
A + 1
vout R2  1  R2 Ao  R 2 Ao   1 
  =      
vin = R1  1

R1s = R1 1+ Ao  
s 
1+ Ai(s) A +(1+Ao ) A(1+Ao) +1
 -3dB = A(1+Ao)
Bandwidth Advantage of a Current Feedback Amplifier

The unity-gainbandwidth is,
R2Ao R2 R2
GB = |Av(0)| -3dB = R1(1+Ao) · A(1+Ao) = R1 Ao·A = R1 GBi
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Magnitude dB
Voltage Amplifier, R 2
R1 > K
R2 A o
dB
R1 1+Ao Voltage Amplifier, R2 = K >1
A R1
K o dB
1+Ao Current Amplifier
Ao dB
(1+Ao)A
0dB log10()
A GBi GB1 GB2
Fig. 7.2-10
Note that GB2 > GB1 > GBi
The above illustration assumes that the GB of the voltage amplifier realizing the voltage
buffer is greater than the GB achieved from the above method.
Current Amplifier using the Simple Current Mirror

VDD VDD
I1 I2 iout
iin iin iout
+ C2
R RL
M1 M2 vin
rds1 gm2vin rds2 0
gm1vin C1 C3
-
Fig. 5.4-3
Current Amplifier
1 1 W2/L2
Rin = g Rout =  I and Ai = W1/L1 .
m1 o
Frequency response:
-(gm1+gds1) -(gm1+gds1) -gm1
p1 = C1+C2 = Cbd1 +Cgs1+C +C
gs2 gd2
= Cbd1 +Cgs1+C +C
gs2 gd2
Note that the bandwidth can be almost doubled by including the resistor, R.
(R removes Cgs1 from p1)
Example 5.4-1- Performance of a Simple Current Mirror as a Current Amplifier

Find the small-signal current gain, Ai, the input resistance, Rin, the output resistance,
Rout, and the -3dB frequency in Hertz for the current amplifier of Fig. 5.4-3(a) if 10I1 = I2
= 100μA and W2/L2 = 10W1/L1 = 10μm/1μm. Assume that Cbd1 = 10fF, Cgs1 = Cgs2 =
100fF, and Cgs2 = 50fF.
Solution
Ignoring channel modulation and mismatch effects, the small-signal current gain,
W2/L2
Ai = W1/L1  10A/A.
The small-signal input resistance, Rin, is approximately 1/gm1 and is
1 1
Rin  2K (1/1)10μA = 46.9μS = 21.3k
N
The small-signal output resistance is equal to
1
Rout = NI2 = 250k.
The -3dB frequency is
46.9μS
-3dB = 260fF = 180.4x106 radians/sec.  f-3dB = 28.7 MHz

Wide-Swing, Cascode Current Mirror Implementation of a Current Amplifier
VDD VDD
IIN IOUT
iin iout
 M3 
VNBias2 M4
vIN vOUT
M1 M2
 
060610-01
1 W2/L2
Rin  gm1, Rout  rds2gm4rds4, and Ai = W1/L1
Example 5.4 -2 - Current Amplifier Implemented by the Wide-Swing, Cascode

Current Mirror
Assume that IIN and IOUT of the wide-swing cascode current mirror are 100μA. Find
the value of Rin, Rout, and Ai if the W/L ratios of all transistors are 182μm/1μm.
Solution
The input resistance requires gm1 which is 2·110·182·100 = 2mS
 Rin  500
From our knowledge of the cascode configuration, the small signal output resistance
should be
Rout  gm4rds4rds2 = (2001μS)(250k)(250k) = 125M
Because VDS1 = VDS2, the small-signal current gain is
W2/L2
Ai = W1/L1 = 1
Simulation results using the level 1 model for this example give
Rin= 497, Rout = 164.7M and Ai = 1.000 A/A.
The value of VON for all transistors is
2·100μA
VON = 110μA/V2·182 = 0.1V

Low-Input Resistance Current Amplifier

To decrease Rin below 1/gm VDD VDD
requires the use of negative, iin I1 I2 iout

iin i=0
shunt feedback. Consider
M3 gm3vgs3
the following example. + - +
M1 M2 vin vgs3 vgs1
rds3
I3 VGG3 - gm1vgs1 rds1 + -
Fig. 5.4-5
Current Amplifier
Feedback concept:
Input resistance without feedback  rds1.
g m1 

g m3 

Loop gain  gds1gds3 assuming that the resistances of I1 and I3 are very large.
 

Rin(no fb.) rds1 1

 Rin = 1 + Loop gain  gm1rds1gm3rds3 = gm1gm3rds3
Small signal analysis:
iin = gm1vgs1 - gds1vgs3
and vgs3 = -vin vgs1 = vin - (gm3 vgs3rds3) = vin(1+gm3rds3)
1
 iin = gm1(1+gm3rds3)vin + gds1vin  gm1gm3rds3vin  Rin = gm1gm3rds3
Differential-Input, Current Amplifiers

Definitions for the differential-mode, iID, and common-mode, iIC, input currents of the
differential-input current amplifier.
i1
iO
iIC iID
i2
2
iIC
2
Fig. 5.4-6
 
i +i
 1 
2
iO = AIDiID ± AICi IC= A (iID-1 i ) ±2 A  
IC 2 
Implementations:
VDD
VDD VDD VDD M3 M4
iO
I 2I I
i1 iO
M1 M2
i2 i2 i1 i2
VGG1
i1-i2
M1 M2 M3 M4
M5 M6
VGG2
Fig. 5.4-7
Summary
• Current amplifiers have a low input resistance, high output resistance, and a defined
output-input current relationship
• Input resistances less than 1/gm require feedback
However, all feedback loops have internal poles that cause the benefits of negative
feedback to vanish at high frequencies.
In addition, these feedback loops can have a slow time constant from a pole-zero
pair.
• Voltage amplifiers using a current amplifier have high values of gain-bandwidth
• Current amplifiers are useful at low power supplies and for switched current
applications
SECTION 5.5 - OUTPUT AMPLIFIERS

INTRODUCTION
General Considerations of Output Amplifiers
VDD
Requirements:
1.) Provide sufficient output power in the form of f1(vIN) i1 i
OUT
vIN
voltage or current. +
2.) Avoid signal distortion. f2(vIN) i2 RL vOUT
Buffer -
3.) Be efficient Class A VSS
4.) Provide protection from abnormal conditions i1
Current
(short circuit, over temperature, etc.)

Types of Output Amplifiers: t
i2=I
Q iOUT
1.) Class A amplifiers Class AB
i1
2.) Source followers iOUT
Current
t
3.) Push-pull amplifiers i2
Class B
4.) Substrate BJT amplifiers i1
iOUT
Current
5.) Amplifiers using negative t

shunt feedback i2
Fig. 5.5-005
CLASS A AMPLIFIERS
Current source load inverter
VDD iD
A Class A circuit has VDD+|VSS|
RL
current flow in the MOSFETs M2
during the entire period of a VGG2 iOUT RL dominates
IQ vOUT
sinusoidal signal. IQ as the load line
Characteristics of Class A iD1
amplifiers: vIN M1CL RL vOUT
IQRL IQRL
• Unsymmetrical sinking and VSS VDD
sourcing VSS Fig. 5.5-1
• Linear
• Poor efficiency
vOUT(peak)2 vOUT(peak)2
 
vOUT(peak)2
PRL 2RL 2RL
Efficiency = PSupply = (VDD-VSS)IQ = (V
 DD-VSS)   VDD-V SS 
 =
(VDD -VSS) 2R 
L 
Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
Optimum Value of Load Resistor

Depending on the value of RL, the signal swing can be symmetrical or asymmetrical.
(This ignores the limitations of the transistor.)
iD1
Smaller RL
VDD+|VSS| Minimum RL for
RL maximum swing
IQ Larger RL
0 vDS1
IQRL IQRL
VSS 0 VDD Fig. 040-03

Specifying the Performance of a Class A Amplifier

Output resistance:
1 1
rout = gds1+ gds2 = (1+2)ID
Current:
• Maximum sinking current is,
- K'1W1
IOUT= 2L (VDD -VSS - VT1)2 - IQ
1
• Maximum sourcing current is,
+ K'2W2 vOUT Imax due to RL
IOUT = 2L (VDD - VGG2 - |VT2|)2  IQ
2
Requirements:
• Want rout << RL Imax due to CL
t
• |IOUT| > CL·SR
vOUT(peak)
• |IOUT| > RL Imax due to RL 070118-01
The maximum current is determined by both the current
required to provide the necessary slew rate (CL) and to provide a voltage across the load
resistor (RL).
Small-Signal Performance of the Class A Amplifier

Although we have considered the small-signal performance of the Class A amplifier as
the current source load inverter, let us include the influence of the load.
The modified small-signal model:
C1
+ +
vin rds1 rds2 RL C2 vout
gm1vin
- -
Fig. 5.5-2
The small-signal voltage gain is:
vout -gm1
vin = gds1+gds2+GL
The small-signal frequency response includes:
A zero at
gm1
z = Cgd1
and a pole at
-(gds1+gds2+GL)
p = Cgd1+Cgd2+Cbd1+Cbd2+CL

Example 5.5-1 - Design of a Simple Class-A Output Stage

Use Table 3.1-2 to design the W/L ratios of M1 and M2 so that a voltage swing of 2V
and a slew rate of 1 V/s is achieved if RL  20 k and CL  1000 pF. Assume VDD =
|VSS|  3V and VGG2  0V. Let L = 2 m and assume that Cgd1 = 100fF.
Solution
Let us first consider the effects of RL and CL.
iOUT(peak) = ±2V/20k = ±100μA and CL·SR = 10-9·106 = 1000μA
Since the slew rate current is so much larger than the current needed to meet the voltage
specification across RL, we can safely assume that all of the current supplied by the
inverter is available to charge CL.
Using a value of ±1 mA,
W1 2(IOUT-+IQ) 4000 3μm
L1 = KN’(VDD+|VSS| -VTN)2 = 110·(5.3)2 = 2μm
and
W2 2IOUT+ 2000 15μm
L2 = KP’(VDD-VGG2-|VTP|)2 = 50·(2.3)2 = 2μm
The small-signal performance is Av = -8.21 V/V (includes RL = 20k) and rout = 50k
The roots are, zero = gm1/Cgd1  .59GHz and pole = 1/[(RL||rout)CL)]  -11.14kHz
Broadband Harmonic Distortion

The linearity of an amplifier can be characterized by its influence on a pure sinusoidal
input signal.
Assume the input is,
Vin()  Vp sin(t)
The output of an amplifier with distortion will be
Vout()  a1Vp sin (t)  a2Vp sin (2t) ... anVp sin(nt)
Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of the
magnitude of the ith harmonic to the magnitude of the fundamental.
For example, second-harmonic distortion would be given as
a2
HD2  a1
Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of
all of the second and higher harmonics to the magnitude of the first or fundamental
2 2 2
[a2 a3 ... an1/2
]
Thus, THD can be expressed as THD  a1
The distortion of the class A amplifier is good for small signals and becomes poor at
maximum output swings because of the nonlinearity of the voltage transfer curve for
large-signal swing
Class-A Source Follower

N-Channel Source Follower Voltage transfer curve:
with current sink bias: vOUT
VDD
VDD VDD VDD-VON1 Triode
VDD-VGS1
vIN M1
IQ VGS1
iOUT |VSS|+VON2+VGS1
VSS vIN
vOUT VDD-V ON1+VGS1
M3 M2 RL
IQRL<|VSS|+VON2
VSS VSS Fig. 040-01 Triode |VSS|+VON2
|VSS| Fig. 040-02
Maximum output voltage swings:
vOUT(min)  VSS - VON2 (if RL is large) or vOUT(min)  -IQRL (if RL is small)
vOUT(max) = VDD - VON1 (if vIN > VDD) or vOUT(max)  VDD - VGS1
Output Voltage Swing of the Follower

The previous results do not include the bulk effect on VT1 of VGS1.
Therefore,
VT1 = VT01 + [ 2|F| -vBS- 2|F|] = VT01+ vSB = VT01+1 vOUT(max)-VSS
 vOUT(max)-VSS = VDD-VSS-VON1-VT1 = VDD-VSS-VON1-VT01-1 vOUT(max)-VSS

Define vOUT(max)-VSS = vOUT’(max)
which gives the quadratic,
vOUT’(max)+1 vOUT’(max)-(VDD-VSS -VON1-VT01)=0
Solving the quadratic gives,
12 1 12+ 4(VDD-VSS-VON1-VT01)
vOUT’(max)  4 - 2 12+4(VDD-VSS-VON1-VT01) + 4
If VDD = 2.5V, N = 0.4V1/2, VTN1= 0.7V, and VON1 = 0.2V, then vOUT’(max) = 3.661V
and
vOUT(max) = 3.661-2.5 = 0.8661V

Maximum Sourcing and Sinking Currents for the Source Follower

Maximum Sourcing Current (into a short circuit): VDD VDD
We assume that the transistors are in saturation and
vIN M1
VDD = -VSS = 2.5V , thus IQ
iOUT
VSS
K’1W1 vOUT
IOUT(sourcing) = 2L1 [VDD  vOUT VT1]2-IQ
M3 M2 RL
where vIN is assumed to be equal to VDD. VSS VSS Fig. 040-01

If W1/L1 =10 and if vOUT = 0V, then
VT1 = 1.08V  IOUT equal to 1.11 mA.
However, as vOUT increases above 0V, the current rapidly decreases.
Maximum Sinking Current:
For the current sink load, the sinking current is whatever the sink is biased to provide.
IOUT(sinking) = IQ
Efficiency of the Source Follower

Assume that the source follower vIN iD
input can swing to power supply. VSS -2VT -VT 0 VT 2VT 3VT 4VT
I R = VSS
VDD Q L
Plotting

iD= 2(v IN - vOUT - VT)2
vOUT IQRL IQ
and vOUT
iD = I Q - R L
VSS VSS-VT -3VT -2VT -VT VT 2VT 3VT VDD-VT VDD
Efficiency = Fig. 040-035
vOUT(peak)2 vOUT(peak)2
vOUT(peak)2

PRL 2RL 2RL
PSupply (VDD-VSS)IQ =
= (V

=
DD-VSS)   VDD-V SS 

(VDD -VSS) 2R 

L
Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
Comments:
• Maximum efficiency occurs for the minimum value of RL which gives max. swing.
• Other values of RL result in less efficiency (and smaller signal swings before clipping)
• We have ignored the fact that the dynamic Q point cannot travel along the full length of
the load line because of minimum and maximum voltage limits.
Small Signal Performance of the Source Follower

v
Small-signal model: + gs1 -
+ C1 +
gm1vgs1 gmbs1vbs1
- -
v
+ gs1 -
+ C1 +
gm1vin gm1vout gmbs1vout
- -
Fig. 040-04
Vout  gm1 gm1 gm1RL

  
Vin gds1  gds2  gm1 + gmbs1+GL gm1 + gmbs1+GL 1 +gm1RL
If VDD = -VSS = 2.5V, Vout = 0V, W1/L1 = 10m/1 m, W2/L2 = 1m/1 m,
and ID = 500 A, then
For the current sink load follower (RL = ):
Vout Vout
Vin = 0.869V/V, if the bulk effect were ignored, then Vin = 0.963V/V
For a finite load, RL = 1000
Vout
Vin = 0.512V/V
Small Signal Performance of the Source Follower - Continued

The output resistance is:
1
Rout = gm1 + gmbs1 + gds1 + gds2
For the current sink load follower:
Rout = 830
The frequency response of the source follower:
Vout(s)  (gm1  sC1)
Vin(s)  gds1  gds2  gm1 + gmbs1 + GL  s(C1  C2)
where
C1 = capacitances connected between the input and output  CGS1
C2 = Cbs1 +Cbd2 +Cgd2(or Cgs2) + CL
gm1 gm1+GL
z = - C1 p  - C1+C2
and
The presence of a LHP zero leads to the possibility that in most cases the pole and zero
will provide some degree of cancellation leading to a broadband response.

PUSH-PULL AMPLIFIERS
Push-Pull Source Follower
VDD VDD
Can both sink and source VDD
M6
current and provide a slightly M1 VGG
M5 M1 VSS
lower output resistance. VBias VSS
iOUT VSS iOUT
vIN vOUT
VBias vOUT
RL VDD M4 M2 VDD RL
Efficiency: M2 VDD
Depends on how the vIN M3
transistors are biased. VSS
VSS VSS Fig. 060-01
• Class B - one transistor has
current flow for only 180° of the sinusoid (half period)
vOUT(peak)2
PRL 2RL  vOUT(peak)
 Efficiency = P = 1  2v 
OUT(peak)
= 2 VDD -VSS
VDD  

(VDD -VSS) 2
   
RL
Maximum efficiency occurs when vOUT(peak) =VDD and is 78.5%
• Class AB - each transistor has current flow for more than 180° of the sinusoid.
Maximum efficiency is between 25% and 78.5%
Illustration of Class B and Class AB Push-Pull, Source Follower

Output current and voltage characteristics of the push-pull, source follower (RL = 1k):
2V 1mA 2V 1mA
vG1 vG1 iD1
iD1
1V 1V
0V 0mA 0V 0mA
vout vG2 vout vG2
-1V -1V
iD2 iD2
-2V -1mA -2V -1mA
-2 -1 0 1 2 -2 -1 0 1 2
Vin(V) Vin(V)
Class B, push-pull, source follower Class AB, push-pull, source follower Fig. 060-02
Comments:
• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
• Note that there is significant distortion at vIN =0V for the Class B push-pull follower

Small-Signal Performance of the Push-Pull Follower

Model:
v
+ gs1 -
+ C1 +
gm1vgs1 gmbs1vbs1 gm2vgs2 gmbs2vbs2 -
-
v
+ gs1 -
+ C1 +
vin 1 vout
gm2 RL C2
gm1vin gm1vout gmbs1vout rds1 gm2vin gm2vout gmbs2vout rds2 -
-
Fig. 060-03
vout gm1 + gm2

=
vin gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL
1
Rout = gds1+gds2+gm1+gmbs1+gm2+gmbs2 (does not include RL)
If VDD = -VSS = 2.5V, Vout = 0V, ID1 = ID2 = 500μA, and W/L = 20μm/2μm, Av = 0.787
(RL= and Rout = 448.
A zero and pole are located at
-(gm1+gm2) -(gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL)
z= C1 p = C1+C2 .
These roots will be high-frequency because the associated resistances are small.
Push-Pull, Common Source Amplifiers

Similar to the class A but can operate as class B providing higher efficiency.
VDD
M2
VTR2 iOUT
vIN vOUT
VTR1
M1CL RL
VSS Fig. 060-04

Comments:
• The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2.
• The efficiency is the same as the push-pull, source follower.

Practical Implementation of the Push-Pull, Common Source Amplifier – Method 1
VDD
M5 M6
M1 M3 VGG3
iOUT
vIN vOUT
M2 M4 VGG4
CL RL
M7 M8
VSS Fig. 060-05

VGG3 and VGG4 can be used to bias this amplifier in class AB or class B operation.
Note, that the bias current in M6 and M8 is not dependent upon VDD or VSS (assuming
VGG3 and VGG4 are not dependent on VDD and VSS).
Practical Implementation of the Push-Pull, Common Source Amplifier – Method 2

VDD
M5
M7 I=2Ib Ib
vin+ M1
M8 M3 M4 M9
vin-
M2
M6
Ib I=2Ib M10
VSS Fig. 060-055

In steady-state, the current through M5 and M6 is 2Ib. If W4/L4 = W9/L9 and W3/L3 =
W8/L8, then the currents in M1 and M2 can be determined by the following relationship:
  
 W1/L 1   W2/L 2 

I1= I =2 I b W7/L 7 = Ib W10/L10 

If vin+ goes low, M5 pulls the gates of M1 and M2 high. M4 shuts off causing all of the
current flowing through M5 (2Ib) to flow through M3 shutting off M1. The gate of M2 is
high allowing the buffer to strongly sink current. If vin- goes high, M6 pulls the gates of
M1 and M2 low. As before, this shuts off M2 and turns on M1 allowing strong sourcing.
Additional Methods of Biasing the Push-Pull Common-Source Amplifier

VDD VDD
VDD -VT+VSat IBias
VDD -VT+2VSat VB2 VB1 vOUT
vOUT
vIN
VT+2VSat
050423-10
vIN
050423-08
Illustration of Class B and Class AB Push-Pull, Inverting Amplifier

Output current and voltage characteristics of the push-pull, inverting amplifier (RL =
1k):
vG2
2V 2mA 2V vG2 2mA
iD1 vG1 vG1
1V 1mA 1V 1mA
iD1 iD2 iD1
iD1
0V 0mA 0V 0mA
iD2 iD2
-1V -1mA -1V v -1mA
vOUT iD2 OUT
-2V -2mA -2V -2mA
-2V -1V 0V 1V 2V -2V -1V 0V 1V 2V

vIN vIN
Class B, push-pull, inverting amplifier. Class AB, push-pull, inverting amplifier. Fig.060-06
Comments:
• Note that there is significant distortion at vIN =0V for the Class B inverter
• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB

BIPOLAR JUNCTION TRANSISTOR OUTPUT AMPLIFIERS

What about the use of BJTs?
VDD VDD VDD
M3
Q1 M2
iB vout vout
iB
M2 Q1
CL M3 CL
VSS VSS VSS
Comments: p-well CMOS n-well CMOS
Fig. 5.5-8A
• Can use either substrate or lateral BJTs.

• Small-signal output resistance is 1/gm which can easily be less than 100.
• Unfortunately, only PNP or NPN BJTs are available but not both on a standard
CMOS technology.
• In order for the BJT to sink (or source) large currents, the base current, iB, must be
large. Providing large currents as the voltage gets to extreme values is difficult for
MOSFET circuits to accomplish.
• If one considers the MOSFET driver, the emitter can only pull to within vBE+VON of
the power supply rails. This value can be 1V or more.
We will consider the BJT as an output stage in more detail in Sec. 7.1.
USING NEGATIVE FEEDBACK TO REDUCE THE OUTPUT RESISTANCE

Concept
VDD
Error M2
Amplifier
iOUT
vIN vOUT
- +
Error
Amplifier CL RL
M1
Fig. 060-07
VSS
rds1||rds2
Rout = 1+Loop Gain
Comments:
• Can achieve output resistances as low as 10.
• If the error amplifiers are not balanced, it is difficult to control the quiescent current in
M1 and M2
• Great linearity because of the strong feedback
• Can be efficient if operated in class B or class AB

Simple Implementation of Neg., Shunt Feedback to Reduce the Output Resistance

VDD
M2
R1 R2 iOUT
vIN vOUT
CL RL
M1
VSS Fig. 060-08
 R1  gm1+gm2 
Loop gain R +R  
1 2 gds1+gds2+GL
rds1||rds2
 Rout =  R  gm1+gm2 
1+R
1  
 +R 
1 2 gds1+gds2+GL
Let R1 = R2, RL = , IBias = 500μA, W1/L1 = 100μm/1μm and W2/L2 = 200μm/1μm.
Thus, gm1 = 3.316mS, gm2 = 3.162mS, rds1 = 50k and rds2 = 40k.
50k|40k  22.22k
 Rout = 
3316+3162  = 1+0.5(143.9) = 304 Rout = 5.42k if RL = 1k)
1+0.5 25+20 
Summary of Output Amplifiers

• The objectives are to provide output power in form of voltage and/or current.
• In addition, the output amplifier should be linear and be efficient.
• Low output resistance is required to provide power efficiently to a small load resistance.
• High source/sink currents are required to provide sufficient output voltage rate due to
large load capacitances.
• Types of output amplifiers considered:
Class A amplifier
Source follower
Class B and AB amplifier
Use of BJTs
Negative shunt feedback

SECTION 5.7 - SUMMARY

Summary of Chapter Topics
• Inverting Amplifiers
Class A (diode load and current sink/source load)
Class AB of B (push-pull)
• Differential Amplifiers
Need good common mode rejection
An excellent input stage for integrated circuit amplifiers
• Cascode Amplifiers
Useful for controlling the poles of an amplifier
• Current Amplifiers
Good for low power supplies
• Output Amplifiers
Minimize the output resistance
Maximize the current sinking/sourcing capability
Chapter 5 – Appendix 5A (7/5/06) Page 5.7-1.
APPENDIX 5A – FREQUENCY RESPONSE BASICS

Complex Frequency (s) Analysis of Circuits
The frequency response of linear circuits can be analyzed using the complex frequency
variable s which avoids having to solve the circuit in the time domain and then transform
into the frequency domain.
Passive components in the s domain are:
1
ZR(s) = R ZL(s) = sL and ZC(s) = sC
s-domain analysis uses the complex impedance of elements as if they were “resistors”.
Example: C1
s-domain A
1/sC1
  conversion  
1
V1 gmV1 R2 C2 V2 V1(s) R2 V2(s)
sC2
   gmV1(s) 
060204-06
Sum currents flowing away from node A to get,

sC1(V2 – V1) + gmV1 + G2V2 + sC2V2 = 0
Solving for the voltage gain transfer function gives,
V2(s) -sC1 + gm  sC1/gm - 1 
T(s) = V1(s) = s(C1+ C2) + G2 = -gmR2 s(C1+ C2)R2 + 1

Complex Frequency Plane

The complex frequency variable, s, is really a complex number and can be expressed as
s =  + j where  = Re[s] and  = Im[s].
Complex frequency plane: j
Positive Imaginary Axis
Negative Real Axis Positive Real Axis


Negative Imaginary Axis
060204-07
It is useful to plot the roots of the transfer function on the complex frequency plane.
For the previous T(s), the roots are:
The numerator root (zero) is s = z1 = +(gm/C1)
The denominator root (pole) is s = p1= -[1/R2(C1+ C2)]
Frequency Response
Frequency response is the result when we replace the complex frequency variable s with
j. (This amounts to evaluating T(s) on the imaginary axis of the complex frequency
plane.)
The frequency response is characterized by the magnitude and phase of T(j).
Example:
a0 + a1s s = j a0 + a1j a0 + ja1
Assume T(s) = b0 + b1s * T(j) = b0 + b1j = b0 + j b1
Since T(j) is a complex number, we can express the magnitude and phase as,
a02 + (a )12  a 1
   b 1
 
|T(j)| = b02 + ( b 1)2 Arg[T(j)] = +tan -1 a0  - tan-1 b0 
For the previous example, the magnitude and phase would be,
1 + (C1/gm)2 Note: Because the zero is on
|T(j)| = gmR2 1 + [ R2(C1+C2)]2 the positive real axis, the
phase due to the zero is
Arg[T(j)] = -tan-1(C1/gm) - tan-1[ R2(C1+C2)] -tan-1( ) rather than +tan-1( ).
More about that later.
Graphical Illustration of Magnitude and Phase

The important concepts of frequency response are communicated through the graphical
portrayal of the magnitude and phase.
Consider our example,
V2(s)  sC1/gm - 1   
  = -T(0)s/z1 - 1 
2 1
T(s) = V1(s) = -gmR2 s(C1+ C 2)R +  s/p1- 1
where T(0) = gmR2, z1 = +(gm/C1) and p1= -[1/R2(C1+ C2)].
Replacing s with j gives [remember tan-1(-x) = - tan-1(x)],
1 + (z1)2
|T(j)| = T(0) and Arg[T(j)] = -tan-1
(z1) - tan -1
[/p2]
1 + ( /p2)2
Graphically, we get the following if we assume |p1| = 0.1|z1|,
1.0 0°
Phase Shift (Degrees)

-20°
Normalized Magnitude
0.8
0.707 -40°
|T(j)|/T(0)
0.6 -60°
0.4 -80°
-100°
0.2
0.707 frequency -120°
0.0 -140°
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
060205-01 Normalized Frequency (/|p1|) Normalized Frequency (/|p1|)
Graphical Illustration of Frequency Response – Continued

If the frequency range is large, it is more useful to use a logarithmic scale for the
frequency. In addition, if one expresses the magnitude as 20 log 10(|T(j)|, the plots can
be closely approximated with straight lines which enables quick analysis by hand. Such
plots are called Bode plots.
0 dB 0°
Slope =
Normalized Magnitude
20log10[|T(j)|/T(0)]
-3 dB
Phase Shift (Degrees)
-20dB/decade -30°
-5 dB
-60°
-10 dB -90°
-120°
-15 dB -3dB frequency
-150°
-20 dB -180°
0.01 0.1 1.0 10.0 100 1000 0.01 0.1 1.0 10.0 100 1000
060205-02 Log Normalized Frequency (/|p1|) Log Normalized Frequency (/|p1|)
To construct a Bode asymptotic magnitude plot for a low pass transfer function in the
form of products of roots:
1.) Start at a low frequency and plot 20 log10(|T(0)| until you reach the smallest root.
2.) At the frequency equal to magnitude of the smallest root, change to a line with a slope
of +20dB/decade if the root is a zero or -20dB/decade if the root is a pole.
3.) Continue increasing in frequency until you have plotted the influence of all roots.
The Influence of the Complex Frequency Plane on Frequency Response

The root locations in the complex frequency plane have a direct influence on the
frequency response as illustrated below. Consider the transfer function:
s/z1 - 1  |p1|  s-z1   s-z1 
T(s) = -T(0) s/p - 1
=-
z1 T(0) 
s-p1
 = - 0.1T(0)  
s-p1where z1 = 10|p1|
1
j |T(j)|/T(0)
j10 1.0
0.8
j10-p1 j8 0.6
j10-z1
0.4
j8-p1 j8-z1
j6
0.2
j6-z1
j6-p1 0.0 
0 1 2 3 4 5 6 7 8 9 10
j4 j4-z1
j4-p1 j2-z1
j2 j0-z1
j2-p1
j0-p1
j0

p1=-1 z1=10 060205-04
Note: The roots maximally influence the magnitude when  is such that the angle
between the vector and the horizontal axis is 45°. This occurs at j1 for p1 and j10 for z1.
Bandwidth of a Low-Pass Amplifier

One of the most important aspects of frequency analysis is to find the frequency at which
the amplitude decreases by -3dB or 1/ 2. This can easily be found from the magnitude
the frequency response.
|A(j)|
A
 0.707A
 
V1(j) V2(j) Bandwidth
  
0 
0 A=0.707 060205-03
Amplifier with a Dominant Root:

Since the amplifier is low-pass, the poles will be smaller in magnitude than the zeros.
If one of the poles is approximately 4-5 times smaller than the next smallest pole, the
bandwidth of the amplifier is given as
Bandwidth = |Smallest pole|
Amplifier with no Dominant Root:
If there are several poles with roughly the same magnitude, then one should use the
graphical method above to find the bandwidth.

Example of Finding the Bandwidth of an Amplifier

Suppose an amplifier has a pole at -10 rads/sec and another at -20 rads/sec. and a zero at
+50 radians/sec. Find the bandwidth of this amplifier if the low frequency gain is 100.
Solution
Since the poles are close together, construct a Bode plot and graphically find the
bandwidth.
dB
3dB
40 -6dB/octave
34
30
-3dB -12dB/octave
20 Bandwidth
10 -6dB/octave
6
0 Frequency (Rad/sec)
12 10 20 100 200 1000
060205-05
From the graph, we see that the -3dB bandwidth is close to 11-12 Rad/sec.

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Chapter 5 – Introduction (7/5/06) Page 5.0-1.

CHAPTER 5 – CMOS AMPLIFIERS

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 5 – Introduction (7/5/06) Page 5.0-2.

Type of Amplifier Output Ideal Input Ideal Output

Current Output Current Zero Infinite

Transconductance Output Current Infinite Infinite

Transresistance Output Voltage Zero Zero

CMOS Analog Circuit Design © P.E. Allen - 2006

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 5 – Introduction (7/5/06) Page 5.0-4.

Components of a CMOS Voltage/Transconductance Amplifier

Voltage Amplifier 060607-01

CMOS Analog Circuit Design © P.E. Allen - 2006

Illustration of Voltage Amplifier Components

Transconductance stages are in the lower two shaded boxes

Chapter 5 – Introduction (7/5/06) Page 5.0-6.

Input Output VDD Input Output

060607-02 Split Power Supplies Single Power Supply

CMOS Analog Circuit Design © P.E. Allen - 2006

Inverting and Noninverting Amplifiers

Load Load vin

Common Common Common

Note that there are two categories of amplifiers:

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 5 – Section 1 (7/5/06) Page 5.1-1.

SECTION 5.1 – INVERTING AMPLIFIERS

vin vin M1 vin M1 M1

060608-02 Class A Amplifiers Push-Pull Amplifier

ACTIVE LOAD INVERTER

The boundary between active and saturation operation for M1 is

Chapter 5 – Section 1 (7/5/06) Page 5.1-3.

Large-Signal Voltage Swing Limits of the Active Load Inverter

CMOS Analog Circuit Design © P.E. Allen - 2006

Small-Signal Midband Performance of the Active Load Inverter

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 5 – Section 1 (7/5/06) Page 5.1-5.

Frequency Response of the MOS Diode Load Inverter

 Vout(Gout + sCM + sCout) = - (gm – sCM)Vin

CMOS Analog Circuit Design © P.E. Allen - 2006

Frequency Response of the MOS Diode Load Inverter - Continued

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 5 – Section 1 (7/5/06) Page 5.1-7.

Example 5.1-1 - Performance of an Active Resistor-Load Inverter

CMOS Analog Circuit Design © P.E. Allen - 2006

CURRENT SOURCE INVERTER

Chapter 5 – Section 1 (7/5/06) Page 5.1-9.

Large-Signal Voltage Swing Limits of the Current Source Load Inverter

This result assumes that vIN is taken to VDD.

CMOS Analog Circuit Design © P.E. Allen - 2006

Small-Signal Midband Performance of the Current Source Load Inverter

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 5 – Section 1 (7/5/06) Page 5.1-11.

Frequency Response of the Current Source Load Inverter

model (x is connected to VGG2): x M2

CMOS Analog Circuit Design © P.E. Allen - 2006

Example 5.1-2 - Performance of a Current-Sink Inverter VDD

Chapter 5 – Section 1 (7/5/06) Page 5.1-13.

0.4 vIN=2.5V vOUT

Small-Signal Performance of the Push-Pull Amplifier

Small-signal analysis gives the following results:

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 5 – Section 1 (7/5/06) Page 5.1-15.