Microprocessors and Microcontrollers – 11EC311

Prodecures, Macros and Interrupts

of 8086
Stack Operation

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In 8086 Stack Pointer Points TOP of the stack
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SS(Base Address) : SP(Offset Address)
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PUSH Decrements SP once for each byte
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POP Increments the SP
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Last in First Out(LIFO)
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Used in CALL and Interrupts

07/08/19 8086 Programming Model - MPMC

Prodecures vs Macros

Procedures
Sequence of Instructions to perform
a specific task which is to be
repeatedly used in the program
Accessed with CALL followed by Accessed with the name given to the
PROCEDURE name, Ends with RET MACRO
Loads the new CS:IP from the
address followed by CALL executes
the Set of Instructions and returns
back to the next instruction to CALL
after RET
Uses STACK
Machine Code is generated once
Macros
Sequence of Instructions to perform
a specific task which is to be
repeatedly used in the program
Set of Instructions written in a Macro
are copied to the called location
Does not use STACK
Generated each time called

07/08/19 8086 Programming Model - MPMC

Prodecures vs Macros

Procedures Macros
Uses PROC and ENDP to define Uses MACRO and ENDM to define

Procedures consumes Lot of time as Macros does not have any control
CALL is to be exectued transfer, executes sequentially
Code Footprint(Size) is less as the Large Code Footprint as the
machine code is generated only Machine code is gerenated for every
once access to Macro

Best for Larger Sub-Routines Best for Smaller Sub-Routines

Best if more Calls have to be made Best for Lesser accesses
Can be defined anywhere in Should be defined before it is called
Program

07/08/19 8086 Programming Model - MPMC

Prodecures vs Macros

Procedures Macros
Syntax: <name> PROC Syntax: <name> MACRO
.......... ..........
.......... ..........
RET ENDM
<name> ENDP
Access: ........... Access: ...........
........... ...........
CALL <name> <name>
............. .............

07/08/19 8086 Programming Model - MPMC

Interrupts in 8086
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Sources of Interrupts
– Internal
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Called within the Program (INT n)
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Caused by an Exception Condition
– External
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Generated by a peripheral (NMI, INTR)
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Classification of Interrupts
–Hardware and Software
– Maskable and Non Maskable
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256 Types of Software Interrupts - Type 0 – Type 255
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Predefined Interrupts - Type 0 – Type 4
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Reserved by INTEL - Type 5 – Type 32
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User Defined Interrupts - Type 33 – Type 255
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Predefined Interrupts in 8086

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Type 0: Divide by Zero Interrupt
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Type 1: Single Step Interrupt (Trap Interrupt)
Trap Flag must be Set
●

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Type 2: NMI (Non- Maskable Interrupt)
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Type 3: Breakpoint Interrupt (Single Byte Instruction)
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Debugging Purpose
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Placing INT 3 whereever debug Required
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Type 4: Interrupt on Overflow
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Occurs if Overflow Flag is Set

07/08/19 8086 Programming Model - MPMC

Interrupt Vector Table

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Stores the Vector Address(Branching Address) of Interrupt
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Each Interrupt requires 4 Bytes of Space
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2 Bytes for IP
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2 Bytes for CS
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256 Types of Interrupts with 4 Bytes Each = 1 KB
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00000h to 03FFFh is space for Vector Table
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Vector Address of INT n is stored in Vector Table having
address
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IP : 2 bytes at n x 4
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CS: 2 bytes at (n x 4) +2

07/08/19 8086 Programming Model - MPMC

Interrupt Vector Table of 8086

07/08/19 8086 Programming Model - MPMC

Steps Involved in Execution of Interrupt

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After interrupt occurs Flag, CS and IP are PUSHED to Stack
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PUSH PSW
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PUSH CS
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PUSH IP
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IP and CS of Interrupt Service Routine are loaded from the
Vector table depending on type of Interrupt from the address
Type n x 4
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Executes Interrupt until IRET
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POPS out IP, CS and Flag from the Stack
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POP IP
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POP CS
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POP PSW
07/08/19 8086 Programming Model - MPMC
Steps Involved in Execution of Interrupt

07/08/19 8086 Programming Model - MPMC

References

●
https://www.sites.google.com/site/sripathroykoganti/my-forms
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D.V.Hall “Microprocessor and Interfacing”, 2nd Edition Tata McGraw
Hill Publishing Company,2006.
●
A.K. Ray & K. M Bhurchandi, “Advanced Microprocessors &
peripherals”, Tata Mc Graw Hill Publishing Company 2002.
●
Rajkamal, “Microcontrollers - Architecture, Programming, Interfacing
& System Design”, 2 nd edition, Pearson Education.

07/08/19 8086 Programming Model - MPMC

 Thank You

07/08/19 8086 Programming Model - MPMC