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Modeling and cosimulation of FPGA-based SVPWM control for PMSM

Conference Paper · December 2005

DOI: 10.1109/IECON.2005.1569133 · Source: IEEE Xplore

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 IECON 2005
The 31st Annual Conference of the IEEE Industrial Electronics Society
Sheraton Capital Center – Raleigh, North Carolina, USA 6-10 Nov 2005

IECON 2005
The Thirty-First Annual Conference
of the IEEE Industrial Electronics Society

Sheraton Capital Center

Raleigh, North Carolina, USA

6-10 November 2005

Sponsored by
IEEE Industrial Electronics Society

Hosted by
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Edited by
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 Copyright © 2005 by The Institute of Electrical and Electronics Engineers, Inc.
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 Modeling and Cosimulation of FPGA-Based SVPWM Control for PMSM
Simin Jiang Jiangang Liang Yadong Liu
IMS-Mechatronics Lab, MAE Dept. IMS-Mechatronics Lab, MAE Dept. IMS-Mechatronics Lab, MAE Dept.
University of California, Davis University of California, Davis University of California, Davis
Davis, CA 95616, USA Davis, CA 95616, USA Davis, CA 95616, USA
sjiang@ucdavis.edu jgliang@ucdavis.edu ydliu@ucdavis.edu

Kazuo Yamazaki Makoto Fujishima

IMS-Mechatronics Lab, MAE Dept Mori Seiki, The Machine Tool Company
University of California, Davis 362 Idono, Yamato-Loriyama
Davis, CA 95616, USA Nara, Japan
kyamazaki@ucdavis.edu fujisima@moriseiki.co.jp

Abstract—This paper presents the modeling and cosimulation
method of a FPGA based Permanent Magnet Synchronous
Machine (PMSM) control system; the current control loop of
PMSM control system is Space Vector Pulse Width Modulation
(SVPWM); a new FPGA based Top-Down design method is
proposed. According to the design method, the function model is
built in Matlab environment, and the behavioral model (VHDL
model) is programmed in the synthesis software platform. In
order to realize the hardware/software codesign, the
cosimulation between function model and VHDL model is
implemented by integrating two models into one cosimulation
model. By the cosimulation, the hardware timing and the
function simulation can be tested and verified at the same time.
In this paper, the case study shows that the design efficiency can
be improved greatly by using this cosimulation method.
I. INTRODUCTION
Today, Digital Signal Processor(DSP) and microcontroller
have been widely used for PMSM control system. But global
competition has brought immense pressure to the product
development of PMSM control system. For the PMSM control
system design, the DSP/MCU based hardware design is very
time-consuming. So if the hardware of PMSM control system
can be re-configurable, it will help to reduce the new PMSM
control system development time and cost. FPGA, as a new
re-configurable hardware platform, has been used for AC
motor control system [1-2][6-7]. VHDL is usually used for
developing the FPGA based motor control system [3-5].
In this paper, a new design method of PMSM control system
based on FPGA is proposed. The PMSM control system is
programmed by using VHDL and is implemented in the FPGA
platform. The FPGA platform realizes the Field Oriented
Control (FOC) algorithm for PMSM, including SVPWM
control for current loop, velocity control loop, position control
loop and all necessary re-configurable I/Os for data
communication and feedback sensing system. According to
the proposed Top-Down design method, the cosimulation of
function model and VHDL model is the most important step.
The function model is built in Matlab environment, and the
behavioral model (VHDL model) is programmed in the
synthesis software platform. In order to realize the
hardware/software codesign, the cosimulation between
function model and VHDL model is implemented by
integrating two models into one cosimulation model. The
hardware timing and the function simulation can be tested and
verified at the same time. By using such a method, the design
efficiency can be improved greatly.
II. SVPWM CONTROL OF PMSM
A. SVPWM Control
In order to control PMSM efficiently, the Field Oriented
Control (FOC) is often applied. FOC is an excellent control
algorithm that is used to control space vectors of magnetic flux,
current and voltage. Actually, FOC relies on the SVPWM
control strategy. By using SVPWM, it is possible to set up the
coordinate system to decompose the vectors into a magnetic
field-generating axis and a torque-generating axis. So by using
SVPWM, the PMSM control is almost the same as the DC
motor control, the magnetic flux and torque can be controlled
separately.
Generally, in the PMSM control system, the SVPWM
module generates the vector control signals, and then these
PWM signals are sent to the inverter in order to drive the
motor. The basic diagram of SVPWM control for PMSM can
be described as Fig. 1. The power switches of the inverter,
shown as Fig. 2, consist of 6 IGBT switches (S1, S2, …, and
S6).
B. Space Vector Definition and d-q Transformation
The model used for vector control design can be realized by
using space vector theory. The three phase motor quantities,
such as voltages, current, magnetic flux, etc. are expressed in
terms of complex space vectors. Such a model is valid for any
instantaneous variation of voltage and current and adequately
describes the performance of the PMSM under both steady
state and transient operation. The complex space vectors can
be described using only two orthogonal axes, which are direct
axis and quadrature axis respectively. So the three-phase

0-7803-9252-3/05/$20.00 ©2005 IEEE 1538

current can be decoupled as two separate parameters and can stator. So the reference frame should be dynamical and the
be controlled as DC motor. transient reference should be attached to the rotor flux linkage
space vector. The reference axes called direct axis (d) and
AC quadrature axis (q), shown as Fig. 3.
Power
q-axis β -axis
6
θ ref + Position PWM Current Encoder b-axis
Control Generation Feedback d-axis
–
+ ωref
θr Vα Vβ
θ α -axis ω
–
α ,β θ r Up/Down
Velocity a-axis
Control a,b,c Counter
c-axis
i qref ia ib
Vq Vd
+ a,b,c θr
Current
Control d,q Fig. 3. Stator current space vector description
–
ωr However, vector control is performed entirely in the d-q
iq id dθ r reference coordinate system to realize the synchronous control
Flux
Control dt of PMSM. So α - β vectors need to be transformed to d-q
coordinates. The transformation from α - β to d-q can be
i dref expressed as follows:
+ –
id = iα cosθ + iβ sin θ
 (2)
Fig. 1. The basic diagram of SVPWM control for PMSM iq = −iα sin θ + iβ cosθ
This transformation is also called as Park transformation.
S1 S5 After finishing the current control, the control variable Vd
S3
and Vq will need to be inversely transformed to Va , Vb
U DC A
B and Vc , and then the control variables can be sent to the three
C C phases of PMSM through power module. To the SVPWM
control, only the inverse Park transformation is needed, then
S2 S4 S6 we can get the six switch output signals by Vα and Vβ . The
inverse Park transformation can be described as follows:
Fig. 2. Power switches of the inverter Vα = Vd cosθ − Vq sin θ
 (3)
Vβ = Vd sin θ + Vq cosθ
Assuming ia , ib and ic are the instantaneous currents of
three phase stator, and iα and iβ are related to α -axis and
C. PWM Signal Generation
β -axis respectively, shown as Fig. 3.
We can get the transformation from three-phase currents ia , The motor stator voltage vector can be expressed as a
ib and ic to the two-phase orthogonal stator axis: iα and iβ . combination of the power bridge (inverter) output voltage Van ,
Vbn and Vcn , and can be described in a vector form as:
This transformation is also called as Clarke Transformation.
2π 4π
iα = ia 2 j j 
 Vs = Van + Vbn ∗ e 3 + Vcn ∗ e 3  = Vα + jVβ (4)
3
 1 2 (1)  
i β = ia + ib
2π
 3 3
Where, Van = Vbase sin(ωt ) , Vbn = Vbase sin(ωt − ) and
Actually, α -axis and β -axis are stationary reference 3
frame attached to the stator. To the PMSM model, the rotor 4π
Vcn = Vbase sin(ωt − ).
always rotates synchronously with the electrical speed of 3

1539
 Vbase is the amplitude of the fundamental component. As However, Equation (8) is dependent on the sector where
Fig. 4 illustrates, there are eight basic switching configurations V out is. In order to calculate the switching time, the sector
of the three-phase PWM inverter. Their corresponding voltage needs to be determined first, then the adjacent vectors V n and
vectors are depicted in Fig. 4, expressed as:
V n+1 can be chosen.
2  (n − 1) 
V n = Vdc ∗ exp j π (5) To determine the sector, we can calculate the projections
3  3 
Va , Vb and Vc of Vαref and Vβref in the (a, b, c) plane by
Where Vdc is the DC-link voltage, and n =1, 2, 3…, 6 and
using inverse Clark transformation:
V 0 =V 7 = 0 . 
Va = Vβref

β -axis  1 (9)
( − 1/ 3,1/ 3 ) ( 1/ 3,1/ 3 ) Vb = ( 3Vαref − Vβref )
 2
S1  1
V2 (110) Vc = 2 (− 3Vαref − Vβref )
V3 (010 ) S0
S2 Vout Then based on Equation (9), we can calculate
N = sign(Va ) + 2 * sign(Vb ) + 4 * sign(Vc ) . Map N to the
(-2/3, 0) V0 (111) actual sector of the output voltage reference by referring to the
V4 (011) V1(100) (2/3, 0) following relationship:
V7 (000 )
α -axis N 1 2 3 4 5 6
S3 S5 Sector 1 5 0 3 2 4
V5 ( 001) V6 (101) After getting the sector of output voltage reference and
S4 calculating the switching time of vectors V n and V n+1 , the
( − 1/ 3,−1/ 3 ) ( 1/ 3,−1/ 3 ) vector switching time pattern for the power switches of
inverter can be described as Fig. 5.
Fig. 4. SVPWM description
T pwm
In order to generate the SVPWM switching signals, two
T0 / 4 T1 / 2 T2 / 2 T0 / 2 T2 / 2 T1 / 2 T0 / 4
adjacent vectors and a zero vector ( V 7 or V 0 ), can be chosen
to express the control reference vector V out :
Vout = VnT1 + Vn +1T2 + Vnull T0 (6) V7 (000 ) Vn Vn +1 V0 (111) Vn +1 Vn V7 (000 )

Where V n and V n+1 are the adjacent vectors. V null is a zero

Fig. 5. Vector switching time pattern for the inverter
vector ( V 7 or V 0 ). T1 , T2 and T0 are the switching time of
three vectors. III. THE FUNCTION MODEL
In order to get V out , the two adjacent vectors can be chosen
correctly. And the switching time of three vectors ( V n , V n+1 No matter what kind of hardware and software are chosen,
the basic function modules of PMSM control system are
and V null ) can be figured out by projecting the reference always identical. Therefore, during the function analysis stage
vector V out on the adjacent vectors. of the system design, a function model can be extracted from
the design specification to express the control system in a
T = T1 + T2 + T0
 pwm neutral expression. The function model includes all necessary
 T1 T function modules for PMSM control system. Such a function
V out = V n + 2 V n+1 (7) model is usually built in C/C++ language and the function
 T pwm T pwm
analysis can be implemented by using Simulink of Matlab.

V out = Vαref + jVβref The function model built in this paper includes PI controller,
SVPWM, d-q transformation, etc, shown as Fig. 1. The
Where Vαref and Vβref are the transformation result from Vd function model can be integrated into the Simulink model by
and Vq through the inverse Park transformation. using S-function of Matlab. As a result, the function
simulation can be done easily by using the Simulink model. So
So from Equation (7), T1 and T2 can be obtained by the the parameters of PMSM control system can be determined.
following equation: As shown as Fig. 6, the simulation model of PMSM control
[T1 T2 ]T = T pwm [Vn Vn+1 ]−1 Vαref [ Vβref ]
T
(8) system includes the SVPWM, Clark and Park transformation,
and PI controller, which are constructed by C/C++ language

1540
 Universal Bridge
g 1.5 Tm
is_abc
+
A A
m m wm
DC B B
-
thetam
C C
Permanent Magnet M achines
Synchronous Machine1 M easurem ent
0
Dem ux1
d-q Iabc
A
U alpha
PID PID
alpha-beta m Pulses a
U beta B
Sine Wave PID Controller1 PID Saturation angle
b
Controller Discrete SV PWM C
Park reverse Generator c 2
Gain a
transform T hree-Phase m
b dq
V-I M easurem ent
angle
d-q
transform
m

Fig. 6. The Simulink model of PMSM

and linked to Simulink model by using S-function. After the Design

function analysis is implemented in Matlab platform, if all specification
system requirements are met, the function model can be used
Function
for the behavioral modeling of the next stage. Logical model analysis
(C/C++ language)
IV. THE VHDL MODEL
Matlab Function simulation Co-simulation
A. Behavioral Modeling and Synthesis Simulink of PMSM system of Simulink
model and
VHDL model
Usually, VHDL can be used for modeling the behaviors of Behavioral VHDL
PMSM control system. Thus, the HDL-based design flow can modeling
be used for the behavioral modeling. All of the behavioral
modules of PMSM control system need to be constructed in Behavioral
VHDL, and then the behavioral simulation can be done. If the synthesis
verification is right, the placing and routing will be Behavioral
VHDL modeling and
implemented. In this paper, the Xilinx ISE Foundation 6.3 has Testbench Hardware simulation
synthesis
been used for the VHDL modeling and synthesis tool. Fig. 7 (Modelsim) (verification)
shows the VHDL based design flow.
Firstly, we must code the modules in VHDL based on the Placement and
function model of PMSM control system. Secondly, the routing
synthesis tool analyzes the VHDL code for correctness and
synthesizes the digital logic circuit by translating the VHDL Generating the
code into the netlist related to the FPGA device chosen. In programming file Physical
order to know whether the circuit works as it’s supposed to do, implementation
FPGA Physical
the design verification needs to be made. According to the
platform Prototype
netlist and specific input/output pattern, we can code the
testbench VHDL, then a simulator, for example, Modelsim
which is a hardware simulation platform from Mentor Fig. 7. VHDL based design flow
Graphics will simulate the circuit and verify the netlist. Finally,
the netlist primitives can be mapped to the target device, and programming language does. So it is effective for modeling
the components will be placed in the CLBs and IOBs of FPGA the PMSM control system by using VHDL. VHDL supports a
device. variety of data types, including Boolean, Integer, Real,
Std_logic, etc. But some types cannot be synthesized, for
B. Modeling Method example Floating-Point data type. When using VHDL for
modeling the control system, one more quick method is to use
Although VHDL is a hardware description language and the reusable modules, so called Intellectual Property (IP) core.
primarily used for hardware design, it also has the same According to the top-down design method, after finishing
properties of calculation and software programming as other the function analysis, the VHDL modeling needs to be made.

1541
Actually, VHDL is different from the object-oriented
programming language, such as C/C++. Because VHDL is
mainly used for describing digital signals, it cannot be used for
power and analog signals. However, the main function model
of SVPWM is digital. So when we construct the PMSM motor
control systems, VHDL can be used to develop the model.
C. Floating-Point Algorithm
The basic functions have been described in Section II,
because the input and output of control system will be
implemented by digital signals, the variables of control system
are signal type or integer type. However, both PI control
algorithm and SVPWM control require floating-point
arithmetic. So the VHDL modules need to implement the
floating-point algorithm. In order to realize the floating- point
algorithm, we will use fixed-point algorithm and
Normalization method to realize the floating- point
algorithm. .
[-1, 1] can be mapped to 16-bit signed fixed-point data. The
first bit of the 16-bit data is the sign bit. So the maximum and
minimum possible values for the coefficients can be
determined by calculating the following equations:
Maximum value= 2N −1 − 1 ( N = 16 , it equals to 32767)
Minimum value= − 2 N −1 ( N = 16 , it equals to -32768)
The actual Normalization format can be 1.F (F=N-1). The
first bit indicates the sign bit and F is the fractional bit
By applying this floating-point algorithm for VHDL
modeling, PI controller, SVPWM and other floating-point
related to calculation can be implemented.
D. Reusable IP Core
When developing VHDL modules for PMSM control
system, some functions are available, such as PCI module,
SINE/COSINE calculation module. Because many companies
have already developed these VHDL modules, so called
Intellectual Property (IP), it will improve the design efficiency
and help to save the design time. Intellectual Property (IP) is a
functional design block in a form of synthesizable RTL VHDL
code, or a specific netlist. In most cases, the IP core can be
used for silicon design many times, in many different
applications, and consequently offers a fast, low risk
alternative to developing the module.
According to the description of PMSM control system in
Section II, when implementing some calculations of PMSM
control, SINE/COSINE and floating-point divider function are
needed. Xilinx also provides these IP cores for specific
application. So we can apply the SINE/COSINE and
floating-point divider IP core to VHDL modeling directly.
V. COSIMULATION BETWEEN FUNCTION AND VHDL MODEL
In order to perform the cosimulation between function and
VHDL model, Link for Modelsim® of Matlab is used. Link for
1542
ModelSim® provides a fast bidirectional connection between
MATLAB and Simulink and Mentor Graphics' HDL simulator,
ModelSim. It enables direct cosimulation and we can
efficiently verify and cosimulate RTL-level models from
within MATLAB/Simulink. Link for ModelSim provides the
support to develop the software test benches in
MATLAB/Simulink for HDL entities, including HDL models
in larger-scale system models developed and simulated in
Simulink, generating test vectors to test, debug, and verify the
HDL model against its original functional model of MATLAB
or Simulink. In addition, it can provide behavioral modeling
capabilities for HDL simulation in MATLAB and Simulink
and verify HDL implementations in MATLAB environment.
As discussed in Section IV, the VHDL model has been
established, and the functional model has also been
constructed based on Matlab and Simulink. Now the VHDL
modules can be inserted into the functional model and replace
the corresponding module in functional model. For example,
PI controller module of VHDL can be inserted into the PMSM
function model and replace the PI controller block of Simulink.
Fig. 8 shows this cosimulation model of connection between
VHDL model and Simulink model of PMSM, in which PI
controller, d-q reverse transformation and SVPWM signal
generation modules are added into the Simulink model.
When connecting VHDL module to Simulink model, the
Link for Modelsim block needs to be created. We need to
define the Input/Output port and Clock signal according to the
VHDL module. At the same time, we need to clarify the data
type of the port connecting VHDL model to Simulink model.
For example, the ports IQ and IQ_REF are input ports of
VHDL module of PI controller, and their signal type is
std_logic_vector, so a data type conversion block needs to be
added to match the signals. Shown as Fig. 8, the PI controller
and SVPWM modules are connected with Simulink model of
PMSM control system. In this example, the frequency of
SVPWM generation model is 20KHz; the DC voltage is 300V;
the load equals to 1.5NM. This example uses a PMSM with 2
pairs of poles, 1.7NM, 300VDC. The velocity reference is
ω ref = 100 sin(100πt ) rad/s. Fig. 9 illustrates the experiment
results of the three PMSM phase current. This example
explains that the cosimulation between VHDL model and
simulink model can testify the VHDL modules efficiently.
VI. CONCLUSION
In this paper, a new FPGA based PMSM control system is
proposed, and the Top-Down design method based on FPGA
is presented. The PMSM control system is programmed in
VHDL, and then is implemented in the FPGA system. During
the design, the cosimulation between function model and
VHDL model has been implemented. The cosimulation
between function model and VHDL model realizes the timing
and control simulation by using Link-for-Modelsim® of
Matlab. The hardware/software codesign of PMSM control
system can be realized by this means.
 Uni versal Bri dge

g
1.5 Tm
+ is_abc
A A
DC m m wm
B
B
thetam
- C
C
M achi nes
PMSM
M easurem ent
i nt16 vel oci ty_REF
Iabc Dem ux1
A
Si ne Wave currentcom m and int16 IQ_REF
Conv1 a
vel oci ty B
vq doubl e
b
IQ
vel oci ty PI M odul e1 Saturati on C
c
ia
PI VHDL M odule T hree-Phase id double
m
V-I M easurem ent
Conv11
ib

0 int16 vd
iq
va ual pha
Conv5 2 T HET A
i nt16 vq
QOUT double In1 Out1 Gain dq.vhd
Conv3
vb ubeta Conv6
T HET A
Subsystem
dq_reverse.vhd SVPWM Generator
Conv4 Subsystem 1

Conv2 i nt16 Out1 In1 Conv8

int16 doubl e
Conv7

i nt16

Fig. 8. Cosimulation between function model and VHDL model

15
Ia
Ib
Ic
10

5
Isabc(A)

-5

-10
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
T(s)

Fig. 9. The three-phase current of PMSM

ACKNOWLEDGMENT
International Users Forum Fall Workshop, 2000. Proceedings 18-20 Oct.
2000, pp:113–117
Mori Seiki Co., LTD, Xilinx, Inc., and Mentor Graphics, [4] Poure, P., Aubepart, F., Braun, F., “A design methodology for hardware
Inc. sponsor this research. The authors wish to express their prototyping of integrated AC drive control: application to direct torque
sincere appreciation for the support. control of an induction machine,” Rapid System Prototyping, 2000. RSP
2000. Proceedings. 11th International Workshop on 21-23 June 2000,
pp:90–95
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