CBT BITS FOR DDTV SUBJECT

UNIT-I
OBJECTIVE QUESTIONS

1. which of the following is not an abstraction level in verilog ( )

a. circuit level. b. gate level c. behavioral level d. dynamic level
Ans: d

2. ---------- is the basic element at circuit level

a. gate b. switch c. system d. none of the above.
Ans: b

3. --------- is the suitable example for switch level constructs.

a. inverter. b. OR gate c. “+” operator d. AND gate.
Ans: a

4. “verilog has basic MOS switches built into constructs”. Statement is-
a. true b. false c. partially correct d. none
Ans: a

5. Basic gates are available as ready made modules called--------- in verilog HDL.
a. inverters. b. switches c. primitives. d. structures.
Ans: c

6. AND gate is suitable for --------- level of abstraction.

a. gate b. switch c. behavioral d. data flow
Ans: a

7. Structural modeling is the second name of

a. circuit modeling b. behavioral modeling c. data flow modeling d. gate level modeling
Ans: d

8. All possible operations are represented as----------- in data flow level model.
a. assignments b. statements. c. variable. d. none
Ans: a

9. ----------- level is the system level itself.

a. data flow b. behavioral c. gate level d. circuit
Ans:b

10. ------------ in verilog calls for concurrency of operation.

a. design b. synthesize c. description d. simulation
Ans: d

11. Translation of debugged design into corresponding output is called------------

a. synthesis b. testing c. timing d. none
ANS: a
12. Testing has two dimensions i.e. functional tests and ---- tests.
a. behavioral b. design c. timing d. none
Ans:c

13. -------------- can be used for accessing the variables within master modules.
a. design addressing b. sequential addressing
c. hierarchical addressing d. all of the above.
Ans: c

14. PLI stands for------------------

a. Programming Loop Identification b. Planned Language Interface.
c. Program Loop Interface. d. Programming Language Interface.
Ans:d

15. Begin and end signify---------- in verilog HDL.

a. comments b. keywords. c. characters. d. strings
Ans: b

16. Assignments are ------------ in nature at data flow level.

a. non concurrent b. variable c. concurrent d. in variant.
Ans: c

17. Which of the following is not a white space character?

a. \b b. \t c. \n d. \e
Ans: d

18. In a number representation, 8’hf4, ‘h’ stands for-------------

a. sign bit b. base of the number c. decimal number d. bit width
Ans:b

19. In logic values representation of verilog HDL, ‘z’ defines-----------

a. high impedance state b. unknown value. c. signal strength d. none of the above.
Ans:a

20. if a signal line ‘a’ is driven by two sources, b at level 1 with strength “ pull 1” & c at level 0 with
strength “strong 0” then ‘a’ will take the value of what?
a. z b. x c. 0 d. 1
Ans:c

21. -------- are generalized modules that already exist in verilog

a. String b.key word c. system tasks d. primitives
Ans: d

22. in the following statement and g1(O, I1,I2,…………,In); g1 specifies…………….

a. and gate b. name of the instantiation c. input d. output
Ans: b
23. ---- keyword specifies settings done initially
a. Begin b. end c. initial d. none
Ans:c

24. ---monitors variables specified whenever any of those changes

a. $monitor b.$display c .$time d. $stop
Ans: a

25. ------------- when encountered exists simulation

a. $stop b.$finish c. $exit d.$end
Ans:b

26. if for an and gate primitive if i/p1=z, i/p2 =x , then the output is in ---------- state.
a. 0 b.1 c. X d. Z
Ans: c

27. the last statement on any module definition is keyword----------

a. end module b.endmodule c. end d. exit
Ans: b

28. in a BUF gate, if the only input is at ‘1’ state, the o/p is -------
a. x b. z c.0 d. 1
Ans: d

29. the below figure defines

a. buf if0(out,in,control); b. buf if1(out,in,control);

c. not if0(out,in,control); d.not if1(out,in,control) 1)

Ans: c

30. in a tristate buffer, when control= ----------, out is cut off from i/p and tristated
a. 0 b.1 c.X d. none of the above
Ans: a

31. the general instantiation of array type is-----------

a. and(a,b,c); b.and gate[mm:nn]; c. and gate(a,b,c); d.and gate [mm:nn](a,b,c);
Ans:d
32. for the module below:
module and1(c,a,b)
input a,b; output c; and(c,a,b); endmodule.
For a test bench input with #2 a=1, b=0; #4 a=1, b=1;
The output goes at logic one at--------------ns.
a. 0 b.6 c.2 d. 4
Ans:b

33. –construct repeats assignment seq. cyclically until simulation stops

a. Initial b.begin c. always d. all of the above
Ans:c

34. which of the foll. Is not a delay type?

a. net delay b.gate delay c. tristate gate delay d. switch delay.
Ans:d

35. wire #2nn; depict --- type of thedelay.

a. gate delay b.net delay c. tristate gate delay d. register delay
Ans: b

36. valid format for different propogation delays are

a. wire #(2,1)nm; b. #2 wire #1 nm; c. Wire nm #(2,1); d. None of the above.
Ans:a

37. and # 3 g(a,b,c); denotes --------

a. net delay b. and delay c.gate delay d. module delay
Ans:c

38. in the format stmt. Shown : bufif1@(1,2,3)b1(a0,ai,c); the first number stands for------------
a. negative transition of output b.positive transition of output c. control signal d. none
Ans: b

39. which of the following gate primitive has the strongest strength?
a. Pull b. weak c. strong d.supply
Ans: d

40. -------------- types of nets have a charge storage capacity with them.
a. Reg b. net c. wire d.trireg
Ans:d

41. Verilog has _____for test bench and design

a) Different code b) Same code c) No code d) None of the above
Ans:a

42. A block comment begins with

a) / b) // c) !! d) --:
Ans: b
43. Simulation at uniform levels obtains____
a) non persistence b) loops c) concurrency d) synthesis
Ans: c
4 4. Verilog HDL can design in which level of decription
a)circuit level b)gate level c)data flow level d)all the above
Ans: d
45. RTL stands for
a)resistor transistor logic b)resistor transfer level c)register transfer level d) non
Ans: c

46. In logic values representation of verilog HDL, ‘z’ defines-----------

a. high impedance state b. unknown value. c. signal strength d. none of the above.
Ans:a

47. In a number representation, 8’hf4, ‘h’ stands for-------------

a. sign bit b. base of the number c. decimal number d. bit width
Ans:b

48. In numbers token if size is not mentioned what is the default size
a)32 bits b)16 bits c)8 bits d)64 bits
Ans: a

49. Wire[3:0]a represents

a)single bit b)4 bit vector c)3 bit vector d) non
Ans: b

50. Symbol identification of system task

a)# b)& c)$ d)*
Ans:c

51. $finish task,when encountered

a)suspends simulation b)exits simulation c)a&b d) non
Ans:a

52. If all the inputs are at one then output state is 1 for which gate
a)OR gate b)AND gate c)NAND gate d)NOR gate
Ans: b

53. If sign is not mentioned in numbers token which sign it consider

a)positive b)negative using 2’s complement c)negative using 1’s complement d) non
Ans:a

54. The higher level of design description next to circuit level is________ level.
a)switch level b)gate level c)data flow level d)behavioral level.
Ans:b

55. In verilog,the system task used for controlling system is

a)$display b)$monitor c)$monitor d)all the above
Ans:c
56. The two groups of data types are,
a)variable and net type b)wire and tri-data type c)integer d)real
Ans:a

57. Functions which are used in all programming language is known as

a) subroutines b)level c)programs d)language
Ans: a

58. -------------- can be used for accessing the variables within master modules.
a. design addressing b. sequential addressing
c. hierarchical addressing d. all of the above.

59. PLI stands for------------------

a. Programming Loop Identification b. Planned Language Interface.
c. Program Loop Interface. d. Programming Language Interface.

Ans:d

60. Begin and end signify---------- in verilog HDL.

a. comments b. keywords. c. characters. d. strings
Ans:b

61. Assignments are ------------ in nature at data flow level.

a. non concurrent b. variable c. concurrent d. in variant.
Ans:c

62. Which of the following is not a white space character?

a. \b b. \t c. \n d. \e
Ans:d

63. In a number representation, 8’hf4, ‘h’ stands for-------------

a. sign bit b. base of the number c. decimal number d. bit width
Ans:b

64. In logic values representation of verilog HDL, ‘z’ defines-----------

a. high impedance state b. unknown value. c. signal strength d. none of the above.
Ans:a

65. if a signal line ‘a’ is driven by two sources, b at level 1 with strength “ pull 1” & c at level 0 with
strength “strong 0” then ‘a’ will take the value of what?
a. z b. x c. 0 d. 1
Ans:c

66. ------------ in verilog calls for concurrency of operation.

a. design b. synthesize c. description d. simulation
Ans:d
67. Translation of debugged design into corresponding output is called------------
a. synthesis b. testing c. timing d. none
Ans:a

68. Testing has two dimensions i.e. functional tests and ---- tests.
a. behavioral b. design c. timing d. none
Ans:c

69. -------------- can be used for accessing the variables within master modules.
a. design addressing b. sequential addressing
c. hierarchical addressing d. all of the above.
Ans:c

70. PLI stands for------------------

a. Programming Loop Identification b. Planned Language Interface.
c. Program Loop Interface. d. Programming Language Interface.
Ans: d

71. Begin and end signify---------- in verilog HDL.

a. comments b. keywords. c. characters. d. strings
Ans:b

72. In a number representation, 8’hf4, ‘h’ stands for-------------

a. sign bit b. base of the number c. decimal number d. bit width

Ans:b

73. In numbers token if size is not mentioned what is the default size

a)32 bits b)16 bits c)8 bits d)64 bits

Ans:a

74. Wire[3:0]a represents

a)single bit b)4 bit vector c)3 bit vector d) non

Ans:b

75. Symbol identification of system task

a)# b)& c)$ d)*

Ans:c

76. $finish task,when encountered

a)suspends simulation b)exits simulation c)a&b d) non

Ans:a
77. Assignments are ------------ in nature at data flow level.
a. non concurrent b. variable c. concurrent d. in variant.
Ans: c

78. Which of the following is not a white space character?

a. \b b. \t c. \n d. \e
Ans: d

79. In a number representation, 8’hf4, ‘h’ stands for-------------

a. sign bit b. base of the number c. decimal number d. bit width
Ans:b

80. In logic values representation of verilog HDL, ‘z’ defines-----------

a. high impedance state b. unknown value. c. signal strength d. none of the above.
Ans:a

81. if a signal line ‘a’ is driven by two sources, b at level 1 with strength “ pull 1” & c at level 0 with
strength “strong 0” then ‘a’ will take the value of what?
a. z b. x c. 0 d. 1
Ans:c

82. Which of the following is not a white space character?

a. \b b. \t c. \n d. \e
Ans:d

83. In a number representation, 8’hf4, ‘h’ stands for-------------

a. sign bit b. base of the number c. decimal number d. bit width
Ans:b

84. In logic values representation of verilog HDL, ‘z’ defines-----------

a. high impedance state b. unknown value. c. signal strength d. none of the above.
Ans:a

85. if a signal line ‘a’ is driven by two sources, b at level 1 with strength “ pull 1” & c at level 0 with
strength “strong 0” then ‘a’ will take the value of what?
a. z b. x c. 0 d. 1
Ans: c

86. The various types of sequential models provided by verilog for storing data are,

a)feedback model b)capacitive model c)implicit model d)all the above

Ans: d

87. The simulation task is controlled by $stop and _______construct.

a)$repeat b)$random c)$finish d)$hold.

Ans: d
88.Formal verification tools do not perform

a)verification b)observation c)simulation d)assertion

Ans:d

89. Trun-on and trun-off delays are associated with __________ switches

a) uni-directional b) bi-directional c) both a and b d) none

Ans:a

90. module path can be specified in a specify block as,

a)simple path b)edge-sensitive path c)state-dependent path d)all the above

Ans: d

91. The parameter values can be overridden or assigned by preceding the assignments
with_____________ keyword.

a)defparam b)specparam c)localparam d)none

Ans: a

92.__________task is used to completely stop the simulation

a)$stop b)$strobe c)$finish d)none

Ans: c

93. The keywords _______ are used to group statements into parallel blocks.

a)begin b)fork c)join d)both b and c

Ans: d

94. The non-blocking assignments are used to implement the ________________ logic
a)combinational b)sequential c)both a and b d)none

Ans:c

95._______ statement is a simple construct in a module for multiple branching.

a)for b)while c)forever d)case

Ans:d
96.Which of the following is a set of specially selected input patterns?

a) test pattern b) debugger pattern c) bit pattern d) byte pattern

Ans:a

97. Which is applied to a manufactured system?

a) bit pattern b) parity pattern c) test pattern d) byte pattern

Ans:c

98. Which of the following is based on fault models?

a) alpha-numeric pattern b) test pattern c) bit pattern d) parity pattern

Ans:b

99. which of the foll. Is not a delay type?

a. net delay b.gate delay c. tristate gate delay d. switch delay.
Ans:d

100. wire #2nn; depict --- type of thedelay.

a. gate delay b.net delay c. tristate gate delay d. register delay
Ans: b

101. valid format for different propogation delays are

a. wire #(2,1)nm; b. #2 wire #1 nm; c. Wire nm #(2,1); d. None of the above.
Ans: a

102. and # 3 g(a,b,c); denotes --------

a. net delay b. and delay c.gate delay d. module delay
Ans: c

103. in the format stmt. Shown : bufif1@(1,2,3)b1(a0,ai,c); the first number stands for------------
a. negative transition of output b.positive transition of output c. control signal d. none
Ans: b

104. which of the following gate primitive has the strongest strength?
aPull b. weak c. strong d.supply
Ans: d

205. -------------- types of nets have a charge storage capacity with them.
a. Reg b. net c. wire d. trireg
Ans:d