GUNEET ARORA

16BEC0578

WINTER SEMESTER 2018-19

ECE 4003
DIGITAL ASSIGNMENT-1

NAME: Guneet Arora

REG. NO.: 16BEC0578
SLOT: E1+TE1
FACULTY: Prof. Ashish P
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1. Create a plot with the three processor technologies on the x

axis, and the three IC technologies on the y-axis. For each axis,
put the most programmable or flexible form closest to the
origin, and the most customized form at the end of the axis.
Plot the 9 points and explain features and possible occasions
for using each. [Hint: Processor technologies are General
Purpose Processor, Single Purpose Processors and ASIPs. The
IC technologies are Full custom VLSI, semi-custom and PLDs].
1A)

1. GPP + PLD the device is flexible since it can run a variety of applications. Since
the designers are using a PLD they can easily change the features of the GPP. This
situation may occur in the development and testing of a GPP.

2. AISP + PLD This device will run a class of applications. Since the designers are
using a PLD they can easily change the features of the ASIP. This situation may be
used when developing and testing an ASIP.

3. SPP + PLD This device will run a single program. However, since the designers
are using a PLD they can easily modify the program or make corrections. This
situation may occur when developing and testing an SPP.

4. GPP + Semi-Custom This device will execute a variety of applications. Since we

are using semi-custom technology, once programming/connection are done the
designers cannot change them. A situation where this may occur is when the GPO
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is already developed and tested and a designers desire an IC but not the cost and
time of making a full-custom IC.

5. ASIP + Semi-Custom This device will execute a class of applications well since it
was optimized with those applications in mind. Once the
programming/connections are done, changes cannot be made. This situation
arises after an ASIP is fully developed and tested and an IC is desired but the time
and cost of full-custom IC is not.

6. SPP + Semi-Custom This device will execute a single program. Once

programming/connections are done the program will not change. This situation
may occur once the final development and testing is done and an IC is desired but
the time and cost of full-custom IC is not.

7. GPP + Full-Custom This device will execute a variety of programs. Each layer
has been optimized so that the device will yield excellent performance and power
consumption. This option is one of the most expensive and is desired when the
performance, size, and power trade offs are of greater concern then cost and
time. This situation may arise after final development and testing. Moreover, a
large quantity of ICs will be produced thereby reducing the NRE per unit.

8. ASIP + Full-Custom This device will execute a domain specific application well.
Each layer has been optimized so the device will yield excellent performance and
power consumption. This option is one of the most expensive and is desired when
the performance, size, and power trade offs are of greater concern then cost and
time. This situation may occur after final development and testing. Moreover, a
large quantity of ICs will be produced thereby reducing the NRE per unit.

9. SPP + Full-Custom This device will execute a single program. Each layer has
been optimized such that the device will yield excellent performance and power
consumption. This option is one of the most expensive and is desired when the
performance, size, and power trade offs are of greater concern then cost and
time. This situation may occur after final development and testing. Moreover, a
large quantity of ICs will be produced thereby reducing the NRE per unit.

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2. Compare the characteristics of Arduino and Raspberry Pi in

a neat tabular column[1].
2A)

Difference between Raspberry Pi and Arduino

Both the Raspberry Pi and the Arduino may look similar in terms of design, but they are

in fact very different devices with different purposes on what they can do.

1. Function of Raspberry Pi and Arduino

– Both the devices are cute little circuit boards which look almost identical and were

initially designed to be learning tools, but they are in fact very different from each other.

While Raspberry Pi is a full-fledged single board computer that is capable of doing

literally all computational tasks like your personal computer, an Arduino is merely a

microcontroller motherboard that can run one program at a time. Arduino is just a

single component of a computer.

2. Design of Raspberry Pi and Arduino

– Raspberry Pi is a fully-functional computer that runs an actual operating system in

Linux and it has all the functionalities of a computer. It has a dedicated processor,

graphics output through HDMI, USB ports, memory, and it connects wirelessly to the

Internet. It’s as good as a personal computer. Arduino, on the other hand, is a

microcontroller motherboard which is just a single component of the computer.

3. Use of Raspberry Pi and Arduino

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– Raspberry Pi is capable of anything from making a retro gaming console to creating a

game server and much more. Arduino is an open source prototyping platform ideal for

making DIY electronics projects like home automation system, controlling motors and

lights, Internet of Things projects, etc.

4. Hardware

– Being a fully functional computer, Raspberry Pi is just like a regular computer with

USB, storage and video. Arduino, on the other hand, is not a computer so no video, no

keyboard or mouse input, no storage, no USB, nothing. It’s just a microcontroller

designed to process information the easy way.

5. Operating System of Raspberry Pi and A rduino

– Raspberry Pi runs an actual operating system in Linux and is powerful enough to

function as a standard PC, whereas an Arduino doesn’t run an operating system.

SL Raspberry Pi Arduino

It is a mini computer with Raspbian Arduino is a microcontroller, which is a

1 OS.It can run multiple programs at a part of the computer. It runs only one

time. program again and again.

It is difficult to power using a battery Arduino can be powered using a battery

2
pack. pack.

It requires complex tasks like It is very simple to interface sensors and

3
installing libraries and software for other electronic components to Arduino.
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interfacing sensors and other

components

4 It is expensive It is available for low cost.

Raspberry Pi can be easily

Arduino requires external hardware to
connected to the internet using
5 connect to the internet and this hardware
Ethernet port and USB Wi-Fi
is addressed properly using code.
dongles.

Raspberry Pi did not have storage

6 on board. It provides an SD card Arduino can provide onboard storage.

port.

Raspberry Pi has 4 USB ports to Arduino has only one USB port to
7
connect different devices. connect to the computer.

The processor used is from ARM Processor used in Arduino is from AVR
8
family. family Atmega328P

This is a just plug and play device. If

This should be properly shutdown
power is connected it starts running the
9 otherwise there is a risk of files
program and if disconnected it simply
corruption and software problems.
stops.

The Recommended programming

10 language is python but C, C++, Arduino uses Arduino, C/C++.

Python, ruby are pre-installed.

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Raspberry Pi Arduino
It’s a fully fledged It’s a microcontroller motherboard
computer that can perform which is just a single component of
all tasks like a standard the computer. It’s not an actual
personal computer. computer.
It runs an actual operating It does not run an operating
system in Linux. system.
It has storage and video,
It has no keyboard and mouse
USB, keyboard and mouse
input, no storage and video,
input just like your
nothing.
personal computer.
It hails from the United
It was born in Italy.
Kingdom.
It runs one program at a time and
It is capable of running
there’s no interactivity unless
multiple programs at once.
created.
It’s faster than the Arduino It’s slower than Pi when it comes to
in terms of clock speed. clock speed.
It’s great for electronic
It’s ideal for beginners looking to
enthusiasts and hobbyists
make cool electronic projects.
alike.
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3. Compare the characteristics of 8051 and PIC16F. [ALU size,

RISC or CISC, clock speeds, number of instructions, inbuilt
peripherals like ADC or DAC, number of timers, interrupts,
RealTime clocks, on-chip RAM and ROM etc.]

3A)

Main Difference between 8051 and PIC Microcontrollers

8051 PIC
8-bit for standard core 8/16/32-bit
Bus width
PIC, UART, USART,
LIN, CAN, Ethernet, SPI,
Communication
UART, USART,SPI,I2C I2S
Protocols
12 Clock/instruction
cycle 4 Clock/instruction cycle
Speed

ROM, SRAM, FLASH SRAM, FLASH

Memory
2 Timers 3 Timers
Timers
Some feature of RISC
CLSC
ISA
Von Neumann
architecture Harvard architecture
Memory Architecture
Average Low
Power Consumption
PIC16,PIC17, PIC18,
8051 variants PIC24, PIC32
Families
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Vast Very Good

Community
NXP, Atmel, Silicon
Labs, Dallas, Cyprus,
Infineon, etc. Microchip Average
Manufacturer
Cost (as compared
to features provide) Very Low Average

Known for its Standard Cheap

Other Feature
PIC18fXX8, PIC16f88X,
Popular
AT89C51, P89v51, etc. PIC32MXX
Microcontrollers

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4. Describe the architectural features of FPGAs, ASICs and

CPLDs.

FPGA Architecture
The general FPGA architecture consists of three types of modules. They are I/O
blocks or Pads, Switch Matrix/ Interconnection Wires and Configurable logic
blocks (CLB). The basic FPGA architecture has two dimensional arrays of logic
blocks with a means for a user to arrange the interconnection between the logic
blocks. The functions of an FPGA architecture module are discussed below:
• CLB (Configurable Logic Block) includes digital logic, inputs, outputs. It
implements the user logic.
• Interconnects provide direction between the logic blocks to implement the
user logic.
• Depending on the logic, switch matrix provides switching between
interconnects.
• I/O Pads used for the outside world to communicate with different
applications.
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FPGA Architecture

Logic Block contains MUX (Multiplexer), D flip flop and LUT. LUT implements the
combinational logical functions; the MUX is used for selection logic, and D flip flop
stores the output of the LUT
The basic building block of the FPGA is the Look Up Table based function
generator. The number of inputs to the LUT vary from 3,4,6, and even 8 after
experiments. Now, we have adaptive LUTs that provides two outputs per single
LUT with the implementation of two function generators.

FPGA Logic Block

Xilinx Virtex-5 is the most popular FPGA, that contains a Look up Table (LUT)
which is connected with MUX, and a flip flop as discussed above. Present FPGA
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consists of about hundreds or thousands of configurable logic blocks. For

configuring the FPGA, Modelsim and Xilinx ISE softwares are used to generate a
bitstream file and for development.

Types of FPGAs Based on Applications

Field Programmable Gate Arrays are classified into three types based on
applications such as Low-end FPGAs, Mid-range FPGAs and high-end FPGAs.

Types of FPGAs

Low End FPGAs

These types of FPGAs are designed for low power consumption, low logic density
and low complexity per chip. Examples of low end FPGAs are Cyclone family from
Altera, Spartan family from Xilinx, fusion family from Microsemi and the Mach
XO/ICE40 from Lattice semiconductor.

Mid Range FPGAs

These types of FPGAs are the optimum solution between the low-end and high-
end FPGAs and these are developed as a balance between the performance and
the cost. Examples of Mid range FPGAs are Arria from Altera, Artix-7/Kintex-7
series from Xlinix, IGL002 from Microsemi and ECP3 and ECP5 series from Lattice
semiconductor.
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High End FPGAs

These types of FPGAs are developed for logic density and high performance.
Examples of High end FPGAs are a Stratix family from Altera, Virtex family from
Xilinx, Speedster 22i family from Achronix, and ProASIC3 family from Microsemi.

ASIC architecture
ASIC stands for Application Specific Integrated Circuit. As the name implies, ASICs
are application specific. They are designed for one sole purpose and they function
the same their whole operating life. For example, the CPU inside your phone is an
ASIC. It is meant to function as a CPU for its whole life. Its logic function cannot be
changed to anything else because its digital circuitry is made up of permanently
connected gates and flip-flops in silicon. The logic function of ASIC is specified in a
similar way as in the case of FPGAs, using hardware description languages such as
Verilog or VHDL. The difference in case of ASIC is that the resultant circuit is
permanently drawn into silicon whereas in FPGAs the circuit is made by
connecting a number of configurable blocks.

FPGA vs ASIC comparison summary

No. FPGA ASIC

1 Reconfigurable circuit. FPGAs can be Permanent circuitry. Once the

reconfigured with a different design. application specific circuit is taped-

They even have capability to reconfigure out into silicon, it cannot be changed.

a part of chip while remaining areas of The circuit will work same for its

chip are still working! This feature is

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No. FPGA ASIC

widely used in accelerated computing in complete operating life.

data centres.

2 Design is specified generally using Same as for FPGA. Design is

hardware description languages (HDL) specified using HDL such as Verilog,

such as VHDL or Verilog. VHDL etc.

3 Easier entry-barrier. One can get started Very high entry-barrier in terms of

with FPGA development for as low as cost, learning curve, liaising with

USD $30. semiconductor foundry etc. Starting

ASIC development from scratch can

cost well into millions of dollars.

4 Not suited for very high-volume mass Suited for very high-volume mass

production. production.

5 Less energy efficient, requires more Much more power efficient than

power for same function which ASIC can FPGAs. Power consumption of ASICs

can be very minutely controlled and

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No. FPGA ASIC

achieve at lower power. optimized.

6 Limited in operating frequency compared ASIC fabricated using the same

to ASIC of similar process node. The process node can run at much higher

routing and configurable logic eat up frequency than FPGAs since its

timing margin in FPGAs. circuit is optimized for its specific

function.

7 Analog designs are not possible with ASICs can have complete analog

FPGAs. Although FPGAs may contain circuitry, for example WiFi

specific analog hardware such as PLLs, transceiver, on the same die along

ADC etc, they are not much flexible to with microprocessor cores. This is the

create for example RF transceivers. advantage which FPGAs lack.

8 FPGAs are highly suited for applications ASICs are definitely not suited for

such as Radars, Cell Phone Base Stations application areas where the design

etc where the current design might need might need to be upgraded frequently

to be upgraded to use better algorithm or or once-in-a-while.

to a better design. In these applications,

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No. FPGA ASIC

the high-cost of FPGAs is not the

deciding factor. Instead, programmability

is the deciding factor.

9 Preferred for prototyping and validating a It is not recommended to prototype a

design or concept. Many ASICs are design using ASICs unless it has been

prototyped using FPGAs themselves! absolutely validated. Once the silicon

Major processor manufacturers has been taped out, almost nothing

themselves use FPGAs to validate their can be done to fix a design bug

System-on-Chips (SoCs). It is easier to (exceptions apply).

make sure design is working correctly as

intended using FPGA prototyping.

10 FPGA designers generally do not need to ASIC designers need to care for

care for back-end design. Everything is everything from RTL down to reset

handled by synthesis and routing tools tree, clock tree, physical layout and

which make sure the design works as routing, process node, manufacturing

described in the RTL code and meets constraints (DFM), testing constraints

timing. So, designers can focus into (DFT) etc. Generally, each of the
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No. FPGA ASIC

getting the RTL design done. mentioned area is handled by

different specialist person.

Complex programmable logic device

Some of the CPLD features are in common with PALs:

Non-volatile configuration memory: Unlike many FPGAs, an external

configuration ROM isn't required, and the CPLD can function immediately on
system start-up.

For many legacy CPLD devices, routing constrains most logic blocks to have input
and output signals connected to external pins, reducing opportunities for internal
state storage and deeply layered logic. This is usually not a factor for larger CPLDs
and newer CPLD product families.

Other features are in common with FPGAs:

Large number of gates available: CPLDs typically have the equivalent of thousands
to tens of thousands of logic gates, allowing implementation of moderately
complicated data processing devices. PALs typically have a few hundred gate
equivalents at most, while FPGAs typically range from tens of thousands to
several million.

Some provisions for logic are more flexible than sum-of-product expressions,
including complicated feedback paths between macro cells, and specialized logic
for implementing various commonly used functions, such as integer arithmetic.

The most noticeable difference between a large CPLD and a small FPGA is the
presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be
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used for "boot loader" functions, before handing over control to other devices not
having their own permanent program storage. A good example is where a CPLD is
used to load configuration data for an FPGA from non-volatile memory.

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5. Describe the architecture and special features of the

Qualcomm Snapdragon 855 Mobile Platform and Snapdragon
X50 5G modem.
Ans)
Snapdragon 855 is a high-performance 64-bit ARM LTE system on a
chip designed by Qualcomm and introduced in late 2018. Fabricated on
Samsung's 7nm process, the 855 features four Kryo 485 Silver high-efficiency
cores operating at 1.8 GHz along with three high-performance Kryo 485
Gold operating at 2.42 GHz and another higher-performance Kryo 485 Gold core
operating at 2.84 GHz. The Snapdragon 855 integrates the Adreno
640 GPU operation at ? MHz and features an X24 LTE modem supporting Cat
20 uplink and Cat 20 downlink. This chip supports up to 16 GiB of quad-channel
LPDDR4X-4266 memory.
The Snapdragon 855 can be paired with Qualcomm's X50 5G modem (an
external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6
GHz and mmWave, support.
Unprecedented wireless broadband speeds
Supporting up to 5 gigabits per second download speeds, the Snapdragon X50 5G
modem can provide a vastly more immediate connection between the user and the
cloud, opening up the possibilities of an entirely new generation of applications
and services.

mmWave with mobility

The Snapdragon X50 5G modem, paired with up to 4 QTM052 mmWave antenna
modules, supports advanced mobility features including beam forming, beam
steering and beam tracking which are engineered to improve mmWave signal
range and coverage, making mobile mmwave viable and ready for large-scale
commercialization.
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Designed from the ground up for mobile

The Snapdragon X50 5G modem is designed to support the next generation of
mobile devices. When paired with a Snapdragon processor with an integrated
Gigabit class LTE modem, the complete Snapdragon X50 5G platform can provide
multi-mode 4G/5G capability via dual connectivity. In fixed wireless applications,
the Snapdragon X50 5G modem can replace fiber-to-the-home (FTTH)
installations with wireless 5G connections.
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6. Describe the special features in the CC3200 Internet on

Chip processor.
Ans)

Created for the Internet of Things (IoT), the SimpleLink CC3200 device is a
wireless MCU that integrates a high-performance ARM Cortex-M4 MCU,
allowing customers to develop an entire application with a single IC. With on-chip
Wi-Fi, Internet, and robust security protocols, no prior WiFi experience is required
for faster development. The CC3200 device is a complete platform solution
including software, sample applications, tools, user and programming guides,
reference designs, and the TI E2E™ support community. The applications MCU
subsystem contains an industry-standard ARM Cortex-M4 core running at 80
MHz. The device includes a wide variety of peripherals, including a fast parallel
camera interface, I2S, SD/MMC, UART, SPI, I 2C, and four-channel ADC. The
CC3200 family includes flexible embedded RAM for code and data and ROM with
external serial flash bootloader and peripheral drivers. The Wi-Fi network
processor subsystem features a Wi-Fi Internet-on-a-Chip and contains an
additional dedicated ARM MCU that completely offloads the applications MCU.
This subsystem includes an 802.11 b/g/n radio, baseband, and MAC with a
powerful crypto engine for fast, secure Internet connections with 256-bit
encryption. The CC3200 device supports Station, Access Point, and Wi-Fi Direct
modes. The device also supports WPA2 personal and enterprise security and WPS
2.0. The Wi-Fi Internet-on-a-chip includes embedded TCP/IP and TLS/SSL stacks,
HTTP server, and multiple Internet protocols. The power-management subsystem
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includes integrated DC-DC converters supporting a wide range of supply voltages.

This subsystem enables low-power consumption modes, such as the hibernate with
RTC mode requiring less than 4 μA of current.

Applications • For Internet-of-Things applications, such as: – Cloud Connectivity –

Internet Gateway – Home Automation – Industrial Control – Home Appliances –
Smart Plug and Metering – Access Control – Wireless Audio – Security Systems –
IP Network Sensor Nodes

Features 1 • CC3200 SimpleLink Wi-Fi—Consists of Programming Interfaces

(APIs) Applications Microcontroller, Wi-Fi Network • 8 Simultaneous TCP or
UDP Sockets Processor, and Power-Management Subsystems • 2 Simultaneous
TLS and SSL Sockets • Wi-Fi CERTIFIED™ Chip – Powerful Crypto Engine for
Fast, Secure Wi-Fi • Applications Microcontroller Subsystem and Internet
Connections with 256-Bit AES – ARM® Cortex® -M4 Core at 80 MHz
Encryption for TLS and SSL Connections – Station, AP, and Wi-Fi Direct –
Embedded Memory ® Modes • RAM (Up to 256KB) – WPA2 Personal and
Enterprise Security • External Serial Flash Bootloader, and – SimpleLink
Connection Manager for Peripheral Drivers in ROM Autonomous and Fast Wi-Fi
Connections – 32-Channel Direct Memory Access (μDMA) – SmartConfig™
Technology, AP Mode, and WPS2 for Easy and Flexible Wi-Fi Provisioning –
Hardware Crypto Engine for Advanced Fast Security, – TX Power Including •
AES, DES, and 3DES • 18.0 dBm @ 1 DSSS • SHA2 and MD5 • 14.5 dBm @ 54
OFDM • CRC and Checksum – RX Sensitivity – 8-Bit Parallel Camera Interface •
–95.7 dBm @ 1 DSSS – 1 Multichannel Audio Serial Port (McASP) • –74.0 dBm
@ 54 OFDM Interface with Support for Two I2S Channels – Application
Throughput – 1 SD/MMC Interface • UDP: 16 Mbps – 2 Universal Asynchronous
Receivers and • TCP: 13 Mbps Transmitters (UARTs) • Power-Management
Subsystem – 1 Serial Peripheral Interface (SPI) – Integrated DC-DC Supports a
Wide Range of – 1 Inter-Integrated Circuit (I2C) Supply Voltage: – 4 General-
Purpose Timers with 16-Bit Pulse- • VBAT Wide-Voltage Mode: 2.1 to 3.6 V
Width Modulation (PWM) Mode • VIO is Always Tied with VBAT – 1 Watchdog
Timer • Preregulated 1.85-V Mode – 4-Channel 12-Bit Analog-to-Digital
Converters – Advanced Low-Power Modes (ADCs) • Hibernate: 4 µA – Up to 27
Individually Programmable, Multiplexed • Low-Power Deep Sleep (LPDS): 250
µA GPIO Pins • RX Traffic (MCU Active): 59 mA @ • Dedicated External SPI
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Interface for Serial Flash 54 OFDM • Wi-Fi Network Processor Subsystem • TX

Traffic (MCU Active): 229 mA @ – Featuring Wi-Fi Internet-On-a-Chip™ 54
OFDM, Maximum Power – Dedicated ARM MCU • Idle Connected (MCU in
LPDS): Completely Offloads Wi-Fi and Internet 825 µA @ DTIM = 1 Protocols
from the Application Microcontroller • Clock Source – Wi-Fi and Internet
Protocols in ROM – 40.0-MHz Crystal with Internal Oscillator – 802.11 b/g/n
Radio, Baseband, Medium Access – 32.768-kHz Crystal or External RTC Clock
Control (MAC), Wi-Fi Driver, and Supplicant • Package and Operating
Temperature – TCP/IP Stack – 0.5-mm Pitch, 64-Pin, 9-mm × 9-mm QFN •
Industry-Standard BSD Socket Application – Ambient Temperature Range: –40°C
to 85°C

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7. Describe the special features in NFE 3240 network

processor.
Ans)

NFE-3240 Features

• Up to 40 flow processing cores

• OpenFlow 1.3 support with 42 match fields
• OVS 2.0 acceleration
• Packet classification and filtering
• Stateful flow analysis and action processing for up to 8 million flows in hardware
• Hardware-based cryptography and PKI operations
• Extremely low latency
• I/O virtualization
• Packet timestamping with 11ns accuracy
• GPS time synchronization
• Dynamic load balancing to parallelize application performance
• Layer 2 switching
• Layer 3 routing
• Network address and port translation (NAPT)
• Full programming flexibility to support network or protocol changes
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• APIs controlling flow processing cores

SOME ADDAPTIVE DATA BRO

NFE-3240 Appliance Adapters NETWORK FLOW ENGINE APPLIANCE

ADAPTERS Accelerate Network and Security Aplications Netronome’s Flow
Engine family of appliance adapters (NFE-3240) are specifically designed to
improve the network performance of x86-based appliances and servers. Available
in 2-port 10GbE and 6-port 1GbE options, the NFE-3240 provides up to 20Gb/s of
line-rate programmable packet and flow processing per card, providing a 10X
performance increase over traditional NICs in real-world network and security
applications running on IA/x86 systems. The NFE-3240 enables the acceleration of
network and security applications by utilizing high-performance packet processing
delivered from 40 networking-optimized processor cores. The NFE-3240 utilizes
several techniques to dramatically improve network workloads, including packet
classification, stateful flow analysis and per flow match/action processing, Layer 2
switching, Layer 3 routing, IPsec VPN origination/termination, SSL inspection,
network address and port translation and dynamic load-balancing of flows across a
virtualized PCIe datapath to parallelize application processing. Benefits • Line-rate
flow processing, packet inspection and packet capture across all packet sizes •
Integrated security processing including 20Gb/s of line-rate cryptography and PKI
operations • Green computing through the industry’s highest BIPs (billion
instructions per second) per watt at 1,800 instructions/packet at 30 million pps
Features • High-performance network flow processing powered by the NFP-3240
(40 MEs @ up to 1.4 GHz) • Packet classification for up to 64,000 rules • Stateful
flow analysis and action processing for up to 8 million flows in hardware • Flexible
interface options including 2x10GbE and 6x1GbE • High-speed PCIe Gen2
interface with 8 lanes offering up to 40Gb/s of bandwidth between the NFE and the
host x86 system