Special Session 1: In-Memory Processing for Future Electronics GLSVLSI ’19, May 9–11, 2019, Tysons Corner, VA,
LSVLSI ’19, May 9–11, 2019, Tysons Corner, VA, USA.
Digital and Analog-Mixed-Signal In-Memory Processing in
CMOS SRAM
Akhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Mustafa Fayez Ali, and Kaushik Roy
School of Electrical and Computer Engineering, Purdue University
West Lafayette, IN, USA
{jaiswal,agrawa64,ichakra,ali102,kaushik}@purdue.edu
ACM Reference Format:
Akhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Mustafa Fayez Ali,
and Kaushik Roy . 2019. Digital and Analog-Mixed-Signal In-Memory Pro-
cessing in CMOS SRAM . In Great Lakes Symposium on VLSI 2019 (GLSVLSI
’19), May 9–11, 2019, Tysons Corner, VA, USA. ACM, New York, NY, USA,
1 page. https://doi.org/10.1145/3299874.3319449
1 INTRODUCTION
Historically, Moore’s Law, has been the key driving force for the
ever increasing compute power on silicon chips. Architecturally, a
key factor fueling the improvement in computing efficiency is due
to the availability of large on-chip memory storage in form of SRAM
arrays as a result of shrinking transistor sizes. The historic trend of
smaller transistors and hence larger on-chip memories is slowing
down recently. In sharp contrast to this slowdown, the demand for
high throughput computations and associated energy-efficiency
has escalated considerably in recent times. Researchers are in active
pursuit of exploring alternate means to improve the computation
throughput while also lowering the required energy consumption.
‘In-Memory computing’ has emerged as a promising candidate to
achieve both increased throughput along with decrease in energy
consumption. SRAM based in-memory computations are of special
interest due to the pervasive presence of large SRAM sub-arrays in
state-of-the-art processors. One could, therefore, think of these in-
memory enabled SRAM arrays as on-chip compute engines, thereby,
exposing the end application to massive levels of parallelism.
2 SRAM BASED IN-MEMORY COMPUTING
Several proposals achieving various levels of compute parallelism
within SRAM cells have been presented in the literature in recent
times [1]-[8]. Interestingly, both digital [1]-[2] as well as analog-
mixed-signal approaches [3]-[8] have been explored extensively.
In general, digital approaches lead to accurate computations at the
cost of reduced compute throughput. On the other hand, analog
approaches lead to higher levels of data parallelism at the cost of
approximate computations due to the inherent nature of analog-
processing. Few representative strategies geared toward SRAM
based in-memory computations are as follows:
(1) Digital Bulk-Bit-wise Computations: The generic approach
toward bulk-bit-wise operations is to enable two memory
Permission to make digital or hard copies of part or all of this work for personal or
classroom use is granted without fee provided that copies are not made or distributed
for profit or commercial advantage and that copies bear this notice and the full citation
on the first page. Copyrights for third-party components of this work must be honored.
For all other uses, contact the owner/author(s).
GLSVLSI ’19, May 9–11, 2019, Tysons Corner, VA, USA
© 2019 Copyright held by the owner/author(s).
ACM ISBN 978-1-4503-6252-8/19/05.
https://doi.org/10.1145/3299874.3319449
371
rows, simultaneously, and read out a desired Boolean func-
tion of the constituent words through modified sensing cir-
cuits [1]-[2].
(2) Analog-Mixed-Signal Binary Dot-Products: Binary dot
products comprise of bit-wise XNOR followed by population-
count (pop-count: counting the number of ‘1’s’). The usual
approach here is to enable bulk-bit-wise operation and gen-
erate an analog voltage that is proportional to the pop-count
in the resultant bit-stream. By sensing the analog voltage
one can estimate the number of ‘1’s’ thereby accomplishing
binary dot product operation [5]-[6].
(3) Analog-Mixed-Signal Multi-bit Dot Products: Multi-bit
dot products require analog element-wise multiplication of
two vectors followed by summation of the elements of the
resulting vector. This summation of multiplications can be
accomplished in 8T SRAM cells through current-mode com-
putations wherein input vector voltages can be multiplied by
effective conductance of the transistors through Ohm’s Law
and the resulting currents can be summed up in accordance
to Kirchoff’s Current Law [8].
Finally, due to the inherent approximate nature of analog pro-
cessing, analog-mixed-signal schemes are suitable only for class of
error-resilient applications as in machine learning. In contrast, digi-
tal in-memory computing can cater to a wider class of applications
including both error-resilient as well as those that require accurate
computations.
3 CONCLUSION
In this paper, we have highlighted three representative approaches
with respect to in-memory computing in SRAM arrays ranging
from strictly digital simple computations as in bulk bit-wise op-
erations to massively parallel analog-mixed-signal computations
involving accelerated multi-bit dot products estimations. It is im-
portant to note that the level of parallelism, the complexity of the
required peripheral circuits and the approximation in computa-
tions increases when moving from digital to analog-mixed-signal
in-memory computations.
ACKNOWLEDGMENT
C-BRIC, one of six centers in JUMP, sponsored by SRC, DARPA,
NSF, Intel Corporation and Vannevar Bush Fellowship.
REFERENCES
[1] S. Jeloka, et. al. JSSCC, 2018. [2] A. Aggrawal et. al. TCAS-I, 2018.
[3] S.K. Gonugondla, et. al. ISSCC, 2018. [4] J. Zhang et. al. JSSCC,
2017. [5] A. Biswas, et. al. ISSCC, 2018. [6] A. Agrawal et. al. arxiv,
2018. [7] Z. Jiang et. al. VLSI, 2018. [8] A. Jaiswal, et. al. arxiv, 2018.