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Synchronous Counters:

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FACULTY OF COMPUTER SCIENCE & INFORMATION SYSTEM
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Synchronous Counter Design FF Excitation Table

About creating Next State table

•  JK Flip-Flop

•  Step 1 •  Step 4
Describe a general Create flip-flop
excitation table
sequential circuit in transition table.
terms of its basic parts
and its input and •  Step 5
outputs. Use K-maps to derive ≡
the logic equations.
•  Step 2
Develop state diagram •  Step 6
Implement counter 0 1
•  Step 3 implementation
Create next state table
(Refer to JK FF truth table
in module 7: page 225) (J-K ff state diagram)

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D flip flop T flip flop

state diagram state diagram
Exercise 8b.1: Exercise 8b.2:

0 1
Construct the 0 1 Construct the
excitation table excitation table
for D flip-flop for T flip-flop

(using its state (using its state

diagram) diagram)

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T flip flop
state diagram Note:
Exercise 8b.2:
Summary These excitation tables will
1 be used while filling in the
Construct the 0 Excitation tables of flip-flops: flip-flop transition table in
excitation table STEP 4 of designing
for T flip-flop synchronous counter.

(using its state

diagram)

J-K flip-flop D flip-flop T flip-flop

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Design 2-bit Synchronous Counter:

J-K Flip-flop Note:
While filling in the
•  Step 1: flip-flop transition
To design 2-bit synchronous counter using JK FF. There is no table, refer to the
input or output element in this design. excitation table.

•  Step 4:
•  Step 2: Draw state diagram •  Step 3: Create next state table
Draw flip-flop transition table
FF1 FF0
00 Present State Next State Present State Next State JK Transition
Q1n Q0n Q1n+1 Q0n+1 Q1n Q0n Q1n+1 Q0n+1 J1 K1 J0 K0
11 01 0 0 0 1 0 0 0 1 0 X 1 X
0 1 1 0 0 1 1 0 1 X X 1
1 0 1 1 1 0 1 1 X 0 1 X
10
1 1 0 0 1 1 0 0 X 1 X 1

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•  Step 6: Implement counter implementation

•  Step 5: J0 FF0 FF1

J1 Q0
Use K-maps to Q0
Q1 0 1 0 1 J0 = 1 J1 = Q0
derive the logic Q1
equations 0 0 1 0 1 X
K0 = 1 K1 = Q0
1 X X 1 1 X
(for present state
only).
J1 = Q0 J0 = 1
K1 Q0 K0 Q0
Q1 0 1 Q1 0 1
0 X X 0 X 1
1 0 1 1 X 1
•  Q0 toggle at positive edge (CLK1, CLK2, CLK3, CLK4)
K1 = Q0 K0 = 1 •  Q1 toggle when Q0=1 at positive edge (CLK2, CLK4)

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Exercise 8b.3: Design 2-bit synchronous counter that using T flip-flop. Exercise 8b.4: Design 2-bit synchronous counter that using D flip-flop.
Show all steps clearly. Show all steps clearly.

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Note:
While filling in
Design 3-bit Synchronous Counter: the flip-flop
transition table,
J-K Flip-flop refer to the
excitation table.

•  Step 2: State diagram •  Step 3: Next State table •  Step 4:

FF transition table FF2 FF1 FF0
Present State Next State
Present State Next State JK Transition Table
Q2 Q1 Q0 Q2+ Q1+ Q0+
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
0 0 0 0 0 1
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0
1 1 1 0 0 0 X 1 X 1 X 1
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(Module page: 256) Q1

Q0
•  Step 6:
•  Step 5: The implementation of 3-bit synchronous counter
Create K-map to determine the Boolean expression
FF0 FF1 FF2
Q1Q0 Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10 J0 = 1 J1 = Q0 J2 = Q1Q0
0 0 1 X X 0 1 X X 1
0 0 0 1 0 K0 = 1 K1 = Q0 K2 = Q1Q0
1 X X X X 1 0 1 X X 1 1 X X 1

J2 = Q1Q0 J1 = J0 =
Q1Q0 Q1Q0 Q1Q0
00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 0 0
1 1 1

K2 = K1 = K0 =
**Fill in the K-maps 17 18

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Exercise 8b.5: Design 3-bit synchronous counter that using D flip-flop.

Show all steps clearly.

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Exercise 8b.6: Design 4-bit synchronous counter that using J-K flip-flop Exercise 8b.7: Design 3-bit synchronous counter that using J-K flip-flop
with negative edge triggered. Show all steps clearly. based on the state diagram below. Show all steps clearly.

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2-bit Down Synchronous Counter:

D Flip-flop •  Step 5: K-Map.
•  Step 1: •  Step 4:
To design 2-bit down synchronous counter using D FF. There is Draw flip-flop transition table. For D FF, D Q0 0 1
no input or output element in this design. input is the same as the next state values. Q1
0 1 0
•  Step 2: Draw state diagram •  Step 3: Create next state table 1 1 0
Present State Next State D Transition
Q1n Q0n Q1n+1 Q0n+1 D1 D0 D0 = Q0
00 Present State Next State 0 0 1 1 1 1
Q1n Q0n Q1n+1 Q0n+1 0 1 0 0 0 0 Q0
11 0 0 1 1 0 1
01 1 0 0 1 0 1 Q1
0 1 0 0 1 1 1 0 1 0 0 1 0

1 0 0 1 1 0 1
10
1 1 1 0
D1 = Q1Q0 + Q1Q0
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2-bit UP/DOWN Synchronous Counter:

D Flip-flop
Exercise 8b.8: Draw the circuit for of 2-bit down synchronous counter •  Step 1:
using D FF with D1 = Q1Q0 + Q1Q0 and D0 = Q0 To design 2-bit up down synchronous counter using D FF based
on input X. When X X=0
= 0, 
it isCounter
up counter
UP and down
X=1 when X = 1.DOWN
 Counter
(Refer previous example: module page 259)

•  Step 2: •  Step 3: Create next state table

Given the state diagram.

00 0
0

Count up
1 1
11 01
1 1

Count down
0 10 0

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(Module page: 149)

•  Step 5: •  Step 5:
•  Step 4: Implement the circuit. •  Step 4: Implement the circuit.
D FF transition table and determine Q1Q0 D FF transition table and determine Q1Q0
Boolean expression. X
00 01 11 10 Boolean expression. X
00 01 11 10
0 0 0 1 0 1
1 1 1 0 1 0

D1 = D1 = X ⊕ Q1⊕ Q0
Q1Q0 Q1Q0
X 00 01 11 10 X 00 01 11 10
0 0 1 0 0 1
1 1 1 0 0 1

D0 = D0 = Q0
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Counter for Arbitrary Sequences

Exercise 8b.9: Draw the circuit for of 2-bit up-down synchronous counter •  Design the counter base on the given state diagram using T FF.
using D FF with D1 = X ⊕ Q1⊕ Q0 and D0 = Q0
(Refer previous example: module page 261)

•  The counter is 3-bit counter

•  The total number state = 23 = 8

•  Only 4 state (1, 2, 5, 7)

à Valid State

•  Other states (0, 3, 4, 6)

à Invalid State
(never occur /don’t care)

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•  State table and T ff transition table.

•  State table and T ff transition table. FF2 FF1 FF0
Present State Next State T FF
Present State Next State T FF
Q2n Q1n Q0n Q2n+1 Q1n+1 Q0n+1 T2 T1 T0
Q2n Q1n Q0n Q2n+1 Q1n+1 Q0n+1 T2 T1 T0
0 0 0 X X X X X X
0 0 0 X X X X X X
0 0 1 0 1 0 0 1 1
0 0 1 0 1 0 0 1 1
0 1 0
0 1 0 1 0 1 1 1 1
0 1 1
0 1 1 X X X X X X
1 0 0
1 0 0 X X X X X X
1 0 1
1 0 1 1 1 1 0 1 0
1 1 0
1 1 0 X X X X X X
1 1 1
1 1 1 0 0 1 1 1 0
•  Derive the Boolean expression and draw the circuit diagram.
**Fill in the next state and T FF transition column •  Derive the Boolean expression and draw the circuit diagram.
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Exercise 8b.10: Derive the Boolean expression and draw the circuit Exercise 8b.11: Design a counter with the irregular binary count
diagram from the previous example. sequence shown in the state diagram below using
J-K FF.

33 Resource: Floyd, Digital Fundamentals, 10th Edition, 2009. 34

**Fill in the
Synchronous BCD Decade Counter Present State Next State T FF Transition T0 column
Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+ T3 T2 T1 T0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 1 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1 0 0 0
0 0 1 1 0 1 0 0 0 1 1

•  Synchronous decade 0 0 1 0 0 0 1 0 1 0 0 0
9 1 0 1 0 1 0 1 1 0 0 0 1
counter counts from 0 to 9
0 1 1 0 0 1 1 1 0 0 0
and then recycles to 0
again. 8 2
0 1 1 1 1 0 0 0 1 1 1

1 0 0 0 1 0 0 1 0 0 0
•  4 FF is required and the 1 0 0 1 0 0 0 0 1 0 0
unused states ie 10 to 15 7 1 0 1 0 X X X X X X X
are taken as don’t care 3 1 0 1 1 X X X X X X X

terms. 6 1 1 0 0 X X X X X X X
4 1 1 0 1 X X X X X X X
5 1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X

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**Fill in the K-maps

Q1Q0 Q1Q0
Q3Q2 00 01 11 10 Q3Q2 00 01 11 10
00 00
Self-Test:
01 01
11 11
Fill in the k-map
to simplify the 10 10
equations. Cascaded Counter
T3 = T2 =
Q1Q0 Q1Q0
Q3Q2 00 01 11 10 Q3Q2 00 01 11 10
00 00
01 01
11 11
10 10

T1 = T0 =
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Recap: Modulus Cascaded Counter

•  Counter can be connected to achieve higher modulus operation.

•  The modulus à number of unique states through •  Cascading means that the last-stage output of one counter drives
which the counter will sequence. the input of the next counter.
•  Maximum possible number of states = 2N, N is the •  Example: Two counters, modulus-4 and modulus-8 connected in
number of flip-flops in the counter. cascade, can achieve count until 32 CLK (modulus-32). (i.e 4 x 8)
•  Example : Modulus 8 = 23 (Need 3 flip flops)
•  Counter can be designed to have less number of
states in their sequence à Truncated sequence.
•  One common modulus for counters à ten
(Modulus 10).
•  It called BCD decade counters (as
explained in previous slides).

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Cascaded Counter: Cascaded Counter:

Modulus-100 Counter Modulus-1000 Counter
•  Three cascaded decade counters forming a divide-by-1000
•  Modulus-100 counter using 2 cascaded decade counters. frequency divider.
•  This counter can be viewed as a frequency divider.
•  It divides the input clock frequency by 100.

(Total MOD = 10 x 10 = 100)
Basis clock frequency of 1 MHz and you wish to obtain Total MOD = 10 x 10 x 10
100kHz, 10Hz, and 1kHz, a series of cascaded = 100
decade counters can be used. If 1 MHz signal is
divided by 10, the output is 100kHz. Then if the 100
kHz signal is divided by 10, the output is 10kHz.
Further division by 10 gives the 1 kHz frequency.

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Analysis of Sequential Circuits

•  Behavior of a sequential circuit is determined from the inputs, the

outputs and the states of its flip-flops.
•  Both the output and the next state are a function of the inputs and
the present state.

Analysis of Sequential Circuits

3
1

2
1
4

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•  Step 1:
•  Step 3:
Start with the logic schematic from which we can derive excitation
Once we have our output and next-state equations, we can
equations for each flip-flop input.
generate the next-state and output tables as well as state
diagrams.
•  Step 2:
To obtain next-state equations, we insert the excitation equations
•  Step 4:
into the characteristic equations. The output equations can be
When we reach this stage, we use either the table or the state
derived from the schematic:
diagram to develop a timing diagram which can be verified
through simulation.

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Analysis of Sequential Circuits:

Modulo-4 Counter
Example:
•  Step 1: Boolean expressions for the inputs of each flip-flops in
Derive the state table the schematic.
and state diagram for the FF0
sequential circuit below. D0 = Cnt ⊕ Q0 = Cnt • Q0 + Cnt • Q0
D1 = Cnt • Q1 + Cnt • Q1 • Q0 + Cnt • Q1 • Q0

•  Step 2: Derive the next-state equations by converting these

excitation equations into flip-flop characteristic equations. In
FF1 the case of D flip-flops, Q+ = D.

Q0 + = D0 = Cnt ⊕ Q0 = Cnt • Q0 + Cnt • Q0

Q1+ = D1 = Cnt • Q1 + Cnt • Q1 • Q0 + Cnt • Q1 • Q0

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Q0 + = D0 = Cnt ⊕ Q0 = Cnt • Q0 + Cnt • Q0 •  Step 4: The state diagram is generated directly from the next-
state table. Next get the timing diagram
Q1+ = D1 = Cnt • Q1 + Cnt • Q1 • Q0 + Cnt • Q1 • Q0

•  Step 3: Input, Present State Next State

Construct the Cnt Q1 Q0 Q1+ = D1 Q0+ = D0
next-state table. 0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 1 1
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 0

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Analysis of Sequential Circuits:

JK Circuit Analysis
•  Sequential circuit
with two JK flip-
flops. There is
one input, X, and
one output, Z.

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•  Remember that there is one input X, one output Z, and two flip-
flops Q1Q0.
•  The present state Q1Q0 and the input will determine the next
state and the output.
•  From the diagram, Z = Q1Q0X
Input, Present State Next State JK FF Transition Output,
Input, Present State Next State Output, X Q1 Q0 Q1+ Q0+ J1 K1 J0 K0 Z
X Q1 Q0 Q1+ Q0+ Z 0 0 0 0 0 0 1 0
0 0 0 0 0 0 1 1 1 0
0 0 1 0 0 1 0 0 0 0
0 1 0 0 0 1 1 1 1 0
0 1 1 0 1 0 0 0 1 0
1 0 0 1 0 1 0 1 0
1 0 1 1 1 0 0 1 0
1 1 0 1 1 1 0 1 1
**Fill in the Z
1 1 1
**Fill in the JK FF transition column 54
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Exercise 8b.12: Draw the state diagram for the example in previous
slide.

Input, Present State Next State JK FF Transition Output,

X Q1 Q0 Q1+ Q0+ J1 K1 J0 K0 Z
0 0 0 0 0 0 0 1 0
0 0 1 1 1 1 0 1 0
0 1 0 1 0 0 1 1 0
0 1 1 0 1 1 1 1 0
1 0 0 0 0 1 1 0 0
1 0 1 0 0 1 1 0 0
1 1 0 0 0 1 1 0 0
1 1 1 0 0 1 1 0 1
**Fill in the next state column 55
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Exercise 8b.13: Analysis for the following sequential circuit.

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