TASK-1

Develop verification environment using system verilog for any one

Digital system
Aim: To develop verification environment using system verilog for binary to gray
and gray to binary converter and shift register .

Tools Used:
Cadence Digital Labs.

Binary to gray
Theory:
The logical circuit which converts the binary code to equivalent gray code is
known as binary to gray code converter. An n-bit gray code can be obtained by
reflecting an n-1 bit code about an axis after 2n-1 rows and putting the MSB (Most
Significant Bit) of 0 above the axis and the MSB of 1 below the axis. Reflection of
Gray codes is shown below.
The 4 bit binary to gray code conversion table is given below:

The gray code to binary converter circuit is shown below:

Gray Code to Binary Conversion
Gray code to binary conversion is again a very simple and easy process.
Following steps can make your idea clear on this type of conversions.
1. The MSB of the binary number will be equal to the MSB of the given gray
code.
2. Now if the second gray bit is 0, then the second binary bit will be the same
as the previous or the first bit. If the gray bit is 1 the second binary bit will
alter. If it was 1 it will be 0 and if it was 0 it will be 1.
3. This step is continued for all the bits to do Gray code to binary conversion.

One example given below will make your idea clear.

Gray Code to Binary Conversion Example
The MSB of the binary will be 0 as the MSB of gray is 0. Now move to the next
gray bit. As it is 1 the previous binary bit will alter i.e it will be 1, thus the second
binary bit will be 1. Next look at the third bit of the gray code. It is again 1 thus the
previous bit i.e the second binary bit will again alter and the third bit of the binary
number will be 0. Now, the 4th bit of the given gray is 0 so the previous binary bit
will be unchanged, i.e 4th binary bit will be 0. Now again the 5th grey bit is 1 thus
the previous binary bit will alter, it will be 1 from 0. Therefore the equivalent
binary number in case of gray code to the binary conversion will be (01001).

Schematic:

Verilog code:
module binarytogray(g,b);
input [3:0]b;
output [3:0]g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];
endmodule
Testbench:

module binarytogray_tb;

/// Inputs
reg [3:0] b;

// Outputs
wire [3:0] g;

// Instantiate the Unit Under Test (UUT)

binarytogray uut (
.g(g),
.b(b)
);

initial begin
// Initialize Inputs
b = 0000;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 0001;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 0010;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

 // Initialize Inputs
b = 0011;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 0100;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 0101;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 0110;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 1000;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 1001;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here
// Initialize Inputs
b = 1010;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 1011;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 1100;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 1101;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 1110;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
b = 1111;
 // Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end

endmodule

Waveform:

Fig: Waveform of binary to gray

.g file

create_clock -name clk -period 10 -waveform {0 5}

set_input_delay -max 4.85 -clock clk [get_ports "b[3]"]
set_input_delay -max 4.85 -clock clk [get_ports "b[2]"]
set_input_delay -max 4.85 -clock clk [get_ports "b[1]"]
set_input_delay -max 4.85 -clock clk [get_ports "b[0]"]
set_output_delay -max 4.85 -clock clk [get_ports "g[3]"]
set_output_delay -max 4.85 -clock clk [get_ports "g[2]"]
set_output_delay -max 4.85 -clock clk [get_ports "g[1]"]
set_output_delay -max 4.85 -clock clk [get_ports "g[0]"]
Gray to binary converter

Theory:

This gray to binary conversion method also uses the working concept of EX-OR
logic gate among the bits of gray as well as binary bits. The following example
with step by step procedure may help to know the conversion concept of gray code
to binary code.

gray to Binary Code Conversion logic Circuit

To change gray to binary code, take down the MSB digit of the gray code number,
as the primary digit or the MSB of the gray code is similar to the binary digit.

To get the next straight binary bit, it uses the XOR operation among the primary
bit or MSB bit of binary to the next bit of the gray code.

Similarly, to get the third straight binary bit, it uses the XOR operation among the
second bit or MSB bit of binary to the third MSD bit of the gray code and so on.

Example of Gray to Binary Code Converter

Let assume the Gray Code digits g3, g2, g1, g0 whereas the particular Binary code
digits are bo, b1, b2, b3 can be attained based on the following concept.
 Gray
Code to Binary Conversion Concept

From the above operation, finally we can get the binary values like b3 = g3, b2 =
b3 XOR g2, b1= b2 XOR g1, b0 = b1 XOR g0.

Gray to Binary Code Conversion Example

For example take the gray value g3, g2, g1, g0 = 0011 and find the binary code b3,
b2, b1, b0 based on the above concept

b3=g3=0
b2 = b3 XOR g2 = 0 XOR 0 =0
b1= b2 XOR g1= 0 XOR 1 = 1
b0= b1 XOR g0= 1 XOR 1 = 0
The final binary code for the value of gray 0011 is 0010
Gray to Binary Code Converter Table
Decimal Number Gray Code
Binary Code
0 0000 0000

1 0001 0001

2 0010 0011

3 0010 0011

4 0110 0100

5 0111 0101

6 0101 0110

7 0100 0111

8 1100 1000

9 1101 1001

10 1111 1010

11 1110 1011

12 1010 1100

13 1011 1101

14 1001 1110

15 1000 1111
Schematic:

Verilog code:
module graytobinary(b,g);
input [3:0]g;
output [3:0]b;
assign b[3]=g[3];
assign b[2]=g[3]^g[2];
assign b[1]=g[3]^g[2]^g[1];
assign b[0]=g[3]^g[2]^g[1]^g[0];
endmodule

Testbench:

module graytobinary_tb;

// Inputs
reg [3:0] g;

// Outputs
wire [3:0] b;

// Instantiate the Unit Under Test (UUT)

graytobinary uut (
.b(b),
 .g(g)
);

initial begin
// Initialize Inputs
g = 4'b0000;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
g = 4'b0001;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
g = 4'b0010;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b0011;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b0100;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b0101;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b0110;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b0111;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b1000;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b1001;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b1010;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b1011;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b1100;
 // Wait 100 ns for global reset to finish
#100;

// Add stimulus here // Initialize Inputs

g = 4'b1101;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b1110;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here // Initialize Inputs

g = 4'b1111;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule
Waveform:

Fig: Waveform of gray to binary

.g file

create_clock -name clk -period 10 -waveform {0 5}

set_input_delay -max 4.85 -clock clk [get_ports "g[3]"]
set_input_delay -max 4.85 -clock clk [get_ports "g[2]"]
set_input_delay -max 4.85 -clock clk [get_ports "g[1]"]
set_input_delay -max 4.85 -clock clk [get_ports "g[0]"]
set_output_delay -max 4.85 -clock clk [get_ports "b[3]"]
set_output_delay -max 4.85 -clock clk [get_ports "b[2]"]
set_output_delay -max 4.85 -clock clk [get_ports "b[1]"]
set_output_delay -max 4.85 -clock clk [get_ports "bc[0]"]

SERIAL IN PARALLEL OUT SHIFT REGISTER

Theory: The Shift Register is another type of sequential logic circuit that
can be used for the storage or the transfer of binary data. This sequential
device loads the data present on its inputs and then moves or “shifts” it to
its output once every clock cycle, hence the name Shift Register.Serial-in
to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a
time, with the stored data being available at the output in parallel form.
Schematic:

Fig:Schematic of serial in parallel out

Verilog:
module sipo(a,clk,rst,q);
input clk,rst;
input a;
output [3:0] q;
wire [3:0]q;
reg [3:0] temp;
always @ (posedge rst or posedge clk)
begin
if(rst==1'b1)
temp<=4'b0000;
else
begin
temp<=temp<<1'b1;
temp[0]<=a;
end
end
assign q=temp;
endmodule

Testbench:
module tb_sipo;
reg rst,clk,a;
wire [3:0]q;
sipo uut(.clk(clk),.rst(rst),.a(a),.q(q));
initial
clk=1'b0;
always #10 clk=~clk;
initial begin
rst=1'b1; a=1'b1;
#500 rst=1'b0;
#100 a=1'b0;
#100 a=1'b1;
#100 a=1'b0;
#100 a=1'b0;
#100 a=1'b1;
#100 a=1'b0;
end
initial
#100 $stop;
endmodule
Waveform:

Fig: Waveform of serial in parallel out

.g file:
create_clock -name clock -period file -waveform {0 5}
set -input -delay 1.0 -clock clk [get _ports "a"]
set -input -delay 1.0 -clock clk [get _ports "clk"]
set -input -delay 1.0 -clock clk [get _ports "rst"]
set -output -delay 1.0 -clock clk [get _ports "q[0]"]
set -output -delay 1.0 -clock clk [get _ports "q[1]"]
set -output -delay 1.0 -clock clk [get _ports "q[2]"]
set -output -delay 1.0 -clock clk [get _ports "q[3]"]

PARALLEL IN SERIAL OUT

Theory:
A shift register basically consists of several single bit “D-Type
Data Latches”, one for each data bit, either a logic “0” or a “1”, connected
together in a serial type daisy-chain arrangement so that the output from
one data latch becomes the input of the next latch and so on. Shift
Registers are used for data storage or for the movement of data and are
therefore commonly used inside calculators or computers to store data
such as two binary numbers before they are added together, or to convert
the data from either a serial to parallel or parallel to serial format. The
individual data latches that make up a single shift register are all driven by
a common clock ( Clk ) signal making them synchronous devices.
Schematic:

Fig: Schematic of parallel in serial out

Verilog code:
module piso(clk,rst,a,q);
input clk,rst;
input [3:0] a;
output q;
reg q;
reg [3:0] temp;
always@ (posedge clk or posedge rst)
begin
if (rst==1'b1)
begin q<=1'b0;
temp<=a;
end
else begin
q<=temp[0];
temp<=temp>>1'b1;
end
end
endmodule
Testbench:
module tb_piso;
reg clk,rst;
reg [3:0] a;
wire q;
piso uut(.clk(clk),.rst(rst),.a(a),.q(q));
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
rst=1'b1;
a=4'b1101;
#300 rst=1'b0;
#200 rst=1'b1;
#200 rst=1'b0;
end
initial #100 $stop;
endmodule
Waveform:

Fig:Waveform of parallel in serial out

.g file:
create_clock -name clk -period 15 -waveform {0 1}
set_input_delay -max 1.0 -clock clk [get_ports "a[0]"]
set_input_delay -max 1.0 -clock clk [get_ports "a[1]"]
set_input_delay -max 1.0 -clock clk [get_ports "a[2]"]
set_input_delay -max 1.0 -clock clk [get_ports "a[3]"]
set_input_delay -max 1.0 -clock clk [get_ports "rst"]
set_input_delay -max 1.0 -clock clk [get_ports "clk"]
set_output_delay -max 1.0 -clock clk [get_ports "q"]

Fig: area and power analysis of parallel in serial out

Fig:area and power analysis of serial in parallel out

Results: System verilog for binary to gray and gray to binary converter and shift
registers are verified.