FPGA Based Solution For Ethernet Controller As

Alternative For TCP/UDP Software Stack

Anshuman Choudhary, Deepika Porwal, Abhishek Parmar
Laser Science and Technology Centre Defence Research and Development Organisation
Delhi, India
anshuman91choudhary@gmail.com, deepikaporwal@lastec.drdo.in, abhishekparmar@lastec.drdo.in

Abstract— This paper presents an Ethernet based embedded

system solution by interfacing FPGA with W5500 for
implementation of UDP/IP stack. Ethernet based embedded
system is required in variety of applications for transmitting
high speed data over long distances. FPGA is a potent solution
for developing customized Ethernet based embedded system.
FPGA based ethernet solution either utilizes high cost
commercially available IP cores or requires TCP/IP core
development with high level of HDL expertise. Commercially
available external ethernet controller like W5500 chip with
inbuilt TCP/IP protocol offers simple, low cost and higher data
rate transmission with FPGA based solution for embedded
systems. This approach reduces coding complexity and the
development cost and time. This design was implemented in
XC7Z020 FPGA device and evaluated for data transmission
rate up to 32 MBPS for data packet size of 1 KB using UDP
Protocol using W5500 external ethernet controller.
Fig.1. Block Diagram
Keywords— FPGA, VHDL, SPI, UDP, socket registers
II. INTERFACE
I. INTRODUCTION
In recent years, demand for transferring data in form of A. SPI
text, video and audio over long distances at high speed has W5500 communicates with FPGA board through SPI
increased tremendously. In laboratory or industry interface using SCLK (Serial Clock), CS (Chip Select),
experimental data can be transmitted through UART on MISO (Master In Slave Out) and MOSI (Master Out Slave
terminal PC. UART can transfer data over short distances at In) signals. FPGA acts as master and W5500 acts as slave.
low speed in the order of few Kilohertz. If we want to send VHDL based programming to configure socket registers is
data at very high speed over long distances then we need to done in FPGA. FPGA board used in the design is Xilinx
choose other alternate approach. In this design we have used Zed board with fundamental clock frequency of 100MHz.
Wiznet's W5500 Ethernet controller which has inbuilt When SS (slave select/chip select) is low then SPI [5]
hardwired TCP/IP core that provides easier Ethernet transmission begins and master sends command through
connection to embedded system [1-3]. W5500 configuration MOSI signal and slave responds by sending MISO signal. In
registers programming is done in FPGA using VHDL and Figure 2 four bytes of data are sent when SS goes low.
FPGA is interfaced with W5500 through SPI. Connection Simultaneously MISO from slave responds to MOSI when
between W5500 and terminal PC is established through SS goes low. This snapshot shows the interfacing signals
UDP interface. W5500 has TCP/IP stack, 10/100 Ethernet between FPGA and W5500 on Mixed Signal Oscilloscope.
MAC and Physical layer that enables users to implement
internet connectivity for various applications by using single
chip. Figure 1 shows block diagram of the system. Wiznet's
Hardwired TCP/IP is the market proven technology that
supports TCP/UDP, IPV4, ICMP, ARP, IGMP and PPPoE
protocols. W5500 has 32Kbyte internal memory buffer for
Ethernet packet processing.W5500 contains 8 independent
hardware sockets which can be used simultaneously.
Developing codes for TCP/IP stack in FPGA [4] needs huge
amount of expertise, so programming in FPGA for Fig.2. SPI timing analysis on MSO
interfacing with W5500 reduces cost and coding.
complexity B. UDP
Communication interface between W5500 and PC is
UDP. UDP [6] stands for User Datagram Protocol. This is
connectionless and UDP processes data without connection
establishment. If a packet is missed by receiver then receiver
cannot send any signal to transmitter which could retrieve

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the lost data. Transmitter keeps on sending packets until
whole transmission process stops. So it has no error control
over data, hence data can be lost. UDP is very useful for
voice process where we can compromise loss of data over
speed. UDP is faster than TCP. Figure 3 shows flow chart
for UDP process. In UDP first of all operation mode and
port number of socket is set i.e. Socket Mode register,
Socket Source register and Socket Command register is set
and then open command is given. As W5500 supports both
TCP and UDP so we have to select mode for UDP. In UDP
mode, if data are being received then receiving process will
continue until all data are received. After receiving process
is over sending process begins and continue until Time Out
state is reached. Finally UDP stops sending data.
Fig.3. Flow Chart for UDP
III. FRAME FORMAT
W5500 supports sequential data read or data write. SPI
frame consists 16 bit address phase, 8 bit control phase and
N bytes data. Bit7 to Bit3 of control phase are used to select
blocks. Bit2 is used for write or read in blocks and Bit1 to
Bit0 is used to select mode of operation. Mode is used to
send data of fixed byte or variable length byte. Figure 4
shows SPI frame format. FPGA used is Xilinx Zed board
with device XC7Z020. In this experiment we have used
variable length data mode. So data packets of desired length
can be transmitted over long distances.
First two bytes of SPI frame is offset address of socket
registers, third byte is control byte which decides to write or
read that socket register. Next N bytes are used to transfer
the data packets. Variable length of data bytes can be
transmitted in this Variable length data transmission mode
resulting in reduction of data overheads to transmit block of
data.
Fig.4. SPI Frame Format
IV. EXPERIMENT
In this experiment Xilinx board used is Zed board [7]
which has fundamental clock frequency of 100MHz. Figure
5 shows the experimental set up which contains Zed board,
MSO (Mixed signal oscilloscope) and W5500 Ethernet
shield and a workstation (PC). VHDL Code to implement
socket register configuration module, buffer management
module, main FSM controller and SPI engine is developed
in Vivado 2015.1 tool [8]. As per the data sheet of W5500
(Version 1.0, August 2013), commands for corresponding
socket registers are generated by FPGA. MSO has protocol
analyzer which records and analyzes the actual SPI frame
format being transmitted between FPGA and W5500 shield.
Vivado 2015.1 tool is used as platform for synthesis,
implementation, place, route and bit stream generation.
Finally bit stream is burned on FPGA target device.
Simulated data packets are transmitted to workstation
through UDP which is recorded on Packet Sender tool
(Version V_5_3_1) with their time stamp. This is done to
verify the result.
Fig.5. Experimental Set Up
Figure 6 shows block diagram of master controller
implemented in FPGA. Master controller block contains
finite state machines (FSM) controller, initialization module,
variable SPI configuration module, SPI command engine,
receiver buffer, transmitter buffer and buffer pointers.
Variable SPI configuration sends data to SPI engine with
variable data width.
Initialization module configures the socket registers by
setting destination MAC address, source IP address, source
gateway and source port number. After this socket mode is
configured to UDP mode and each transmitter and receiver
buffer size is configured to 16KByte. All FPGA commands
and data are transmitted to W5500 through SPI interface
with SPI frame format as explained in Figure 4.
Transmitter/Receiver buffer management module
synchronizes data transmitted by FPGA to W5500 and data
transmitted by W5500 to FPGA. Buffer pointers are used to
update the current buffer address as W5500 buffers operate
in circular fashion. This module checks for free available
buffer space for loading the data from FPGA to W5500’s
buffer. Main FSM controller synchronizes all the above
mentioned modules.
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 Figure 7 shows commands given by FPGA through SPI
module and its reply by W5500. SPI frame is recorded with
MSO 4104B and corresponding event table is generated. In
figure 7, (80) hex is written at offset address (0000) hex to
reset common registers. Third byte (04) hex is control byte
which depicts write operation. In second line of MOSI MAC
address of PC (DEADBEEFFEED) hex is written in common
register having offset address (0009) hex. Similarly source
gateway address, source IP address and source port number
is configured on W5500 by FPGA. After final configuration
of ports, sockets and buffers, FPGA sends command to
W5500 to initiate the UDP data transmission process.
1KByte of simulated data packets are transmitted by FPGA
to W5500’s transmission buffer and W5500 transmits these
data packets to PC through UDP which is recorded and
verified by Packet Sender software tool (Version V_5_3_1).
Fig.6. Block diagram of Master Controller
Fig.7. Event Table on MSO
V. RESULT
Figure 8 shows snap shot of Packet Sender tool (Version
V_5_3_1) [9] illustrating the data received from FPGA via
W5500 controller through UDP. This snap shot shows time
stamp, source IP address (192.168.13.69), source port
number (8888), destination port number (55930), method
(UDP) and data in ASCII format. Simulated data packets of
1000 bytes are sent to W5500’s transmission buffer and
W5500 sends these data packets to PC. Master controller
starts writing commands in socket registers of W5500 and
checks for free size of W5500's receiver buffer. Time
between first command and command given to check free
size of receiver buffer of W5500 is called initialization time
which is 60µs. Time taken to transmit 1000 bytes of data is
190μs. Hence total time taken to transmit data to PC is
250μs. So we can transmit data through UDP to a remote PC
at the rate of 32Mbps as shown in equation (1). Table I
shows total time taken to transmit 1000 bytes of data from
FPGA to PC.
Data Rate = (1000×8) bits÷250µs =32Megabits/s (1)
Table I. Timing Analysis
Timing No. of Bytes
Analysis
Initialization Data Data Data
Bytes Byte1 Byte2 Byte1000
Time 60μs 190μs
Fixed amount of data having data packet size of 20 bytes
are sent in one loop. Starting value of data packet is given as
Table I .This loop is executed (34)hex[(52)dec] times and
every time data are incremented by 1. Total number of bytes
sent is 52*20=1040 in 190μs. We can approximate 1040 to
1000 bytes. We have used Packet Sender V_5_3_1 to
receive data on PC through UDP mode. Figure 8 shows data
received from source port 8888 to destination port 55930 in
ASCII format.
Fig.8. Data Packets received on Packet Sender
Hence FPGA device sends data at 32 Mbps on UDP by
interfacing W5500 Ethernet controller utilizing the internal
circular buffer mechanism of W5500. This W5500 ethernet
controller interface design module can be integrated with
custom algorithm on FPGA fabric to achieve fast data
communication with PC or outside world over UDP without
compromising algorithm throughput.
This design utilizes flip-flops, LUTs, and buffers which
is shown in figure 9. FPGA uses 3% of its memory for its
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transmission and receiver buffers, 3% for Input/output, 1% would like to extend sincere thanks to Shri Hari Babu
for LUT and 1% for flip flops. Srivastava, Director LASTEC, DRDO, for allowing us to
work at such a prestigious organization.
REFERENCES
[1] M. R. Mahmoodi, S. M. Sayedi and B. Mahmoodi, “Reconfigurable
hardware implementation of gigabit UDP/IP stack based on spartan-6
FPGA”, Information Technology and Electrical Engineering
(ICITEE) 2014 6th International Conference on, pp. 1-6, 2014.
[2] “W5500 ethernet controller datasheet”, December 2014. [Online
document]. Available :http://www.wiznet.io/product-item/w5500.
[Accessed: April 2018]
Fig.9. FPGA Utilization Report on Vivado [3] Goran Horvat, Damir Sostaric, Zoran Balkic “ Cost-effective Ethernet
communication for low cost microcontroller architecture”,
International Journal of Elctrical and Computer Engineering Systems,
vol.3, November 1,2012.
In contrast with FPGA based design, Microcontroller
[4] “Xilinx 10Gbps TCP/IP stack datasheet”, February 2015. [Online].
based ethernet solutions can also be implemented using
Available:http://www.forums.xilinx.com/xlnx/attachments/xlnx/CON
inbuilt ethernet controller [10] or by interfacing with N/11601/1/TCPIPDatasheet_v1_060315.pdf. [Accessed: April 2018]
external ethernet controller like W5500. In case of [5] F. Leens, “An introduction to I2C and SPI protocols,” IEEE
microcontroller with inbuilt ethernet controller, TCP/UDP Instrumentation & Measurement Magazine, pp. 8-13, February 2009.
software stack/firmware is used. While in case external [6] “A deeper look At UDP/IP protocol”, 28 February 2017. [Online].
controller (W5500) with ATmega328P [11-12] operating at Available:http://www.sionsemi.com/whitepapers/udp-ip-
overview.html. [Accessed: April 2018]
maximum clock frequency is 16 MHz, data rate only up to
[7] “ZynqTM evaluation and development hardware user's guide”, 27
250 Kilo Bytes per second (KB/s) can be achieved over SPI January 2014. [Online]. Available :www.zedboard.org. [Accessed:
interface. April 2018]
Thus FPGA based design offers higher data transfer rate [8] “Vivado design tool (2015.1)”, April 2015. [Online]. Available
:http://www.xilinx.com/ . [Accessed: April 2018]
with external ethernet controller (W5500) in comparison
[9] “Packet sender software tool”, February 2017. [Online]. Available
with microcontroller based approach. :https://github.com/dannagle/PacketSender/releases?after=v5.3.1.
[Accessed: April 2018]
VI. CONCLUSION [10] Shang He, “Design and implement of an embedded ethernet system
In this paper FPGA based W5500 ethernet controller based on LPC2368 microprocessor”, Computer Application and
System Modeling (ICCASM), vol.8, pp.671-675, 2010.
interface design module solution for Ethernet
[11] “ATmega328P Datasheet”, May 2009. [Online]. Available
communication as alternative for TCP/UDP Software Stack :http://www.microchip.com/. [Accessed: April 2018]
has been developed and implemented. In this experiment [12] Wang Mei, Zhao Ruimei, Duan Huiting, “Design and realization of
FPGA device has fundamental clock frequency of 100MHz the embedded ethernet communication system based on ARM”, 2nd
and W5500 device supports clock frequency up to 80MHz. International Symposium on Information Science and Engineering
(ISISE), pp.287-289, 2009.
SPI clock (SCLK) generated from the FPGA board is
50MHz and this enables user to transmit data at the rate of
32 Mbps. As the Ethernet controller supports clock
frequency up to 80MHz the data transmission rate can be1.
further increased by increasing SPI clock from 50MHz to1.
80MHz. FPGA based 50 MHz SPI interface design offers
better utilization of W5500 as compared to ATmega328P
microcontroller based design. This design also offers low
cost FPGA based TCP/UDP design module as an alternative
to commercial available TCP/UDP IP core for embedded
system development. Further development can be done by
incorporating TCP mode support to W5500 ethernet
controller interface design in addition to UDP mode. This
will guarantee end to end delivery of each data packet at the
cost of speed. It is observed that the proposed system has
large flexibility to implement different Ethernet based
controller in real time. Security is an important issue related
to embedded system whenever data are transmitted over a
network. Any malicious content can infect our system and
corrupt our data. Proper security related protocol can be
implemented at upper layer of IP. We still need to work in
the area where appropriate security can be guaranteed.
ACKNOWLEDGEMENT
We are obliged to Ms. Sandhya Bajaj, Group Head EEG,
LASTEC, DRDO for giving us opportunity to work on
LASTEC projects as well as for her fruitful suggestions. We

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