2015 International Conference on Information Processing (ICIP)
Vishwakarma Institute of Technology. Dec 16-19, 2015
Design of Area and Delay Efficient Vedic Multiplier
Using Carry Select Adder
Ms. G. R. Gokhale
E&TC dept.
N. K. Orchid college of Engg & Tech
Solapur, India
gokhalegayatri1991@gmail.com
Abstract— In this paper, Vedic multiplier is designed using
area-efficient Carry Select Adder (CSLA). As the multiplication
is the process of subsequent addition, adder is important block in
implementation of multiplier. Digital adder has problem of carry
propagation, thus carry select adder is used instead of simple
Ripple Carry Adder (RCA). Carry select adder is known to be
one of the fastest adder structures. Here Vedic multiplier is
implemented instead of normal multipliers like add and shift
multiplier, array multiplier etc. The goal of this paper is to design
Vedic multiplier based on crosswise and vertical algorithms using
area-efficient CSLA. Conventional CSLA designs like Binary to
Excess one Converter (BEC) based CSLA and Modified CSLA
(MCSLA) are compared with proposed CSLA design to prove its
efficiency. It shows improved performance in terms of area. This
renovated CSLA is used to design proposed Vedic multiplier. It
has 6% less area than Vedic multiplier using MCSLA and 16%
less area than Vedic multiplier using BEC-based CSLA.
Proposed design is also compared with the Booth multiplier.
Proposed multiplier showed more excellent results than Booth
multiplier.
Keywords— Carry Select Adder; Ripple Carry Adder; Binary to
Excess one Converter; Vedic Multiplier; Area-Efficient; Delay.
I. INTRODUCTION
There is booming in use of portable devices in day to day
life ultimately demand for high performance Very Large Scale
Integration (VLSI) systems have been increased. To cope with
these demands various researchers are developing improved
VLSI systems in terms of area, power, delay etc. Multiplier is
one of the important blocks in arithmetic unit. High speed and
area-efficient multiplier is required in various Digital Signal
Processing (DSP) algorithms. Vedic multiplication is used in
various DSP applications like convolution, Fast Fourier
Transform and microprocessor applications. Vedic
mathematics is an ancient mathematical technique. Vedic is a
word obtained from the word “Veda” and its meaning is “store
house of all knowledge” [1]. These mathematical techniques
require less area and they work with high speed. 16 sutras are
basis of Vedic mathematics. In this paper, 8 by 8 multiplier is
implemented using “Urdhva-Tiryakbhyam – Vertically and
crosswise.”
 forwarding pre-carry to next steps as explained earlier. In this
978-1-4673-7758-4/15/$31.00 ©2015 IEEE
Mr. S. R. Gokhale
Comp dept.
Modern Education Society’s College of Engg
Pune, India
sohamgokhale96@gmail.com
The rest of the paper is as follows. Introduction to Urdhva-
Tiryakbhyam method is given in section II. Architecture of
Vedic multiplier is explained in section III. Conventional carry
select adder and proposed design are presented in section IV
and V respectively. Implementation results and conclusion are
given in sections VI and VII respectively.
II. ANCIENT VEDIC MATHEMATICAL ALGORITHM
By applying sutras Vedic mathematics resolves
complexicty of calculations. It requires less computaion time
and less hardware for implemetation. These sutras are
basically used for decimal multiplication here it is
incarporated to binary multiplication.
A. Urdhva – Tiryakbhyam Sutra(Vertically and Crosswise)
In this paper implementation of Vedic multiplication
technique namely “Urdhva-Tiryakbhyam – Vertically and
crosswise” is demonstrated. This technique is more popular
for its high speed working as it generates partial products in
parallel manner and then adding partial products
simultaneously. There is reinforcing need of high speed data
processing systems. Vedic multiplier conciliates this need
without increasing power consumption. It has less complexity
compared to booth multiplier. Vedic multiplier requires less
hardware. Thus Vedic multiplier gives numerous advantages
in terms of area, power, delay and complexity.
B. Example for Vedic multiplication (Decimal
Multiplication)
Two decimal numbers 234 and 159 are considered.
Multiplication of these two numbers (234 X 159) is described
with the line diagram for clear understanding as shown in fig.
1. At first, two numbers shown with line are multiplied, 2
digits output is generated. One’s place of this generated result
is stored as one’s place of final product and ten’s place of the
generated output is hooked up as pre-carry for the next step. In
this way the process perpetuated. At which point, there is
more than one digit to multiply then multiply those digits
shown with lines and accumulate all those generated products.
Output of this summation is again stored in final result with
way process continues to get final result of multiplication of
two numbers (234 X 159).
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Fig. 1. Multiplication of two decimal numbers
III. ARCHITECTURE AND IMPLEMENTATION OF VEDIC
MULTIPLIER
In the previous section Vedic multiplication technique for
decimal numbers is described. This section explains
architecture of N by N bit multiplier. The Vedic multiplication
technique can be used for multiplication of binary numbers.
Implementation of 2 X 2 Vedic multiplier block is prime
important in the implementation of 4 X 4 and 8 X 8 Vedic
multiplier architecture. In this section implementation of 2 X
2, 4 X 4 and 8 X 8 Vedic multiplier architecture are explained.
A. 2 X 2 Vedic Multiplier Block
Here, actual Urdhva -Tiryagbhyam Sutra multiplication
technique is applied by to 2 binary numbers with 2 bits each.
Considering two numbers are A and B where A = A1A0 and B
= B1B0. Least Significant Bit (LSB) of first number A that is
A0 and LSB of second number B that B0 are multiplied with
each other (vertical). Generated product is saved as LSB of
final result. Thus, AND gate is used for multiplication of A0
and B0. Fig. 2, shows 2 X 2 multiplication process. Next step
is to multiply LSB of number A with MSB of number B that is
(A0 X B1) and MSB of number A with LSB of number B that
is (A1 X B0). Thus, two AND gates are required for this
multiplication.
Fig. 2. 2 X 2 Vedic multiplier architecture
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These generated product are added that is (A0 X B1) + (A1
X B0) using half adder. This summation generates output of 2
bits. LSB of this generated output is loaded as second bit of
final result and MSB of this generated output is loaded as pre
carry for next step. Last step is multiplication of MSB of A
with MSB of B that is (A1 X B1). One AND gate is utilized for
this multiplication. This generated product is added with pre
carry of previous step. Thus again one more half adder is
required for it. This half adder generates 2 bits output which is
taken as third and fourth bit of final result. The final result is
given by C2S2S1S0. In this way 2 X 2 Vedic multiplication
process is carried out. The 2 X 2 Vedic multiplication process
is shown with equations.
S0 = A0B0 (1)
C1S1 = A0B1 + A1B0 (2)
C2S2 = C1 + A1B1 (3)
B. 4 X 4 Vedic Multiplier Block
In this section 4 X 4 Vedic multiplier architecture is
discussed. Consider two 4-bits numbers such as A and B
where A = A3A2A1A0 and B = B3B2B1B0. The LSBs of two
numbers (A0 X B0) are multiplied to generate LSB S0 of final
result. Same procedure is hunted here as 2 X 2 Vedic
multiplication procedure discussed earlier. Initially pre-carry
is set to zero. In each and every step generated carry is
forwarded to next step and process goes on. At the end C6 and
S6 is obtained. Output lines C6S6S5S4S3S2S1S0 gives finally
generated result.
The 4 X 4 Vedic multiplication block diagram is shown in
fig. 3. Here, 2 X 2 Vedic multipliers are used to implement 4
X 4 Vedic multiplier to generate partial product. Three ripple
carry adders of 4 bits each are used for addition of generated
partial products. The carry output of first two ripple carry
adders are ORed and output of this OR gate is given to next
ripple carry adder. Zero inputs are given to some of the ripple
carry adders wherever required. The arrangement of ripple
carry adders is made in such way that computation time
required for whole multiplication process is reduced and speed
of working is increased.
Fig. 3. 4 X 4 Vedic multiplier architecture
C. 8 X 8Vedic Multiplier Block
Here, implementation of 8 by 8 Vedic multiplier is
outlined. Consider two 8-bits binary numbers namely A and B
where A = A7A6A5A4A3A2A1A0 and B = B7B6B5B4B3B2B1B0.
8 X 8 Vedic multiplication process is mirror to 4 X 4 Vedic
multiplier expressed in the previous sub-section B. Pre-carry
at first step is set to zero. In every step generated carry is
shifted to next step for addition and process continues. At the
end C14 and S14 is obtained. Finally generated result is given in
terms of C14S14S13S12S11S10S9S8S7S6S5S4S3S2S1S0.
Implementation of 8 by 8 Vedic multiplier is clearly
understood from the block diagram as shown in fig. 4. Here,
four 4 X 4 Vedic multiplier blocks and three carry select
adders of 8 bits each are used. The arrangement of the carry
select adders is made in different way such that it requires less
computation time. Some of the carry select adders are given Fig. 5. BEC-Based CSLA
with zero inputs, wherever required. Output of middle
multipliers are added using first CSLA. Output of first CSLA According to the input carry Cin = ‘0’ or ‘1’, final output
and first Vedic multiplier are added using second CSLA. is selected. If Cin = ‘0’ then multiplexer will select output of
Carry outputs from first two CSLAs are ORed and given as RCA else it will select output of BEC. BEC takes the output of
input to the third CSLA to generate final result. RCA and gives output to multiplexer. As the name suggests,
BEC generates output by adding one to its input. Thus,
whenever Cin = ‘1’ multiplexer will select output of BEC.
Accordingly final sum and carry is generated. By using this
BEC-based CSLA, Vedic multiplier [1] is implemented.

B. MCSLA
B. K. Mohanty and S. K. Patel proposed modified CSLA
[3]. The block diagram of that carry select adder is shown in
fig. 6. This CSLA has one Half Sum Generation (HSG) unit,
one Final Sum Generation (FSG) unit, one Carry Generation
(CG) unit, and one Carry Selection (CS) unit. The CG unit
composed of two CGs (CG0 and CG1) corresponding to input-
carry ‘0’ and ‘1’ [3]. Two n bit operands (A and B) are given
to HSG unit that generates n bits S0 and n bits C0. These
generated S0 and C0 are given to CG0 as well as CG1 and n-bit
full carry words C01 and C11. CS unit selects one of the outputs
from full carry words C01 and C11. If Cin = ‘0’ then CS will
select C01, else it will select C11. By using this modified
CSLA, Vedic multiplier [8] is implemented.
Fig. 4. 8 X 8 Vedic multiplier architecture

IV. CONVENTIONAL CARRY SELECT ADDER

In [1] Vedic multiplier is implemented using BEC based
carry select adder whereas in [8] Vedic multiplier is
implemented with MCSLA. Still there is scope to use more
efficient carry select adder instead of CSLA [2] [3]. Hence
new Vedic multiplier is proposed using more efficient carry
select adder. In this paper, 8 X 8 Vedic multiplier is
implemented as shown in fig. 4.

A. BEC Based CSLA

B. Ramkumar and H. M. Kittur [2] presented low power &
area efficient CSLA composed of one RCA & one BEC
instead of twin RCA. The structure of that carry select adder is
shown in fig. 5. Fig. 6. Modified CSLA

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 V. PROPOSED DESIGN
BEC-based CSLA and MCSLA are briefly studied and
noticed the possibility of designing more improved CSLA.
Proposed CSLA consists of basically two units 1) sum and
carry generation unit 2) sum and carry selection unit.
Redundant operations present in previous CSLA designs are
identified and eliminated. This has lent a hand to reduce
number of gates required for the proposed design. So the aim
is to reduce number gates required for the design of CSLA.
Minimizing the number of gates of design involves two steps
• Generate all the prime implicants for the given logic
function f [9].
• Find the set of essential prime implicants. Fig.7. Single stage CSLA
Accordingly new area-efficient carry select adder is
designed. B. Multistage CSLA
By cascading single stage CSLAs, multistage CSLAs are
A. Single Stage CSLA formed. Here different bit widths of CSLA are designed such
as 8-16-32 bits. Proposed CSLA structure at gate level is
In proposed design some logic formulations are made.
shown in fig. 8 where fig. 8 (a) stands for gate level design of
Depending upon the sum and carry functions equal to ‘1’
carry generation unit. Gate level implementation of sum
prime implicants are noted down. Essential prime impicants
generation unit is shown in fig. 8 (b). Gate level design of sum
are combined so that final sum and final carry can be
and carry selection unit is shown in fig. 8 (c). For selection of
generated. Separate sum and carry selection units are used
sum and carry multiplexer is utilized. These are 4:2
after sum and carry generation units to eliminate the redundant
multiplexers obtained from two 2:1 multiplexers one for carry
operations. At first, single stage CSLA is implemented.
selection and other for sum selection.
Depending upon bit pattern of input carry ‘Cin’ final sum and
carry is selected. ‘If Cin = ’0’ then carry selection unit will Multistage CSLA of ‘n’ bit width is shown in fig. 9.
select output ‘p’ from carry generation unit else it will select Equations for sum generation carry generation as well as sum
‘q’. If Cin = ‘0’ then sum selection unit will select output ‘r’ and carry selection are given below.
from sum generation unit else it will select‘s’ as shown in the
fig. 7.

Fig.8. (a) Carry generation unit (b) Sum generation unit (c) Sum and carry selection unit

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 MCSLA based Vedic multiplier. Vedic multiplier is also
compared in terms of delay. Delay is maximum
combinational path delay obtained from the final report.
Proposed Vedic multiplier shows lesser delay than Vedic
multiplier using MCSLA but it has higher delay than BEC-
based Vedic multiplier as shown in fig. 11. Proposed Vedic
multiplier is also compared with Booth multiplier [4] in
terms of area and delay. Results obtained from these
implementations are shown in Table III. Vedic multiplier
shows better performance results than Booth multiplier in
terms of area as well as delay as shown in fig. 12 and fig. 13
respectively. Proposed Vedic multiplier is faster compared
to Booth multiplier.

TABLE I. COMPARISON OF PROPOSED AND EXISTING CSLAS

Fig.9. Multistage CSLA
Width Area
Design
p(i) = a(i) ǜ b(i) (4a) (n) (gate count)

q(i) = a(i) + b(i) (4b) 8 188

BEC based CSLA [2] 16 376
s(i) = p(i) + q(i) (5a)
32 752
r(i) = s(i) (5b)
8 133
c(i) = p(i) if (Cin = 0) (6a)
Modified CSLA [3] 16 266
c(i) = q(i) if (Cin = 1) (6b)
32 532
sum(i) = r(i) if (Cin = 0) 7(a) 8 104
sum(i) = s(i) if (Cin = 1) 7(b) Proposed CSLA 16 208

Equations for carry generation are given by 4(a) and 32 416

4(b). Sum generations are given by equations 5(a) and 5(b).
If ‘Cin = 0’ then output carry c(i) will take input from carry TABLE II. COMPARISON OF PROPOSED AND EXISTING VEDIC
generation unit as p(i) and output sum(i) will take input MULTIPLIER
from sum generation unit as r(i) as given in equations 6(a)
and 6(b). If ‘Cin = 1’ then output carry c(i) will take input Design
Width Area Delay
from carry generation unit as q(i) and output sum(i) will (n) (gate count) (ns)
take input from sum generation unit as s(i) as provided in
equations 7(a) and 7 (b). Here, in all the equations ‘i’ is Vedic Multiplier [1] 8 bits 1545 41.696
equal to 0 to n-1.

VI. IMPLEMENTATION RESULTS Vedic Multiplier [8] 8 bits 1380 45.678

Xilinx tool is used for the simulation. First of all, BEC

Proposed Vedic
based CSLA [2] and MCSLA [3] are designed for 8-16-32 multiplier
8 bits 1293 44.358
bit widths in Xilinx schematic entry tool. Results that is area
for these two CSLAs are shown in Table I. Area required is
conveyed as the number of AND, OR, INV (AOI) gates
required for the design. Here gate count is chosen for 1600
comparison. Table I. shows that proposed CSLA has better
1500 BEC Based Vedic
performance than MCSLA and BEC based CSLA. Thus,
Multiplier
proposed Vedic multiplier design is implemented using 1400
refined CSLA. Vedic multipliers based on BEC based 1300
MCSLA Based
CSLA and MCSLA are designed separately. Table II shows Vedic Multiplier
result obtained from all these Vedic multipliers. Vedic 1200 Proposed Vedic
multiplier is also designed in the Xilinx schematic entry tool 1100
Multiplier
and final report generated after post and route simulation. Area
Here, total number of gate count is obtained. Fig. 10, shows
that proposed Vedic multiplier based on this renovated
CSLA is supreme compared to conventional BEC based and Fig. 10. Area comparison of proposed and conventional Vedic multiplier

299
 VII. CONCLUSION
46 Vedic multiplier using carry select adder is implemented
45 here. At first conventional CSLAs like (BEC based CSLA
44 BEC Based Vedic
43 Multiplier and MCSLA) as well as proposed CSLA are implemented.
42 MCSLA Based According to the results obtained, it is concluded that
41 Vedic Multiplier proposed carry select adder requires less number of gates
40
Proposed Vedic
than both MCSLA and BEC based CSLA. On an average,
39
Multiplier proposed carry select adder requires 21 % less area than
Delay MCSLA and 44% less area than BEC based CSLA for
(ns) different bit widths. Hence proposed Vedic multiplier is
implemented using this improved CSLA. Proposed Vedic
multiplier requires less number of gates. On an average,
Fig. 11. Delay comparison of proposed and conventional Vedic multiplier proposed Vedic multiplier requires 6% less area than Vedic
multiplier using MCSLA and 16% less area than Vedic
multiplier using BEC based CSLA. Thus proposed Vedic
TABLE III. COMPARISON OF DELAY AND AREA BETWEEN BOOTH AND multiplier is more area-efficient than conventional Vedic
PROPOSED VEDIC MULTIPLIER
multipliers. Proposed Vedic multiplier is also compared
with conventional Vedic multipliers in terms of delay.
Design
Width Area Delay Proposed Vedic multiplier requires less delay than Vedic
(n) (gate count) (ns) multiplier using MCSLA whereas it requires more delay
than Vedic multiplier using BEC – based CSLA. Proposed
Vedic multiplier is also compared with the Booth multiplier.
Booth Proposed Vedic multiplier has approximately 43 % less area
8 bits 2301 52.677
Multiplier [4] than Booth multiplier. Proposed multiplier is faster than
Booth multiplier as it has approximately 15 % less delay
than Booth multiplier. Thus, Proposed Vedic multiplier is
Proposed Vedic superior to Booth multiplier in terms of delay as well as
8 bits 1293 44.358
Multiplier
area.

2500
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1500
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