Deshdeepak Nautiyal

Contact No: +91-9591183105 Email:deepakn97@gmail.com

Synopsis

VLSI Hardware Engineer with substantial experience of RTL verification for complex ASIC
products. Main areas include,
➢ Experience of development of coverage-driven constrained random test environments at IP,
subsystem and SOC level
➢ Experience in Verification planning, test planning and coverage closure
➢ Sound Understanding and experience in verifying various complex protocols such as ARM
architecture, DDR ,SATA and AMBA ACE ,based ASICs .

➢ Good knowledge of System Verilog (SV), UVM, based component, sequences, cover groups,
checkers.

Work Experience

April 2017 – Present: Qualcomm India Private Limited, Noida

Senior Engineer, Corporate R&D Division .

August 2015 – April 2017: Mentor Graphics India Private Limited, Noida
Senior member of technical staff, Veloce Emulation Transactor Group.

October 2012 – August 2015 :Sankalp Semiconductor Private Limited, Bangalore

Verification Engineer, Digital Business Unit

Overall Experience of 7+ years in the field of Digital Frontend Verification.

Core Skills

HVLs : System Verilog , UVM

HDLs : Verilog
Protocol : AMBA AXI4 ,ACE,SATA
Software Languages : C,C++
EDA Tool : Questa ,Ncsim (Cadence) , and VCS
Emulation tools : Veloce (Mentor Graphics)
Scripting language : Shell,Make
Operating system : Unix,Windows

Projects Experience

1) Verification of Neural signal processor subsystem

Language: System Verilog, UVM
Tools used: VCS, Verdi
Organization: Qualcomm
Duration: October 2018 – Present

Description: NSP (Neural signal processor) subsystem is a subsystem made to accelerate server
on pretrained data .This subsystem was built around DSP processor and have capability to
communicate with complex NOC working on 4 QNS4 slave , 4 QNS4 slave ,1 AXI slave and 1 APB
slave .

Roles & Responsibilities

➢ Created testplan and verification plan for debug feature
➢ Independently lead verification of debug feature trace, trigger and CSR access
➢ Worked on verification of DSP subsystem processor features such as Interrupt, crash reset
and subsystem restart.
➢ Contribute on GLS flow and GLS failure debugging .

2) Verification of Centriq Server SOC.

Language: System Verilog, UVM, C based environment
Tools used: VCS Simulator ,Vplanner
Duration: April 2017 – Oct 2018
Description: Centriq is ARM based multicore chip ,having ARM-v8 based 82 processing cores ,One
Boot core and one Debug processor core, PCIE ,USB ,Ethernet ,DDR etc connected 34 subsystems
and ARM Coresight based debug architecture
.
Roles & Responsibilities :

➢ Understanding specification of all debug component (e.g DAP ,CTI ,TPIU, ETB and ETR ) in
each subsystem and preparing testplan and verification plan
➢ Writing self checking C based tests to verify Trigger network built on ARM Coresight Cross
trigger interface across on SOC
➢ Verifying ATB Trace ,QATB trace ,generic trace ,source to sink verification
➢ Worked on Debug and config access Port (DAP), Interrupts ,Trace ,trigger ,reset and clock
architecture feature verification.

3) Verification of ACE Transactor

Language: System Verilog, UVM,
Tools used: Veloce Emulator ,Questa .`
Organization: Mentor Graphics India Pvt Ltd, Noida
Duration: Aug 2015 – April 2017

Description: ACE, defined as part of the AMBA 4 specification, extends AXI with additional
signaling introducing system wide coherency. This transactor a behavioral model of ACE master
,was having in built software based cache memory and hardware synthesizable ACE transactor .
Roles & Responsibilities
➢ Understanding Coherency and Cache memory concepts in ARM architecture.
➢ Defining and implementing verification plan and verification environment
architecture
➢ Generating AXI transaction and snoop transaction based test cases ,causing change
in cache states ,coherency .
➢ Developing UVM based self-checking environment for this transactor.
➢ Generate various IP level and system level test suite
➢ Provide customer support for various issues/features

4) Verification of SATA Host Controller Adapter

Language: System Verilog ,UVM,UVM register model
Tools :NCSIM and Questa
Customer: Sankalp & KPIT Semiconductor in house product
Duration: October 2012-Dec 2013

Description: SATA Host Controller Adapter is 1st generation SATA controller which works on 1.5
Gbit/s-150 MB/s .The SATA host adapter supports an Configuration bus and DMA Interface on
CPU side, while a single SATA port on device side. SATA port can plug third party PHY layer and
can be connected via this PHY to the SATA device (optical disk or drive).

Roles & Responsibilities

➢ Extracted features and Created Verification plan, Test Plan and coverage plan
➢ Developed UVM based register model.
➢ Developed SV assertions for Link Layer Primitives.
➢ Register model based Coverage and scoreboard.
➢ Developed sequences and test cases to generate interesting scenarios.
➢ Regression, functional and code coverage closure.

Education

Education College / School Discipline Academic year Percentage

Bachelors of GBPEC, Pauri Garhwal Electronics & 2008-2012 71.94

Technology under Uttarakhand Communication
Technical University
Intermediate G.G.D.S.V.M. , 2007 84.6
Uttarkashi,
Uttarakhand
High school G.G.D.S.V.M. , 2005 82.3
Uttarkashi,
 Uttarakhand

Personal Details

Name : Deshdeepak Nautiyal

Father’s Name : Mr. Nagendra Dutt Nautiyal
Date Of Birth : July 5, 1991
Address : c-87/2 First floor Pryavaran complex Saket, Delhi
Nationality : Indian
Languages : English, Hindi
Hobbies : Creative Writing
Marital Status : Married

Declaration

I hereby declare that all the information furnished above is true to the best of my knowledge
and belief.
Deshdeepak Nautiyal