VHDL code ( including the RegisterFile-RAM based

model ) for SimpleProcessor of BrownVranesic

chapter 7
library ieee;

use ieee.std_logic_1164.all;

entity regn is

generic (N : integer := 8);

port (R : in std_logic_vector(N-1 downto 0);

Rin, Clock : in std_logic;

Q : out std_logic_vector(N-1 downto 0));

end regn;

architecture Behavior of regn is

begin

process

begin

wait until Clock'EVENT and Clock = '1';

if Rin = '1' then

Q <= R;

end if;

end process;

end Behavior;

library ieee;

use ieee.std_logic_1164.all;

entity shiftr is -- left-to-right shift register with async reset

generic (K : integer := 4);

port (Resetn, Clock, w : in std_logic;

 Q : buffer std_logic_vector(1 to K)) ;

end shiftr;

architecture Behavior of shiftr is

begin

process (Resetn, Clock)

begin

if Resetn = '0' then

Q <= (others => '0');

elsif Clock'event and Clock = '1' then

Genbits : for i in K downto 2 loop

Q(i) <= Q(i-1);

end loop;

Q(1) <= w;

end if;

end process;

end Behavior;

library ieee;

use ieee.std_logic_1164.all;

--use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity upcount is

port (Clear, Clock : in std_logic;

Q : buffer std_logic_vector(1 downto 0)) ;

end upcount;

architecture Behavior of upcount is

begin

upcount : process (Clock)

 begin

if (Clock'EVENT and Clock = '1') then

if Clear = '1' then

Q <= "00";

else

Q <= std_logic_vector( unsigned(Q) + 1 );

end if;

end if;

end process;

end Behavior;

library ieee;

use ieee.std_logic_1164.all;

entity dec2to4 is

port(sel : in std_logic_vector(1 downto 0);

en : in std_logic;

op : out std_logic_vector(3 downto 0)

);

end dec2to4;

architecture behav of dec2to4 is

begin

process(sel, en)

begin

if(en = '0')then

op <= "0000";

else

if(sel = "00")then

op <= "1000";
 elsif(sel = "01")then

op <= "0100";

elsif(sel = "10")then

op <= "0010";

else

op <= "0001";

end if;

end if;

end process;

end behav;

library ieee;

use ieee.std_logic_1164.all;

entity trin is

generic (N : integer := 8);

port (X : in std_logic_vector(N-1 downto 0);

E : in std_logic;

F : out std_logic_vector(N-1 downto 0)) ;

end trin;

architecture Behavior of trin is

begin

F <= (others => 'Z') when E = '0' else X;

end Behavior;

library ieee;

use ieee.std_logic_1164.all;

package subccts is
component regn -- register

generic (N : integer := 8);

port (R : in std_logic_vector(N-1 downto 0);

Rin, Clock : in std_logic;

Q : out std_logic_vector(N-1 downto 0)) ;

end component;

component shiftr -- left-to-right shift register with async reset

generic (K : integer := 4);

port (Resetn, Clock, w : in std_logic; Q : buffer std_logic_vector(1 to K));

end component;

component trin -- tri-state buffers

generic (N : integer := 8);

port (X : in std_logic_vector(N-1 downto 0);

E : in std_logic;

F : out std_logic_vector(N-1 downto 0)) ;

end component;

component upcount is

port (Clear, Clock : in std_logic;

Q : buffer std_logic_vector(1 downto 0)) ;

end component;

component dec2to4 is

port(sel : in std_logic_vector(1 downto 0);

en : in std_logic;

op : out std_logic_vector(3 downto 0)

);
 end component;

end subccts;

library ieee;

use ieee.std_logic_1164.all;

--use ieee.std_logic_signed.all;

use ieee.numeric_std.all ;

use work.subccts.all;

entity proc is

port (Data : in std_logic_vector(7 downto 0);

Reset, w : in std_logic;

Clock : in std_logic;

F, Rx, Ry : in std_logic_vector(1 downto 0);

Done : buffer std_logic;

BusWires : inout std_logic_vector(7 downto 0);

debug_T, debug_I : out std_logic_vector(3 downto 0);

debug_FuncReg : out std_logic_vector(1 to 6);

debug_R0, debug_R1, debug_R2, debug_R3 : out std_logic_vector(7 downto 0);

debug_extern : out std_logic) ;

end proc;

--architecture Behavior of proc is

-- signal Rin, Rout : std_logic_vector(0 to 3);

-- signal Clear, High, AddSub : std_logic;

-- signal Extern, Ain, Gin, Gout, FRin : std_logic;

-- signal Count, Zero : std_logic_vector(1 downto 0);

-- signal T, I, X, Y : std_logic_vector(0 to 3);

-- signal R0, R1, R2, R3 : std_logic_vector(7 downto 0);

-- signal A, Sum, G : std_logic_vector(7 downto 0);

-- signal Func, FuncReg : std_logic_vector(1 to 6);

--begin

-- Zero <= "00";

-- High <= '1';

-- Clear <= Reset or Done or (not w and T(0));

-- counter : upcount port map (Clear, Clock, Count);

-- decT : dec2to4 port map (Count, High, T);

-- Func <= F & Rx & Ry;

-- FRin <= w and T(0);

-- functionreg : regn generic map (N => 6) port map (Func, FRin, Clock, FuncReg);

-- decI : dec2to4 port map (FuncReg(1 to 2), High, I);

-- decX : dec2to4 port map (FuncReg(3 to 4), High, X);

-- decY : dec2to4 port map (FuncReg(5 to 6), High, Y);

-- Extern <= I(0) and T(1);

-- Done <= ((I(0) or I(1)) and T(1)) or ((I(2) or I(3)) and T(3));

-- Ain <= (I(2) or I(3)) and T(1);

-- Gin <= (I(2) or I(3)) and T(2);

-- Gout <= (I(2) or I(3)) and T(3);

-- AddSub <= I(3);

-- RegCntl : for k in 0 to 3 generate

-- Rin(k) <= ((I(0) or I(1)) and T(1) and X(k)) or ((I(2) or I(3)) and T(3) and X(k));

-- Rout(k) <= (I(1) and T(1) and Y(k)) or ((I(2) or I(3)) and ((T(1) and X(k)) or (T(2) and Y(k))));

-- end generate RegCntl;

-- tri_extern : trin port map (Data, Extern, BusWires);

-- reg0 : regn port map (BusWires, Rin(0), Clock, R0);

-- reg1 : regn port map (BusWires, Rin(1), Clock, R1);

-- reg2 : regn port map (BusWires, Rin(2), Clock, R2);

-- reg3 : regn port map (BusWires, Rin(3), Clock, R3);

-- tri0 : trin port map (R0, Rout(0), BusWires);

-- tri1 : trin port map (R1, Rout(1), BusWires);

-- tri2 : trin port map (R2, Rout(2), BusWires);

-- tri3 : trin port map (R3, Rout(3), BusWires);

-- regA : regn port map (BusWires, Ain, Clock, A);

-- alu : with AddSub select

-- Sum <= std_logic_vector(signed(A) + signed(BusWires)) when '0',

-- std_logic_vector(signed(A)-signed(BusWires)) when others;

-- regG : regn port map (Sum, Gin, Clock, G);

-- triG : trin port map (G, Gout, BusWires);

--

-- --Debug signals

-- debug_T <= T;

-- debug_I <= I;

-- debug_FuncReg <= FuncReg;

-- debug_R0 <= R0;

-- debug_R1 <= R1;

-- debug_R2 <= R2;

-- debug_R3 <= R3;

-- debug_extern <= Extern;

--end Behavior;

architecture RegFileBehavior of proc is

signal Rin, Rout : std_logic_vector(0 to 3);

signal Clear, High, AddSub : std_logic;

signal Extern, Ain, Gin, Gout, FRin : std_logic;

signal Count, Zero : std_logic_vector(1 downto 0);

signal T, I, X, Y : std_logic_vector(0 to 3);

signal R0, R1, R2, R3 : std_logic_vector(7 downto 0);

signal A, Sum, G : std_logic_vector(7 downto 0);

signal Func, FuncReg : std_logic_vector(1 to 6):=(others=>'0');

signal RF_wr_en : std_logic := '0' ;

signal RF_wr_addr , RF_rd_addr : std_logic_vector( 1 downto 0 ) := "00" ;

type t_RegFile is array (natural range <>) of std_logic_vector(7 downto 0);

signal RF : t_RegFile( 0 to 3 ) := ( others => ( others => '0' ) );

signal RF_out : std_logic_vector( 7 downto 0 );

begin

Zero <= "00";

 High <= '1';

Clear <= Reset or Done or (not w and T(0));

counter : upcount port map (Clear, Clock, Count);

Func <= F & Rx & Ry;

FRin <= w and T(0);

functionreg : regn generic map (N => 6) port map (Func, FRin, Clock, FuncReg);

decT : dec2to4 port map (Count, High, T);

decI : dec2to4 port map (FuncReg(1 to 2), High, I);

Extern <= I(0) and T(1);

Done <= ((I(0) or I(1)) and T(1)) or ((I(2) or I(3)) and T(3));

Ain <= (I(2) or I(3)) and T(1);

Gin <= (I(2) or I(3)) and T(2);

Gout <= (I(2) or I(3)) and T(3);

AddSub <= I(3);

regA : regn port map (BusWires, Ain, Clock, A);

alu : with AddSub select

Sum <= std_logic_vector(signed(A) + signed(BusWires)) when '0',

std_logic_vector(signed(A)-signed(BusWires)) when others;

regG : regn port map (Sum, Gin, Clock, G);

process ( Clock, Reset )

begin

if ( Reset = '1' ) then RF <= ( others => ( others => '0' ) );

elsif rising_edge( Clock ) then

if ( RF_wr_en = '1' ) then

RF( to_integer( unsigned(RF_wr_addr) ) ) <= BusWires ;

end if ;

end if ;

end process ;
 RF_out <= RF( to_integer( unsigned(RF_rd_addr) ) ) ;

BusWires <= RF_out

when ((I(1) and T(1)) or ((I(2) or I(3)) and (T(1) or T(2))))='1'

else G when Gout='1'

else Data when Extern='1'

else Data ;

--else (others => 'Z') ;

RF_rd_addr <= Rx when ((I(2) or I(3)) and T(1)) = '1'

else Ry when ( (I(1) and T(1) ) or ((I(2) or I(3)) and T(2)) ) = '1'

else ( others => '0' ) ;

RF_wr_addr <= Rx when (((I(0) or I(1)) and T(1)) or ((I(2) or I(3)) and T(3))) = '1'

else ( others => '0' ) ;

RF_wr_en <= '1'

when (((I(0) or I(1)) and T(1)) or ((I(2) or I(3)) and T(3))) = '1'

else '0' ;

--Debug signals

debug_T <= T;

debug_I <= I;

debug_FuncReg <= FuncReg;

debug_R0 <= RF(0);

debug_R1 <= RF(1);

debug_R2 <= RF(2);

debug_R3 <= RF(3);

debug_extern <= Extern;

end RegFileBehavior;

library ieee;
use ieee.std_logic_1164.all;

entity test_proc is

end test_proc;

architecture behav of test_proc is

component proc is

port (Data : in std_logic_vector(7 downto 0);

Reset, w : in std_logic;

Clock : in std_logic;

F, Rx, Ry : in std_logic_vector(1 downto 0);

Done : buffer std_logic;

BusWires : inout std_logic_vector(7 downto 0);

debug_T, debug_I : out std_logic_vector(3 downto 0);

debug_FuncReg : out std_logic_vector(1 to 6);

debug_R0, debug_R1, debug_R2, debug_R3 : out std_logic_vector(7 downto 0);

debug_extern : out std_logic) ;

end component;

signal Data,BusWires : std_logic_vector(7 downto 0);

signal Reset, w, Clock, Done : std_logic;

signal F, Rx, Ry : std_logic_vector(1 downto 0) := ( others=>'0');

signal debug_T, debug_I : std_logic_vector(3 downto 0);

signal debug_FuncReg : std_logic_vector(1 to 6);

signal debug_R0, debug_R1, debug_R2, debug_R3 : std_logic_vector(7 downto 0);

signal debug_extern : std_logic;

constant boundT : time := 500 ns ;

-- for uut: proc use entity work.proc( Behavior ) ;

-- for uut: proc use entity work.proc( RegFileBehavior ) ;

begin

uut: proc port map(Data,Reset,w,Clock,F,Rx,Ry,Done,BusWires,debug_T,debug_I, debug_FuncReg,

debug_R0, debug_R1, debug_R2, debug_R3, debug_extern);

clk_process: process

variable varT : time := 0 ns ;

begin

Clock <= '0';

wait for 10 ns;

Clock <= '1';

wait for 10 ns;

varT := varT + 20 ns ;

-- assert ( varT <= boundT ) report "TimeUp" severity failure ;

if ( varT > boundT ) then wait ; end if ;

end process;

process

begin

--resetting the microprocessor(Mandatory)

reset <= '1';

--Loading data to R0(i.e. Rx)

wait for 40 ns;

w <= '1';

reset <= '0';

F <= "00";

Rx <= "00";

Data <= "00000101";

wait for 20 ns;

w <= '0';
--Loading data to R1(i.e. Rx)

wait for 60 ns;

w <= '1';

F <= "00";

Rx <= "01";

Data <= "00000011";

wait for 20 ns;

w <= '0';

--Adding R0(i.e Rx) to R1(i.e. Ry) and saving the result to R0(i.e. Rx)

wait for 60 ns;

w <= '1';

F <= "10";

Rx <= "00";

Ry <= "01";

wait for 20 ns;

w <= '0';

--Moving the data from R0(i.e. Ry) to R3(i.e. Rx)

wait for 60 ns;

w <= '1';

F <= "01";

Ry <= "00";

Rx <= "11";

wait for 20 ns;

w <= '0';

--Substracting R1(i.e. Ry) from R3(i.e. Rx) and storing the result in R3(i.e. Rx)

wait for 60 ns;

w <= '1';

F <= "11";

Rx <= "11";

Ry <= "01";

wait for 20 ns;

w <= '0';
--Moving the data from R0(i.e. Ry) to R3(i.e. Rx)

wait for 60 ns;

w <= '1';

F <= "01";

Ry <= "11";

Rx <= "10";

wait for 20 ns;

w <= '0';

wait;

end process;

end behav;