NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA

DEPARTMENT OF COMP. SC. & ENGG.

END-SEM B.TECH/M.TECH (DUAL)/MSC AUTUMN EXAM NOV 2017
COURSE: COMPUTER SYSTEMS ARCHITECTURE (CS-442)); DURATION: 3 HOURS; FULL MARKS: 50
INSTRUCTION: Answer All Questions. All parts of a question (a, b, etc.,) should be answered at one place.
Answer should be brief and to-the-point and be supplemented with neat sketches. Unnecessary long answers
may result in loss of marks. Any missing or wrong data may be assumed suitably giving proper justification.
Q. No. Description MARKS
1(a) How do you compute the maximum size of main memory in a computer system? [1X10]
(b) Write the formulae for finding average access time of non-random access memory.
(c) Specify two types of memory interleaving. Which is better? Justify.
(d) Write two characteristics of storage devices and explain their meaning.
(e) Differentiate between MAR and MBR. How they are different from PC?
(f) Differentiate between ASCII and EBCDIC. Write their usage in a computer.
(g) What is the use of index register and displacement value?
(h) Which type of computer architecture uses the split cache as its cache memory?
(i) Differentiate between write-through and write back policy in cache memory.
(j) What is the use of TLB? How it is different from page table base register?
2(a) Differentiate between opcodes and operands in an instruction. Write the different [5+5]
phases and the requisite hardware stages for each phase for executing an
instruction. Draw the instruction cycle state diagram considering the arrival of
interrupts.

(b) Consider an ISA having 120 instructions which are categorized into 4 types of
instructions such as 8 instructions of type 1, 16 instructions of type 2, 32
instructions of type 3 and 64 instructions of type 4. The number of bits allocated to
each type of instruction is 5 bits for type 1, 7 bits for type 2, 6 bits for type 3 and 8
bits for type 4 respectively. Compute the average size of the instruction. What are
the advantages and disadvantages of using fixed size opcodes instead of variable
size opcodes?

3(a) The amount of time required to read a block of data from a disk into memory is [5+5]
composed of seek time, rotational latency, and transfer time. Define each of these
terms. Assume that the disk system has 10 disks and each disk has two surfaces.
The cylinder in a disk system is defined as the set of corresponding tracks of every
disk surface. The outer surface of the first and last disk is not recorded with any
data. If the magnetic disk has 100 cylinders, each containing 10 tracks of 10
sectors in each track, and each sector in each track can contain 128 bytes, what is
the maximum capacity of the disk in bytes, kilobytes and megabytes? If the
diameter of each cylinder is 10 cm, what is the disk density in Mega bits per cm?

(b) Differentiate between moving and fixed head disk system? How virtual memory is
different from physical address space? Illustrate the address translation process
with the help of a diagram.
4(a) Consider the main memory of capacity 64 KB and 1 MB respectively for two [4+4+2]
different machines namely machine 1 and machine 2. Compute the total number of
address lines required to address the entire physical address space of each of the
machines. If the number of data lines is 8 and 16 for both machine 1 and machine

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 2, is it possible to use a common bus that can be shared as both address and data?
Write at least two advantages and two disadvantages to support sharing of address
and data lines.

(b) Illustrate the different types of placement policies for cache memory with
examples. Illustrate FIFO & LRU cache replacement algorithm using the following
sequence of CPU references: A-Miss, B-Miss, C-Miss, A-Hit, D-Miss, E-Miss, A-
Hit, D-Hit, C-Hit, F-Miss. Compute the hit ratio in both FIFO and LRU? Which
algorithm gives better hit ratio and why?

(c) A given memory chip has 12 address pins and 8 data pins. How many locations
can be addressed? Represent the address range using hexadecimal notation.

5(a) What are the properties of pipelining? Consider a non-pipelined machine with 6
execution stages of lengths 50 ns, 50,ns, 60ns, 60ns, 50ns, 50ns. Suppose we
introduce pipelining on this machine without considering any stalls. Assume that
when introducing pipelining, the clock skew adds 5ns of overhead to each
execution stage. What is the instruction execution time (or latency) on the non-
pipelined and pipelined machine? How much time does it take to execute 100
instructions in both non-pipelined and pipelined machine? What is the speedup [4+4+2]
obtained from pipelining?

(b) Consider the following sequence of statements to be executed on a computer that

supports pipeline having five phases such as IF, ID, IE, OF, SR.

A = B + C; D = A-F; E = G-H;

Write the assembly language code for these statements and identify the type of
pipeline hazards. Explain clearly the actions that are needed to avoid pipeline stalls
in your scheduled code. Reorder the sequence of code such that the number of
pipeline stalls can be minimized.

(c) What are the different pipeline hazards ? Which of these hazards will incur
maximum penalty as compared to other hazards?

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