SMART PATTERN RECOGNITION SYSTEM FOR POWER

MINIMIZATION IN IoT SENSOR NODES

Submitted by
BAKYALAKSHMI P 15EC201
PORSELVI S 15EC206
PRATHEBA M 15EC139
SHERLINE HEYNAA 15EC150

Under the Guidance of

DR. M. THATCHAYANI

BACHELOR OF TECHNOLOGY

SEVENTH SEMESTER

PHASE -1 : FINAL REVIEW

for

EC124 PROJECT WORK

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PONDICHERRY ENGINEERING COLLEGE
PUDUCHERRY – 605 014
DEC - 2018
 BONAFIDE CERTIFICATE

Certified that this project report, “SMART PATTERN RECOGNITION

SYSTEM FOR POWER MINIMIZATION IN IoT SENSOR NODES” is the
bonafide work done by BAKYALAKSHMI P. [15EC201], PORSELVI S. [15EC206],
PRATHEBA M. [15EC139], SHERLINE HEYNAA [15EC150] sixth semester
B.Tech class of Electronics and Communication Engineering in the project phase-1
during the year 2018-2019.

HEAD OF THE DEPARTMENT FACULTY INCHARGE

Dr. M. TAMILARASI DR. M. THATCHAYANI

Submitted for the practical exam held on ____________________

 ACKNOWLEDGEMENT

The successful completion of the project is indeed practically incomplete without

the mention of all those people who greatly supported and encouraged us throughout the
project. I feel grateful to our guide Dr. M. THATCHAYANI, Professor, Department of
Electronics and Communication Engineering, Pondicherry Engineering College, for her
encouragement and support. She has been a source of valuable guidance, suggestions and
kindness during the course of project work.

I would like to express my sincere thanks to Dr. P. DANANJAYAN, Principal,

and Pondicherry Engineering College for providing the college facilities for the
completion of this project work.

I would like to express my heartfelt gratitude to Dr. M. TAMILARASI,

Professor and Head, Department of Electronics and Communication Engineering,
Pondicherry Engineering College for providing Department facilities and guidance,
which enabled us to complete this project work.

I feel obliged to thank the review by the panel members DR.G.NAGARAJAN,

Professor, DR. R. GUNASUNDARI, Professor, DR. D. SARASWADY, Professor,
Dr.S.BATMAVADY, Professor, of the Electronics and Communication Engineering
Department, for their support, encouragement and guidance.

We express our deep sense of gratitude to all the teaching and non-teaching staffs
of our Department and to our friends for their support and encouragement during the
entire course of this dissertation work. We also express our warm regards to our parents
who motivated us.
BAKYALAKSHMI
PORSELVI
PRATHEBA
SHERLINE HEYNAA
 ABSTRACT

High-precision and continuous acquisition are both desirable features of IoT

sensor nodes, as well as low cost and integrated form factor to enable large scale
deployment. However, as target data are often sparse in time, considerable energy is
wasted in acquiring and processing uninformative data. The common approach is to
dynamically duty-cycle the HPS to a power-saving mode, e.g., to a sleep mode or to a
power-gating mode, when high precision is not needed. The toggling of the HPS mode is
controlled by an always-on wake-up circuit (WUC) responsible to wake-up the HPS from
the power-saving mode when full precision data is required. However, a simple
threshold-based WUC that only compares the input signal to a voltage level is often not
suitable to discriminate the inception of data patterns. Such systems may yield into many
false positive(FP) events and ultimately in high power consumption as the HPS is woken
up unneccessarily. Hence, more advanced signal processing must be embedded close to
the sensor to correctly identify the events of interest. Being always-on,substantial effort is
devoted to lower the power consumption of the WUC. Circuits with advanced
classification capabilities that could be used as WUC’s only recently appeared in
scientific literature in search of innovative ways to lower HPS based IoT sensing nodes
power consumption.Most implementations are based on alternative architectures and are
designed to cover a single specific application only, thus lacking the flexibility to cover
different IoT applications.Due to the intrinsic real-world signal variability, e.g.,caused by
the source-to-source mis-match or same-source variations over time, embedding
cognition in the WUC increases the classification capabilities in case of alike signals.
This can further relax analog precision requirements as analog non-idealities are
included in the training loop and compensated for.To practically embed cognition in the
WUC, a flexible and programmable classifier model which can be used to real-time
discriminate the patterns of interest is required. The objective of this project is to develop
a smart digital pattern recognition system for the wake-up circuit in IoT sensor nodes.
Machine learning based classifier will be used to determine the parameters of the wake-
up circuit. The proposed solution is expected to be applicable to systems with different
sensors and wake-up patterns.
 CONTENTS

CHAPTER TITLE PAGE NO.

BONAFIDE CERTIFICATE ii
ACKNOWLEDGEMENT iii
ABSTRACT iv
LIST OF FIGURES viii
LIST OF SYMBOLS ix
LIST OF ABBREVATION x
1 INTRODUCTION 01
1.1 Introduction 01
1.2 scope 02
1.3 Review of the existing system 03
1.4 shortcomings of the exisiting system 04

1.5 literature survey 05

1.6 objective 05

1.7 organization 05
2 PROPOSED MODEL 06
2.1 Introduction 06
2.2 overview 06
2.3 ECG pattern recognition 06
2.4 structure of ecg signal 07
2.5 block diagram 08
2.6 working
2.7 LC-ADC
 2.8 digital pattern recognition
3 SOFTWARE CODING
4 4.1 Simulation results
4.2 conclusions
4.3 future scope
 LIST OF FIGURES

FIGURE NO. NAME OF THE FIGURE PAGE NO.

2.1 BLOCK DIAGRAM 03
2.2 LC-ADC 04
2.3 LC ADC-SIGNAL 07
3.1 INPUT SIGNAL 08
3.2 HIGH PEAK OUPUT 11
3.3 LOW PEAK OUTPUT 13
3.4 CLASSIFIED OUTPUT 14
3.5 POWER CONSUMPTION 15
 CHAPTER 1

1.1 INTRODUCTION

INTERNET-OF-THINGS (IoT) sensor nodes are the key interfaces to the

physical world enabling sense-making and insight extraction from the sensed data . High-
precision, continuous acquisition, low cost and integrated form factor are the most
indispensable features of IoT sensor nodes to enable large scale deployment. However, as
target data are often sparse in time, considerable energy is wasted in acquiring and
processing uninformative data. Hence, A smart pattern recognition based system which
wakes up the high precision system during data acquisition has been proposed.

1.2 SCOPE

With the increase in Iot applications day by day, optimization of IoT applications
is required in terms of power consumption, area, size and speed of operation. IoT
senosors being continuously on leads to high power consumption and leakage of power
over a gradual course of time. As target data are often sparse in time, the high precision
system is duty cycled to a power-saving mode, e.g., to a sleep mode or to a power-gating
mode, when high precision is not needed. The toggling of the HPS mode is controlled by
an always-on wake-up circuit (WUC) responsible to wake-up the HPS from the power-
saving mode when full precision data is required. The high precision system is toggled to
on state when the pattern matches the target pattern stored thereby minimizing power
consumption.

1.3 REVIEW OF THE EXISTING SYSTEM

The exisiting system of pattern recognition system in IoT sensor nodes consume a
large amount of power, nearly 100 mW. Earlier, Threshold based WUC were developed
but it had poor discrimination capabilities which led to misdetected events
Hence, a cognitive based WUC architecture consisting of LC-ADC for signal
preprocessing and feature extraction and trainable digital pattern recognition circuit
for efficient prediction capabilities is being proposed.

1.4 SHORTCOMINGS OF THE EXISTING SYSTEM

 High Power consumption
 Poor classsification abilities
 Application specific

1.5 LITERATURE SURVEY

The basic idea of this project is obtained from the following papers,

Sl. Title of the paper Journal/ Technique Issues

No. Conference employed

1. Always on acoustic sensing S.Jeong This system Only stationary

and object recognition D.Slyvester employed ADC sound signals
microsystem for 2017 for microphone can be
unattended ground sensor output signal distinguished
nodes
 2. Normally off ECG SoC International This system Application
with non volatile MCU Journal of uses auto specific
and noise tolerant Computer corelation and
heartbeat detector Applications, template
Vol-170, matching
No.5, Pages technique
26-30, July
2015

3. 300 mw event driven ADC IEEE Moving Classifier

with real time QRS Transactions window model supports
detection for ECG sensor on sensors, implementation QRS detection
nodes June 2016. only

Table 1.1 literature survey

1.6 OBJECTIVE OF THE PROJECT

The objective of the project is to develop a Smart Digital Pattern Recognition
System based Wake-Up Circuit for duty-cycling the power-constrained Internet-of-
Things (IoT) sensor nodes. Whenever a true event, matching with the target pattern
occurs, the device must be woken up else the system must be sent to an idle state or a
sleep mode.

1.7 ORGANIZATION OF THE THESIS

The presentation of the thesis is organized as follows.
The current chapter introduces the project undertaken and presents an overview of
“Smart pattern recognition system for power minimization in IoT sensor nodes” along
with its Literature Survey.
Chapter 2 explains the system design, block diagram and the working of each
block.
Chapter 3 explains the software implementation, flow charts and algorithms used
in this project.
Chapter 4 shows the simulated result, conclusion and reference of this project.
 CHAPTER 2
PROPOSED SYSTEM IMPLEMENTATION

2.1 INTRODUCTION
Almost every IoT application require modules that are to be Always-On and
monitoring continuously. This increases power consumption as the system keeps
tracking the input data continuously. So a pattern recognition system which wakes up
only when accurate data matches the specified pattern has been proposed, thereby
minimizing the power consumption.
A low power consumption level crossing ADC and SVM machine learning
algorithm has been employed in the proposed system. This pattern recognition system has
several applications in IoT i.e., speech recognition, automatic medical diagnosis,
multimedia document recognition, heart beat pattern recognition, fingerprint recognition,
automatic face detection, finger snapping detection in touch phones etc. In this paper,
pattern recognition of pathologic heart beats and hand gesture pattern recognition has
been proposed.

2.2 OVERVIEW OF THE PROJECT

 The smart pattern recognition system has been proposed for mainly two
applications in this paper.
 Pathologic ECG pattern recognition(PHASE- I)
 Accelerometer based hand gesture pattern recognition(PHASE- II)

2.2.1 Pathologic ECG pattern recognition system

ECG is the standard tool for monitoring and diagnosing cardiac problems by
measuring electrical activity of the heart. ECG is a graphical representation of electrical
activity of the atrial and ventricles, which are responsible for repolarization and
depolarization. It contains clinical information of heart. Pathologic ECG dataset is trained
and the required parameters are determined. Unlabeled ECG dataset is tested with respect
to the trained abnormal ECG dataset and are classified as normal or pathologic. The
power consumed and the speed of operation is also determined.

2.2.2 Accelerometer based hand gesture pattern recognition

Hand-gesture recognition application captures and records hand gestures like
finger snapping on a device and/or object, typically by a human user or operator. It is
mainly used in smart phones, touch devices, portable smartwatches,etc. The finger
snapping gesture is selected as target class of interest (positive class), because of its
potential use as trigger event for data acquisition. Finger snapping can be easily
discriminated against low energy gestures, e.g., writing, keyboard typesetting,
handshaking, touchscreen navigation,etc. However it is more challenging to keep the
number of FP events low when similar energy gestures happens. The second phase of our
project deals with hand gesture pattern recognition using SVM algorithm. The data is
tested based on the trained data and hand gestures are detected.

2.3 ECG PATTERN RECOGNITION

2.3.1 ECG
In recent years, cardiovascular disease, including heart disease and stroke,
remains the leading cause of death around the world. Yet most heart attacks and strokes
could be prevented if some method of pre-monitoring and pre-diagnosing can be
provided. In particular, early detection of abnormalities in the function of the heart can
prevent life-threatening cardiac conditions and improve patient safety.
The ECG provides an analytical tool for detecting disorder of rhythm and change
in the morphological pattern. This typically is centered on the study of Pathalogic ECG
heatbeats(arrthymia), which can be any disturbance in the rate, regularity and site of
origin or conduction of the cardiac electric impulse.
Ventricular fibrillation (VF) is one of the main causes of sudden cardiac death. It
is a type of arrhythmia that causes the heart to beat chaotically, rendering it unable to
pump blood. VF is usually preceded by ventricular tachycardia (VT), which is another
type of arrhythmia that also constitutes a medical emergency. Ventricular arrhythmia is an
abnormal ECG rhythm and is accountable for 75%–85% of unexpected deaths in persons
with heart tribulations unless treated within seconds. The goal of this research is to
investigate the possibility of predicting ventricular arrhythmias from an
electrocardiogram (ECG) signal, which is a measurement of cardiac electrical
commotion.
In a conventional 12-lead ECG, ten electrodes are placed on the patient's limbs
and on the surface of the chest. The overall magnitude of the heart's electrical potential is
then measured from twelve different angles ("leads") and is recorded over a period of
time (usually ten seconds). In this way, the overall magnitude and direction of the heart's
electrical depolarization is captured at each moment throughout the cardiac cycle.[5] The
graph of voltage versus time produced by this non invasive medical procedure is
an electrocardiogram.

2.3.2 STRUCTURE OF ECG SIGNAL

ECG signal has a time varying morphological characteristics named as P, T waves

and QRS complex.
 Fig.2.1 ecg signal

Normal rhythm produces four entities

 The P wave represents atrial depolarization.

 The QRS complex represents ventricular depolarization.
 The T wave represents ventricular repolarization.
 The U wave represents papillary muscle repolarization.

However, the U wave is not typically seen and its absence is generally ignored.
Changes in the structure of the heart and its surroundings (including blood composition)
change the patterns of these four entities.

These waves will be of different amplitudes. Among these QRS complex wave
has highest amplitude and specific shape and is the mid to high frequency wave. P and Q
are the low frequency waves. Extracting the information in the P-QRS-T waves is called
feature extraction and it involves in determining the amplitude and intervals in the ECG
signals. Variations in length and width of the QRS complex appear for short period of
time and continue for indefinite periods of time

2.3.3 BLOCK DIAGRAM OF SMART PATTERN RECOGNITION SYSTEM

 Fig.2.2 block diagram

2.3.4 WORKING OF THE MODEL

The Smart pattern recognition system architecture consists of
1) a LC-ADC for non-uniform sampling analog-to-digital conversion and feature
Extraction
2) a digital pattern recognition (DPR) block for binary pattern classification.

The LC-ADC outputs a deltamodulated sample, once one of the internal analog
levels is crossed by the preamplified signal Vamp.. The LC-ADC is equivalent to a
combination of multiple comparators with 1 LSB spaced levels, similar to a flash-ADC
architecture, but with higher efficiency .
A sequence of delta-modulated samples of the LC-ADC are segmented, digitally
processed, and sequentially compared against programmable digital thresholds by the
DPR block which implements the binary classifier. If the target pattern stored in the DPR
block matches the pattern sought for in the input signal, then a wake-up line is asserted
which can be used to awake a duty-cycled HPS, triggering high-precision signal
processing.
 Fig.2.3 overall block diagram

A preliminary training is required to ”teach” the DPR digital thresholds to identify

the targeted signal. During the training phase, labeled positive and negative signals are
fed through both the preamplifier and the LC-ADC. The generated delta-modulated
samples are acquired and fed to the off-chip training algorithm that infers a set of
optimum DPR parameters, i.e., digital thresholds. Then, efficient real-time classification
is performed by the DPR on unlabeled, LCADC digitized signals.

2.3.5 LC-ADC
Asynchronous level-crossing sampling scheme is an approach which meets data
compression and feature extraction simultaneously.Under the scheme, the sampling rate
is directly proportional to the activity of the input signal and no power is wasted for
sampling, converting, and processing the useless data in the inactive parts of the signal.
This is well suited for ECG signal due to its sparse and burst-like nature.

Fig.2.1 LCADC signal

 In level-crossing ADCs, the input signal is compared with predefined thresholds
and the output of the comparators are combined to generate a clock signal. The latter is,
therefore, a function of amplitude, slope and frequency of the input Signal. This leads to a
non-uniformly spaced samples in time. The sampling rate adapts to the rate of change of
the input signal. Thus, the average sampling rate will be lower than that required for
conventional Nyquist ADCs, thereby making the ADC to asynchronous in nature.

The input voltage is compared with two reference voltages, VA and VB, generated
from the sliding window reference generator in the continuous time domain. If VIN > VB,
then UP=l, DOWN=O and a clock (CLK) will be generated in order to activate the ADC,
which, in turn, will provide the digital output corresponding to the analog input signal.
Similarly, if VIN < VA then UP=O, DOWN=l and CLK =1. However, if VA < VIN
< VB, then the clock signal is not generated and the ADC remains off for that period of
time, i.e. the clock is generated only and if the input crosses any of the threshold values
within a given thresholds range.
The generated clock pulse is fedback to the reference generator, where the
reference voltages VA and VB are slided up or down by I Least Significant Bit (LSB)
depending on the slope of the input signal. Thus, the input signal again lies in the
thresholds range and both UP and DOWN signals will be logic zero thereby making
CLK=O. The clock is automatically turned off once the input again falls within the
current thresholds range.
It is important to note that, during this operation, the input should not change by
more than I LSB. Thus, the delay of the circuit from clock generation to the shift in the
reference voltages should be less than the time required for the input signal to change by
1 LSB.
Thus, they are immune to metastable behaviour, reduces electromagentic
interferences, speed and saves power. The ADC conversion time is mainly dominated by
the signal tracking time, comparator speed, and digital propagation delay.

2.3.6 DIGITAL PATTERN RECOGNITION BLOCK-SVM ALGORITHM

The digital pattern recognition block contains the SVM machine learning
algorithm. Support Vector Machine (SVM) is a supervised machine learning algorithm
which can be used mostly used in classification problems.
Support Vectors are simply the co-ordinates of individual observation. Support
Vector Machine is a frontier which best segregates the two classes (hyper-plane/ line).
The basic of SVM involves the adoption of a nonlinear kernel function to
transform input data into a high dimensional feature space, which is easier to separate
data rather than at the original input space. Thus, depending on input data, the iterative
learning process of SVM will finally devise optimal hyper planes with the maximal
margin between each class in a high dimensional feature space. Hence, the maximum
margin hyper planes will be the decision boundaries for distinguishing different data
clusters. Therefore, the larger distance between hyper planes and group data will result in
better classification performance.
An SVM generates parallel partitions by generating two parallel lines for each
category of data in a high-dimensional space and uses almost all attributes. It separates
the space in a single pass to generate flat and linear partitions. It Divides the 2 categories
by a clear gap that should be as wide as possible. This partitioning is done by a plane
called hyperplane.
An SVM creates hyperplanes that have the largest margin in a high-dimensional
space to separate given data into classes. The margin between the 2 classes represents the
longest distance between closest data points of those classes.
 The larger the margin, the lower is the generalization error of the classifier. After
training map the new data to same space to predict which category they belong to. The
new data is categorized into different partitions by training data.
SVM provides the largest flexibility. SVMs are like probabilistic approaches but
do not consider dependencies among attributes.

CHAPTER 3
SOFTWARE DESCRIPTION AND CODING

3.1 GENERATION OF NUMERIC DATA FILE FROM DATA SET

Module to read ECG DATA which is scanned from images

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.math_complex.all;
use ieee.numeric_std.all;

entity read_file is
port(clk,clr: in std_logic;
eone_out,rfzx,read6: out real);
end read_file;

ARCHITECTURE beha OF read_file IS

signal bin_value : std_logic_vector(3 downto 0):="0000";

signal file_dat,sqr_file_dat : real;
signal outdata: real;
signal test_sig : std_logic;
signal Nsamp: real;
signal onebyn,eone,eone_value: real;
signal file_out: real;

type array_type1 is array (0 to 10) of real;

BEGIN

Nsamp<=10.0;
onebyn<=(1.0/Nsamp);

--Read process

process
file file_pointer : text;
variable line_content : real;
variable line_num : line;
variable add_data : real:=0.00;
variable j : integer := 0;
variable char : character:='0';
begin
--Open the file read.txt from the specified location for reading(READ_MODE).
file_open(file_pointer,"C:\read5.txt",READ_MODE);

while not endfile(file_pointer) loop --till the end of file is reached continue.
readline (file_pointer,line_num); --Read the whole line from the file
--Read the contents of the line from the file into a variable.
READ (line_num,line_content);

file_dat<= line_content;
 wait for 5 ns;
sqr_file_dat<= file_dat*file_dat;

wait for 1 ns;

add_data := add_data+sqr_file_dat;

wait for 7 ns; --after reading each line wait for 7 ns.

outdata<=add_data;

end loop;
file_close(file_pointer); --after reading all the lines close the file.
wait;
end process;

t1: process
begin
wait for 110 ns;
test_sig<='0';
wait for 110 ns;
test_sig<='1';
end process t1;

t2:process(clr,test_sig)
begin
if clr='1' then
eone<=0.000;
elsif rising_edge(test_sig) then
eone<=(onebyn*outdata);
end if;
end process t2;

eone_value <=eone;
eone_out <=eone;

rfzx<= (eone_value**(0.5));

file_out<=(eone_value**(0.01));
read6<=file_out;

end beha;
3.2 SIGNAL ANALYSIS-TRAINING CODE

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.math_complex.all;
use ieee.numeric_std.all;

entity signal_analysis is
port(clk,clr : in std_logic;
elow1,ehigh1,str_low1,str_high1,fmax1,fmin1,far1:in real;
str1 : in real;eone_out1,rfzx1: in real);
end signal_analysis;

architecture behave of signal_analysis is

signal ap_enab,nr_enab,ma_enab,ra_enab,dclr,d2clr : std_logic;
signal status1 : string(1 to 5);
signal status2 : string(1 to 11);
signal status3 : string(1 to 16);
signal status4 : string(1 to 19);
signal fs: std_logic;

begin

--Benign LOW BREATH * PREASURE

ap: process(eone_out1,elow1,clr)
begin
if clr='1' then
ap_enab<='0';
status1<="NORML";
else if (elow1>eone_out1) then
ap_enab<='1';
status1<="LOWBP";
end if;
end if;
end process ap;

--BODY BLOOD PRESSURE

sigt:process
begin
wait for 300 ns;
fs<='0';
wait for 300 ns;
fs<='1';
end process;

mbt: process(eone_out1,elow1,str1,str_high1,rfzx1,fmin1,far1,clr)
begin
if clr='1' then
nr_enab<='0';
status2<="NORML******";

else if (eone_out1>ehigh1) then

if (str1>str_high1) then
if (rfzx1>fmin1) then
if (far1>fmin1)then
nr_enab<='1';
status2<="HIGH-BP-DET";

end if;
end if;
end if;
end if;
end if;
end process mbt;

dclr<= clr after 1 ns;

--Secondary (Metastatic) Malignant Brain Tumors

mmbt: process(eone_out1,elow1,clr,nr_enab)
begin
if dclr='1' or nr_enab='0' then
nr_enab<='0';
status3<="*****NORML******";

else if (elow1<eone_out1) then

else if (str1<str_low1) then

nr_enab<='1';
status3<="MILD-ATTACK*****";
end if;
end if;
end if;
end process mmbt;

d2clr<= dclr after 1 ns;

pg: process(eone_out1,elow1,d2clr,str1,str_low1,far1,fmax1,rfzx1,fmin1,nr_enab)
begin
if d2clr='1' or nr_enab='0' then
nr_enab<='0';
status4<="*****NORML*********";

else if (elow1<eone_out1) then

if (str1<str_low1) then
if (far1>0.0) then
if (fmax1>rfzx1) then

nr_enab<='1';
status4<="VENTRIC-ARYTHMIA***";

end if;
end if;
end if;
end if;
end if;
end process pg;

end behave;
3.3 CLASSIFICATION ALGORITHM

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.math_complex.all;
use ieee.numeric_std.all;

entity classification_alg is
port(clk,clr: in std_logic;fsample : in real;
elow,ehigh,str_low,str_high,fmax,fmin,far:out real;
str : out real);
end classification_alg;

architecture behave of classification_alg is

signal angle: real;
signal temp_ver: real;
begin

angle<=30.0;
temp_ver<=(30.0/360);
str<=1.0;

cont_lat:process(clk,clr)
begin
if clr='1' then
elow<=0.0;
ehigh<=0.0;
str_low<=0.00;
str_high<=0.00;
fmin<=0.00;
fmax<=0.00;

elsif rising_edge(clk) then

elow<=2.0;--200.00
ehigh<=5.0;--500.00
str_low<=0.7;
str_high<=0.9;
fmin<=0.2;
fmax<=0.7;
end if;
end process cont_lat;

plat:process(clk,clr)
begin
if clr='1' then
far<= 0.00;
elsif falling_edge(clk) then
far<= fsample*temp_ver;
end if;
end process plat;

end behave;

3.4 TOP MODULE

--*****************************************************************
-- Design of ECG signal analysis & classificatin algorithm WITH low voltage from 0.25
V TO 10.00 V
-- Language : VHDL
-- Tool : ModelSim 6.3 / any latest
--*****************************************************************

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.math_complex.all;
use ieee.numeric_std.all;

entity top_module is
port(clk,clr:in std_logic;fsample: in real;
read6: out real);
end top_module;

architecture behave of top_module is

-- COMPONENT declaration of sub modules
component read_file is
port(clk,clr: in std_logic;
eone_out,rfzx,read6: out real);
end component;

component classification_alg is
port(clk,clr: in std_logic;fsample : in real;
elow,ehigh,str_low,str_high,fmax,fmin,far:out real;
str : out real);
end component;

component signal_analysis is
port(clk,clr : in std_logic;
elow1,ehigh1,str_low1,str_high1,fmax1,fmin1,far1:in real;
str1 : in real;eone_out1,rfzx1: in real);
end component;

signal elow_pm,ehigh_pm,str_low_pm,str_high_pm,fmax_pm,fmin_pm,far_pm: real;

signal str_pm : real;
signal eone_out_pm,rfzx_pm ,read6_pm: real;

begin

-- PORT MAPPING of sub modules

 m1:read_file port map(clk,clr,eone_out_pm,rfzx_pm,read6);
m2:classification_alg port
map(clk,clr,fsample,elow_pm,ehigh_pm,str_low_pm,str_high_pm,fmax_pm,fmin_pm,far
_pm,str_pm);
m3:signal_analysis port
map(clk,clr,elow_pm,ehigh_pm,str_low_pm,str_high_pm,fmax_pm,fmin_pm,far_pm,str_
pm,eone_out_pm,rfzx_pm);

end behave;

CHAPTER 4
SIMULATION RESULTS

4.1 RESULTS

This Chapter deals with the simulated results obtained from the project. The dataset is
trained and fed into the system. Random dataset is then fed and signals are classified as per
the training algorithm as normal and abnormal signals.
Abnormal ECG dataset with high peaks
Abnormal ECG dataset with high peaks
CLASSIFIED SIGNAL
POWER CONSUMPTION:
 By this methodology of using LC-ADC and SVM ALGORITHM, power
consumption is reduced to approximately 48 mW.

AREA OCCUPIED:

SYNTHESIS REPORT
Release 12.2 - xst M.63c (nt64)

Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.25 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.25 secs

--> Reading design: classification_alg.prj

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Parsing

3) HDL Elaboration

4) HDL Synthesis

4.1) HDL Synthesis Report

5) Advanced HDL Synthesis

5.1) Advanced HDL Synthesis Report

6) Low Level Synthesis

7) Partition Report

8) Design Summary
 8.1) Primitive and Black Box Usage

8.2) Device utilization summary

8.3) Partition Resource Summary

8.4) Timing Report

8.4.1) Clock Information

8.4.2) Asynchronous Control Signals Information

8.4.3) Timing Summary

8.4.4) Timing Details

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : "classification_alg.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "classification_alg"

Output Format : NGC

Target Device : xq6slx75l-1L-cs484

---- Source Options

Top Module Name : classification_alg

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : LUT

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Shift Register Extraction : YES

ROM Style : Auto

Resource Sharing : YES

Asynchronous To Synchronous : NO

Shift Register Minimum Size :2

Use DSP Block : Auto

Automatic Register Balancing : No

---- Target Options

LUT Combining : Auto

Reduce Control Sets : Auto

Add IO Buffers : YES

Global Maximum Fanout : 100000

Add Generic Clock Buffer(BUFG) : 16

Register Duplication : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Auto

Use Synchronous Set : Auto

Use Synchronous Reset : Auto

Pack IO Registers into IOBs : Auto

Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed

Optimization Effort :1

Power Reduction : NO

Keep Hierarchy : No

Netlist Hierarchy : As_Optimized

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator :/

Bus Delimiter : <>

Case Specifier : Maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

DSP48 Utilization Ratio : 100

Auto BRAM Packing : NO

Slice Utilization Ratio Delta :5

=========================================================================
=========================================================================

* HDL Parsing *

=========================================================================

Parsing VHDL file "\Users\Roger\Desktop\roger\kan\mod1.vhd" into library work

Parsing entity <classification_alg>.

Parsing architecture <behave> of entity <classification_alg>.

=========================================================================

* HDL Elaboration *

=========================================================================

Elaborating entity <classification_alg> (architecture <behave>) from library <work>.

WARNING:HDLCompiler:1127 - "\Users\Roger\Desktop\roger\kan\mod1.vhd" Line 21:

Assignment to angle ignored, since the identifier is never used

=========================================================================

* HDL Synthesis *

=========================================================================

Synthesizing Unit <classification_alg>.

Related source file is "/users/roger/desktop/roger/kan/mod1.vhd".

Register <elow_dummy_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <elow_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <elow_dummy> equivalent to <ehigh_dummy> has been removed

 Register <fmax_dummy_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <fmax_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <fmax_dummy> equivalent to <ehigh_dummy> has been removed

Register <fmin_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <fmin_dummy> equivalent to <ehigh_dummy> has been removed

Register <str_high_dummy_dummy_dummy_dummy> equivalent to <ehigh_dummy> has

been removed

Register <str_high_dummy_dummy_dummy> equivalent to <ehigh_dummy> has been

removed

Register <str_high_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <str_high_dummy> equivalent to <ehigh_dummy> has been removed

Register <str_low_dummy_dummy_dummy> equivalent to <ehigh_dummy> has been

removed

Register <str_low_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <str_low_dummy> equivalent to <ehigh_dummy> has been removed

Register <ehigh_dummy_dummy_dummy_dummy_dummy_dummy> equivalent to

<ehigh_dummy> has been removed

Register <ehigh_dummy_dummy_dummy_dummy_dummy> equivalent to <ehigh_dummy>

has been removed

Register <ehigh_dummy_dummy_dummy_dummy> equivalent to <ehigh_dummy> has been

removed

Register <ehigh_dummy_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <ehigh_dummy_dummy> equivalent to <ehigh_dummy> has been removed

Register <elow_dummy_dummy_dummy_dummy> equivalent to <ehigh> has been removed

Register <elow> equivalent to <ehigh> has been removed

Register <fmax_dummy_dummy_dummy_dummy> equivalent to <ehigh> has been removed

Register <fmax> equivalent to <ehigh> has been removed

Register <fmin_dummy_dummy_dummy> equivalent to <ehigh> has been removed

 Register <fmin> equivalent to <ehigh> has been removed

Register <str_high_dummy_dummy_dummy_dummy_dummy> equivalent to <ehigh> has

been removed

Register <str_high> equivalent to <ehigh> has been removed

Register <str_low_dummy_dummy_dummy_dummy> equivalent to <ehigh> has been

removed

Register <str_low> equivalent to <ehigh> has been removed

Register <ehigh_dummy_dummy_dummy_dummy_dummy_dummy_dummy> equivalent to

<ehigh> has been removed

Found 1-bit register for signal <ehigh>.

Found 1-bit register for signal <ehigh_dummy>.

Found 32-bit register for signal <far>.

Found 32x32-bit multiplier for signal <n0021> created at line 52.

INFO:Xst:2840 - Register <ehigh<1:22>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <ehigh<23:23>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <ehigh<23:23>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <str_low<1:24>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <str_low<25:27>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <str_high<1:24>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <str_high<25:25>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <str_high<25:25>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.
INFO:Xst:2840 - Register <fmin<1:26>> in unit <classification_alg> has a constant value of 0
during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <fmin<27:27>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <fmin<27:27>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <fmax<1:24>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <fmax<25:27>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <elow<1:23>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <elow<24:25>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

INFO:Xst:2840 - Register <elow<26:27>> in unit <classification_alg> has a constant value of 0

during circuit operation. The register is replaced by logic.

Summary:

inferred 1 Multiplier(s).

inferred 34 D-type flip-flop(s).

Unit <classification_alg> synthesized.

=========================================================================

HDL Synthesis Report

Macro Statistics

# Multipliers :1

32x32-bit multiplier :1

# Registers :3

1-bit register :2
32-bit register :1

=========================================================================

=========================================================================

* Advanced HDL Synthesis *

=========================================================================

WARNING:Xst - The specified part-type was not generated at build time. XST is loading the full
part-type and will therefore consume more CPU and memory.

Loading device for application Rf_Device from file '6slx75.nph' in environment

C:\Xilinx\12.2\ISE_DS\ISE\.

Loading device for application Rf_Device from file '6slx75.nph' in environment

C:\Xilinx\12.2\ISE_DS\ISE\.

4.2 CONCLUSIONS:

 Power consumption is reduced to 48 mW

 Speed is faster

 Better classification capabilities

4.3 FUTURE SCOPE:

Smart pattern recognition system can be further extended for any application. It is
basically designed for mutli application support. It can be further used for EEG pattern
classification, hand gesture recognition pattern recognition, face detection, etc.
4.4 REFERENCES

[1]. S. Jeong, Y. Chen, T. Jang, J.M. Tsai, D. Blaauw, H. Kim, and D. Sylvester,
“Always-On 12-nW Acoustic Sensing and Object Recognition Microsystem for
Unattended Ground Sensor Nodes,” IEEE J. Solid-State Circuits, 2017.

[2]. S. Izumi et al., “Normally Off ECG SoCWith Non-Volatile MCU and Noise
Tolerant Heartbeat Detector,” IEEE Trans. Biomed. Circuits and Syst., vol. 9, no.
5, pp. 641–651, October 2015.

[3]. N. Ravanshad, H. Rezaee-Dehsorkh, R. Lotfi and Y. Lian, “A LevelCrossing

Based QRS-Detection Algorithm for Wearable ECG Sensors,” IEEE J. Biomed.
Health Inform., vol. 18, no. 1, pp. 183–192, January 2014.

[4]. Y. Li, D. Zhao, and W. A. Serdijn, “A Sub-Microwatt Asynchronous Level-

Crossing ADC for Biomedical Applications,” IEEE Trans. on Biomed. Circuits
and Syst., vol. 7, no. 2, pp. 149–157, April 2013.

[5]. G. Rovere, S. Fateh, and L. Benini, “2.1 uW Event-Driven Wake-Up Circuit

Based on a Level-Crossing ADC for Pattern Recgnition in Healthcare”, IEEE
Biomed Circuits and Syst. Conf. (BioCAS), pp., 322-335, October 2017.

[6]. Giovanni Rovere, “A 2.2 uW Cognitive Always-ON Wake-Up Circuit for Event-
SS Driven Duty-Cycling of IoT sensor nodes”, IEEE Journal on Emerging and
Selected Topics in Circuits and Systems, DOI 10.1109/JETCAS.2018.2828505.

[7]. M. Alioto, “Enabling the Internet of Things from Integrated Circuits to

Integrated Systems”, Springer, 2017.

[8]. C.Perera, Azaslavsky, P.Christen and D. Georgakotoulos, “Context Aware

Computing for the Internet of Things: A Survey”, IEEE Commune.Surveys
Tut.,vol. 16,no. 1, pp. 414-454, January 2018.

[9]. N. Ravanshad, H. Rezaee-Dehsorkh,R. Lotfi and Y. Lian, “A Level-Crossing

Based QRS-Detection Algorithm for Wearable ECG Sensors”,IEEE J.
Biomed.Health Inform., vol. 18, no.1, pp. 183-192, January 2014.