MES Lab Manual

LAB MANUAL
MODELING OF ELECTRICAL SYSTEMS LAB
Department of Electrical Engineering

School of Engineering
Central University of Karnataka
Kadaganchi, Kalaburagi -585367
Lab Manual MODELING OF ELECTRICAL SYSTEMS
LIST OF EXPERIMENTS
S. No Name of the Experiment Page

No.
1 Simulation of dynamic response of parallel RLC circuit
2 Simulation of transient response of an RL circuit with AC
excitation
3 Determination of per unit parameters of a three phase bundled
conductor ac line
4 Transient simulation of a 500 kV single phase line
5 Simulation of a single-phase two-winding transformer
6 Determination of voltage and current ratios of the Delta-Wye
connected transformer
7 Simulating transformation of phase (abc) to dq0.
8 Simulation of a stationary reference dq0 model of a singly
excited three phase induction motor
9 Simulation of starting methods of three phase induction motor
10 Simulation of single phase induction motor
11 Simulation of three phase synchronous machine
12 Simulation of DC shunt generator
Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 2

EXPERIMENT-1
SIMULATION OF DYNAMIC RESPONSE OF
PARALLEL RLC CIRCUIT
OBJECTIVES:
1) To investigate dynamic response of parallel RLC circuit
EQUIPMENT & COMPONENTS:

1) MATLAB - SIMULINK
BACKGROUND
Consider the implementation and verification of the simple parallel RLC circuit
shown in Fig. 1.1. It has the following circuit equations:
Eq (1.1)
Eq (1.2)
Eq (1.3)
Fig 1.1 Parallel RLC circuit

Choosing the inductor current and capacitor voltage as state of the system, the
above circuit equation can be written in terms of the two states and the input
voltage as follows:
Eq (1.4)
PROCEDURE
1) For determining the analytical results that we will use to verify the
simulation, we will consider the transient response of the RLC
circuit to be a step function voltage.
2) Start up MATLAB and SIMULINK, double-click on the SIMULINK
file menu and use the open file command to select and open the S2
file containing the model of the parallel RLC circuit.
3) As shown in Fig. 1.1, the step voltage excitation is simulated by a
step input generator from the SIMULINK sources block library.
4) Check the connections of the various blocks in S2 to confirm that
the simulation agrees with the mathematical model given in Eqs.
1.4.
5) Fig. 1.2 shows the use of a floating scope, Scope2, to display the
variable iC, the selected input to the floating scope being indicated
by the little black square on the output line.
Fig. 1.2 SIMULINK Simulation of RLCcircuit.

Before we can run the simulation, we must first initialize the

circuit parameters to represent a circuit with Rs=50Ω, L=0.1H, and
c=1000µF. next we must set the desired initial condition of the system,
that is the initial value of the system states. The initial values of the
inductor current and capacitor voltage can be set by either directly
entering the desired initial value in the dialog boxes of the respective
integrators with inductor current and capacitor voltage as output, or by
using named variable in these dialog boxes and assigning these variables
desired initial values from the MATLAB command window. For this run,
set the initial values of the inductor current and capacitor voltage
directly to zero.
Finally we must choose the integration method to use and set the
start time, stop time, step size range , and error tolerance. All these are
to be specified under parameters of the simulation menu. For this run,
we select the Adams/Gear integration method, set the start time to zero,
the stop time to 0.5 seconds, the minimum step size to 0.1msec, the
maximum step size to 1 msec, and the error tolerance to 1e -5.
As shown in Fig. 1.2, the results are stored as the array y in the
MATLAB workspace. The variable values in y are stored column-wise in a
stacking order corresponding to the order of the multiplexed input. As
shown, the clock time will be stored in the first column of y,
corresponding values of iS in the second column, and so on.
Plot the values of iS, vC and iL at the first 0.5 second interval. A sample
output response of the RLC circuit with zero initial capacitor voltage and
inductor current set to a step input voltage of 100 V step applied at 0.05
sec is given in Fig. 1.3
% M-file for Exercise 2 RLC circuit simulation

% input parameters and initial conditions
% and plot results of simulation
Rs = 50; %Rs = 50 ohms
L = 0.1; %L = 0.1 Henry
C = 1000e-6; % C = 1000 uF
VS_mag = 100; % magnitude of step voltage Vs in Volts
tdelay = 0.05; % initial delay of step voltage in sec
vCo = 0; % initial value of capacitor voltage
iLo = 0; % initial value of inductor current
tstop = 0.5; % stop time for simulation
disp('run simulation, type ''return'' when ready to return')
keyboard
subplot(3,1,1)
plot(y(:,1),y(:,2))
title('source current')
ylabel('iS in A')
subplot(3,1,2)
plot(y(:,1),y(:,3))
title('capacitor voltage')
ylabel('vC in V')
subplot(3,1,3)
plot(y(:,1),y(:,4))
title('inductor current')
xlabel('time in sec.')
ylabel('iL in A')

OUTPUT WAVEFORMS
Fig. 1.3 RLC circuit response to a 100V step input vS.

EXPERIMENT - 2
SIMULATION OF TRANSIENT RESPONSE OF
AN RL CIRCUIT WITH AC EXCITATION
OBJECTIVES:
1) To investigate transient response of an RL circuit with AC excitation.

1) MATLAB – SIMULINK
BACKGROUND:
In this third exercise, we will examine the transient response of a simple RL
circuit to an ac voltage energization; in particular, we will look at the dc offset
in the response current from energizing at different points of the ac voltage
wave. The circuit and its SIMULINK simulation are shown in Fig 2.1.
Fig. 2.1 AC energization of an RL circuit.
The circuit equation for the RL circuit with an ac source is
For simulation purpose, the above equation is rearranged into its integral form:

The above integral equation is implemented in the SIMULINK file s3 using a

summer and an integrator. The ac voltage source is represented by a sinusoidal
signal source from the source library block. Set the circuit parameter values of
R=0.4Ω and L=0.04H, and set the initial values of the current to zero, the
magnitude of the sinusoidal signal source to 100v its frequency, ωs to 314
rad/sec, and its phase angle, θ, to Zero. select the ode45 or Linsim numerical
integration method and set the start time to zero, the stop time to 0.5sec, the
minimum step size to 1msec, the maximum step size to 10msec, and the error
tolerance to 1e-5. Run the simulation.
Repeat the run using two different values of θ, θ = Π/2 & θ=tan-1 ωsL/R.
Examine the simulated response of i(t) to determine whether the initial dc
offset, the decay of the dc offset, and the final steady state magnitude and
phase of i(t) agree with the corresponding values predicted from the following
analysis:
The complete response of the current to sinusoidal excitation of
Vpksin(ωst+ θ)u(t) may be expressed as
Where the time constant t is L/R, the impedance, Z, is √(R2+ωs2L2) and the
power factor angle,ϕ, is tan-1(ωsL/R). constant A can determined from the initial
condition of i(0)=0, that is
Thus
It is evident from the above expression that the current, i(t), will have some dc
offset when the circuit is being energized at a point of the wave other than at
θ = ϕ, and that the dc offset decays off at a rate equal to the L/R time constant
of the RL circuits.
Figure 2.2 shows the result for the case when the RL circuit with zero
initial inductor current is being energized with a sin wave voltage of 100sin314t
v. determine the value of the power factor angle of the RL circuit ϕ, use it in a
run where the sin wave voltage is set equal to 100sin(314t+ ϕ), and note the
initial offset in the response of i(t).

MATLAB PROGRAM
% M-file for Exercise 3 RL circuit simulation
% input parameters and initial conditions
R = 0.4; %R = 0.4 ohm
L = 0.04; %L = 0.04 Henry
we = 314; % excitation frequency in rad/sec
Vac_mag = 100; % magnitude of ac voltage Vac in Volts
iLo = 0; % initial value of inductor current
tstop = 0.5; % stop time for simulation
disp('run simulation, type ''return'' when ready to return')
keyboard
subplot(2,1,1)
plot(y(:,1),y(:,2))
title('ac excitation voltage')
ylabel('Vac in V')
subplot(2,1,2)
plot(y(:,1),y(:,3))
title('mesh current')
xlabel('time in sec.')
ylabel('i in A')
OUTPUT WAVEFORMS
Fig. 2.2 RL circuit response to ac excitation.

EXPERIMENT-3
DETERMINATION OF PER UNIT PARAMETERS OF A
THREE PHASE BUNDLED CONDUCTOR AC LINE
OBJECTIVES:
To investigate the per unit parameters of a three phase bundled conductor ac
line.

BACKGROUND:
In this project, we will first determine the per unit length parameter of a 60Hz,
345kv, three phase ac line with conductor arrangement as shown in Fig. 3.1.
next, we will compare the sending ends condition as determined using a series
RL and nominal Π with that of an equivalent Π circuit model of entire line,
160km long, delivered 120MW at 0.9 power factor lagging to a fixed receiving
end voltage, VR, of 345/√(3)∟00 kV. Finally we will examine the behavior of real
reactive power transfer through the same length of line when the angle and
magnitude of the voltage across the line are varied.
Relative accuracy of circuit models for different line lengths.

The line has conductor spacing of D12’ =7.772m and D1’2 = 6.858m. Each phase
is a bundle of two identically sized conductors, each of diameter 4.4755cm, an
ac resistance of 0.02896Ω/km, and a GMR of 1.6276cm.
The GMDs between any two of the bundled phase conductors are
Fig. 3.1 Three-phase bundled conductor line.
TABLE 3.1 SENDING END CONDITION

Thus, with full transposition, the GMD over a transposition cycle is
Run the ml m-file to determine the RLC parameters of the line, the ABCD
transmission matrices of the series RL, nominal Π, and equivalent Π circuit
models of the whole line. Table 3.2 shows sample results for the case where the
line length is 160km and the total power delivered to the receiving end is
120MW at 0.9 power factor lagging.
Modify the data in the M-file for the case where the line length is 240
instead of 160km. compare the result from the equivalent Π model with those
from the other two circuit models. Modify the M-file to use two nominal Π
sections for each half of the line and again compare the results obtained with
those from the equivalent Π model. Note the improvement in accuracy of the
results as compared to that from just one nominal Π section.
Real and reactive power transfer :

In this part of the project, we will examine the behavior of real and reactive
power delivered to the receiving ends load when the voltage magnitudes at both
ends are held constant but the relative phase angle between the sending and
receiving ends voltage is varied. We will begin with the base case condition of
the 160km length line delivering 120MW at 0.9 power factor lagging to a
receiving end when the magnitudes of the sending and receiving ends voltages
are held constant at their previous values, that is 199.24 and 345/√(3) kV,
respectively. Keep the phase angle of VR at zero, but vary that of VS from – Π to
+ Π radians in one degree increments.
The complex power delivered to the receiving end can be computed from

Figure 3.2 shows the loci of the receiving ends complex power for the 160km
line based on the ABCD parameters of its equivalent Π circuit model. These
plots are obtained by varying the angle of VS over the range of ± π. The solid-
line plot is the PQ locus for a |VS| of 199.24kv. The inner dash-dot plot is for
six percent less in the sending ends voltage, and the outer dotted-line plot is
for 6% more in sending ends voltage.
From transient stability consideration, the phase difference between the
sending ends and receiving ends voltages of lines is to be kept will within 900.
Examine the data of these plots and see if you can identify the portions of these
loci that are of practical use from the point of view of lower line current and
losses for some given level of power transfer.
MATLAB PROGRAM:
% M-file for Project 1 on line parameters and circuit models

% m1.m determines the RLC parameters of the line from its physical
% description and then computes
% the ABCD matrix and the circuit parameters of the
% series RL, nominal pi and equivalent pi model of the line.
% It computes and plot the receiving-end real and reactive power
% circle diagram of the line assuming that the voltage magnitude
% at the sending- and receiving-end are kept constant.
% input constant
epso = 8.854e-12; % permittivity of free space in F/m
muo = 4e-7*pi; % permeability of free space in H/m
we = 2*pi*60 ; % system frequency in rad/sec
% input conductor spacings, length, and resistance

D12p = 7.772; % conductor spacing in m
D1p2 = 6.858; % conductor spacing in m
radc = 4.4755e-2/2; % envelope radius of conductor in m
GMRc = 1.6276e-2; % GMR of conductor in m
d = 160 % length of line in m
s = (D12p- D1p2)/2; % conductor spacing of bundle in m

D12 = D12p+s; % conductor spacing in m
D12eq = (D12*D12*D12p*D1p2)^(1/4);
D23eq = D12eq;
D13eq = ((D12+D1p2)*(D12+D12p)*(D12p+D1p2)^2)^(1/4);
GMD = (D12eq*D23eq*D13eq)^(1/3);
GMR = sqrt(GMRc*s);
GMR1 = sqrt(radc*s);
% RLC per m of line

r = 0.02896e-3/2 % resistance per meter length of phase bundle
l = (muo/2*pi)*log(GMD/GMR) % inductance per meter length
c = 2*pi*epso/log(GMD/GMR1) % capacitance per meter length
% series RL circuit model parameters

R = r*d;
L = l*d;

Z = R + j*we*L;
ABCD_RL = [ 1 Z; 0. 1 ]
% nominal pi circuit model parameters

Cby2 = c*(d/2);
Yby2 = j*we*Cby2;
Y = j*we*Cby2*2;
ABCD_nompi = [ (1 + Z*Yby2) Z; Y*(1+Z*Y/4) (1+Z*Yby2)]
% equivalent pi circuit model parameters

gamma = sqrt((r + j*we*l)*j*we*c);
Zc = sqrt((r + j*we*l)/(j*we*c));
gammad = gamma*d;
ABCD_eqpi=[cosh(gammad) Zc*sinh(gammad);sinh(gammad)/Zc cosh(gammad)]
% receiving-end condition
PR = 120e6/3; % per phase receiving-end power in W
VR = 345e3/sqrt(3); % receiving-end phase voltage in rms V used as ref
pfR = 0.9; % pf of load at receiving end
sinphiR = -sqrt(1-pfR*pfR);%sine of pf angle, neg for lagging
SR = PR*(1 - j*sinphiR/pfR)% per phase complex load power
IR = conj(SR/VR) % receiving-end current
% compute sending-end condition

VIS_RL = ABCD_RL*[VR; IR]
SS_RL = VIS_RL(1)*conj(VIS_RL(2)) % per phase sending-end complex power
pfS_RL = cos(angle(SS_RL))
VS_RL = abs(VIS_RL(1))
IS_RL = abs(VIS_RL(2))
VIS_nompi = ABCD_nompi*[VR; IR]
SS_nompi = VIS_nompi(1)*conj(VIS_nompi(2)) % per phase complex power
pfS_nompi = cos(angle(SS_nompi))
VS_nompi = abs(VIS_nompi(1))
IS_nompi = abs(VIS_nompi(2))
VIS_eqpi = ABCD_eqpi*[VR; IR]
SS_eqpi = VIS_eqpi(1)*conj(VIS_eqpi(2)) % per phase complex power
pfS_eqpi = cos(angle(SS_eqpi))
VS_eqpi = abs(VIS_eqpi(1))
IS_eqpi = abs(VIS_eqpi(2))
% Locus of PQ at receiving-end with changing angle of VS

% while the magnitude of VS and VR held fixed
% using mag of previous condition as base, and +- 3% about base
clf; clear figure window
VS_mag = (0.94:0.06:1.06)*real(VIS_eqpi(1));% create VS angle array
del_VS = (-1:1/180:1)*pi; % create row array for VS angle
inmag = 0 % initialize magnitude index
indel = 0 % initialize angle index
for VSm = VS_mag % external for loop to step through VS mag values
inmag = inmag + 1;
for del = del_VS % internal for loop to step through VS angle values
indel = indel + 1;
VS = VSm*exp(j*del); % compose fixed magnitude VS phasor
IR = (VS - ABCD_eqpi(1,1)*VR)/ABCD_eqpi(1,2);
SR(inmag,indel) = VR*conj(IR); % save complex power value for plotting
end % end of for del loop

end % end of for Vsm loop
% plot PQ locus
plot(real(SR(1,:)),imag(SR(1,:)),'-.', real(SR(2,:)),imag(SR(2,:)),'-',
real(SR(3,:)), imag(SR(3,:)),':');
title('Loci of receiving-end P+jQ')
xlabel('P in W');
ylabel('Q in Var');
axis('square'); % set for square plot
axis('equal'); % equal scaling for both axis
OUTPUT :
Fig. 3.2 Loci of receiving end’s real and reactive power.

EXPERIMENT-4
Transient simulation of a 500 kV single phase line
OBJECTIVES:
1) To implement a Transient simulation of a 500 kV single phase line.
2) Use the simulation to study the impact of inserted circuit breaker
resistance on the breaker and line transient voltages during and
following the opening and closing of the breaker.
3) Examine the impact of line loading on the breaker and line transient
voltages.

BACKGROUND:
In the single-phase circuit of Fig. 4.1, the supply source at the sending end of
the single–phase line is represented by thevenin’s equivalent consist of a 60Hz
2
voltage source, e  500 cos et KV and source inductance, Ls=0.1H. The single-
3
phase line is 100 miles long and is to be represented by a distributed
parameter model.
Figure 4.1: single-phase circuit.
The electrical parameters of the line are

The circuit breaker shown one main contact, M, and two auxiliary
contacts represented by switches Sc, and So. Upon receiving a signal to close
the circuit breaker closes its auxiliary contact, Sc, first, inserting the closing
resistor, Rc, for tc, second before its main contact, M, closes. The closing of
main contact, M, shorts out Rc immediately, following which Sc reopens and
remains open until another closing operation.
When a circuit breaker is closed and it receives a signal to open, it closes
its auxiliary contact, So, first before it opens its main contact, M at the next
breakers current zero. After the opening of main contact, the auxiliary contact,
So, remains closed with Ro inserted for further to seconds. After to seconds, So
opens to interrupt the diminished breaker current at the next current zero.
Figure 4.2a shows the overall diagram of simulation S2 of circuit Fig. 4.1.
The details inside the main blocks of the simulation are given in fig. 4.2b
through 4.2e, as simulated, the breaker can be closed at any point of the wave
of the source voltage. It is however, simpler to obtain the point of the wave of
closing onto the energized line by arranging for the breaker to close at t=0,
using an initial phase of the source voltage, e, that corresponds to desired
point of the wave of closing.
(a) Overall diagram of S2 simulation

(b) Inside breaker
(c) Inside delay tc of breaker

(d) Inside the line block
(e) Inside the RL load block
Fig. 4.2 Simulation S2 of distributed line and breaker.
In figure 4.2a, the thevenin’s source inductance and operational logics of

the breakers with insertion resistors are simulated in the source block, the
delay and attenuation of the line in the line block, and the series RL load at the
receiving end of the line in the RL load block.
In Fig. 4.2b, the switches, insert iS*Rc and insert iS*Rc, insert the
appropriate amount of breaker insertion resistive drops. These two switchs
controlled by logic signals having pulse width corresponding to tc and to
respectively. As required by the condition that M and Sc open on current zero,
the rising and falling edge of the opening pulse signals are synchronized to the
current zeros of the breaker current, is. Since the switch block operates with a
default transition condition of input (2)≥0, a bais of -0.5 must be added to its
logic signal, with true=1, and false=0, to operate the switch properly. As shown
current zero is approximately located by testing for condition when abs(is)≤€.
Care must be exercised in selecting €, as too small and € can result in a
current zero being stepped over when the integration step size is not small.
Set up the simulation S2. Also given is the MATLAB script file m2 that
can be used to set up the desired parameters of the system and operating times
of the breaker. Modify m2 to establish the condition for each case, and use s2
to investigate the following switching operations:


MATLAB PROGRAM 1:
% M-file for Project 2 on switching transients of a distributed parameter %

line
% m2.m sets up the parameters and initial condition

% for the simulation in SIMULINK file s2.m.
% It also plots the results of the simulation.
% Source voltage magnitude, frequency, and inductance

Vrated = 500e3; % rated line to line 3-phase rms voltage
Epk = Vrated*sqrt(2/3); % Peak value of phase voltage
we = 2*pi*60; % 60 Hz supply
Te = 1/60; % period of source voltage in secs.
Ls = 0.1; % source inductance, Henry
tstop = 15*Te; % simulation run time
% Distributed line parameters

d = 100; % 100 miles long
R = 0.15; % resistance of line, Ohm per mile
L = 2.96e-3; % inductance of line, Henry per mile
C = 0.017e-6; % capacitance of line, Farad per mile
Zc = sqrt(L/C) % characteristic impedance in ohms
tdelay = d*sqrt(L*C) % one-way propagation time delay in seconds
atten = exp(-(R/2)*sqrt(C/L)*d) % one-way attenuation
buffer_size = 20000; % buffer size of delay module
% Load parameters
SL = 30e6*(0.8 +j*0.6) % 30 MVA, 0.8 pf lagging
ZL = Vrated^2/conj(SL) % per phase load impedance in Ohms
RL = real(ZL) % series RL load model resistance
LL = imag(ZL)/we % series RL load model inductance
% Breaker's parameter
tc = 1/60 % one cycle closing time
Rc = 1000; % closing resistance in Ohms
to = 1/60 % one cycle opening time
Ro = 1000; % opening resistance in Ohms
disp('Run simulation and return for plots')

keyboard
clf;
subplot(3,1,1)
plot(y(:,1),y(:,2),'-')
ylabel('e in V')
title('Source voltage')
subplot(3,1,2)
plot(y(:,1),y(:,3),'-')
ylabel('Vb in V')
title('Breaker voltage')
subplot(3,1,3)
plot(y(:,1),y(:,4),'-')
ylabel('IS in A')
title('Sending end current')

h2=figure;
subplot(3,1,1)
plot(y(:,1),y(:,5),'-')
ylabel('VS in V')
title('Sending end voltage')
subplot(3,1,2)
plot(y(:,1),y(:,7),'-')
ylabel('IR in A')
title('Receiving end current')
subplot(3,1,3)
plot(y(:,1),y(:,6),'-')
ylabel('VR in V')
xlabel('Time in sec')
title('Load terminal voltage')
disp('Save plots before typing return to exit')

keyboard
close (h2)
MATLAB PROGRAM 2:
function [ret,x0,str,ts,xts]=s2(t,x,u,flag);
%s2 is the M-file description of the SIMULINK system named s2.
% The block-diagram can be displayed by typing: s2.
%
% SYS=s2(T,X,U,FLAG) returns depending on FLAG certain
% system values given time point, T, current state vector, X,
% and input vector, U.
% FLAG is used to indicate the type of output to be returned in SYS.
%
% Setting FLAG=1 causes s2 to return state derivatives, FLAG=2
% discrete states, FLAG=3 system outputs and FLAG=4 next sample
% time. For more information and other options see SFUNC.
%
% Calling s2 with a FLAG of zero:
% [SIZES]=s2([],[],[],0), returns a vector, SIZES, which
% contains the sizes of the state vector and other parameters.
% SIZES(1) number of states
% SIZES(2) number of discrete states
% SIZES(3) number of outputs
% SIZES(4) number of inputs
% SIZES(5) number of roots (currently unsupported)
% SIZES(6) direct feedthrough flag
% SIZES(7) number of sample times
%
% For the definition of other parameters in SIZES, see SFUNC.
% See also, TRIM, LINMOD, LINSIM, EULER, RK23, RK45, ADAMS, GEAR.
% Note: This M-file is only used for saving graphical information;

% after the model is loaded into memory an internal model
% representation is used.
% the system will take on the name of this mfile:

sys = mfilename;

new_system(sys)
simver(1.3)
if (0 == (nargin + nargout))
set_param(sys,'Location',[78,47,687,392])
open_system(sys)
end;
set_param(sys,'algorithm', 'Adams/Gear')
set_param(sys,'Start time', '0.0')
set_param(sys,'Stop time', 'tstop')
set_param(sys,'Min step size', '0.0001')
set_param(sys,'Max step size', '0.0010')
set_param(sys,'Relative error','1e-5')
set_param(sys,'Return vars', '')
% Subsystem ['CB on//off',13,'signal'].
new_system([sys,'/',['CB on//off',13,'signal']])
set_param([sys,'/',['CB on//off',13,'signal']],'Location',[5,40,315,196])
add_block('built-in/Outport',[sys,'/',['CB on//off',13,'signal/out_1']])
set_param([sys,'/',['CB on//off',13,'signal/out_1']],...
'position',[285,60,305,80])
add_block('built-in/Look Up Table',[sys,'/',['CB on//off',13,'signal/Look-Up

Table']])
set_param([sys,'/',['CB on//off',13,'signal/Look-Up Table']],...
'Input_Values','t',...
'Output_Values','y',...
'position',[210,58,250,82])
add_block('built-in/Fcn',[sys,'/',['CB on//off',13,'signal/Fcn1']])
set_param([sys,'/',['CB on//off',13,'signal/Fcn1']],...
'Expr','rem(u[1],period)',...
'position',[110,60,150,80])
add_block('built-in/Clock',[sys,'/',['CB on//off',13,'signal/Clock']])
set_param([sys,'/',['CB on//off',13,'signal/Clock']],...
'position',[45,60,65,80])
add_line([sys,'/',['CB on//off',13,'signal']],[255,70;280,70])
set_param([sys,'/',['CB on//off',13,'signal']],...
'Mask Display','plot([t,t+period,t+2*period],[y,y,y])',...
'Mask Type','Repeating table')
'Mask Dialogue','Repeating table.\nEnter values of time and output
for first cycle.|Time values:|Output values:',...
'Mask Translate','period = max(@1); t = @1; y = @2;')
'Mask Help','Repeats cycle given in table. Time values should be
monotonically increasing.',...
'Mask Entries','[0 10*Te 10*Te 1.1*tstop ]\/[1 1 0 0 ]\/')
% Finished composite block ['CB on//off',13,'signal'].

'position',[110,198,140,222])
add_block('built-in/Note',[sys,'/','iR'])
set_param([sys,'/','iR'],...
'position',[455,150,460,155])
add_block('built-in/Note',[sys,'/','Vb'])
set_param([sys,'/','Vb'],...
'position',[240,175,245,180])
add_block('built-in/Note',[sys,'/','iS'])
set_param([sys,'/','iS'],...
'position',[240,150,245,155])
add_block('built-in/Note',[sys,'/','vS'])
set_param([sys,'/','vS'],...
'position',[360,175,365,180])
add_block('built-in/Note',[sys,'/','vR'])
set_param([sys,'/','vR'],...
'position',[360,150,365,155])
add_block('built-in/Clock',[sys,'/','Clock'])
set_param([sys,'/','Clock'],...
'position',[125,110,145,130])
% Subsystem 'RL load'.
new_system([sys,'/','RL load'])
set_param([sys,'/','RL load'],'Location',[580,121,1019,341])
add_block('built-in/Gain',[sys,'/','RL load/gain1'])
set_param([sys,'/','RL load/gain1'],...
'Gain','1/LL',...
'position',[150,68,205,112])
add_block('built-in/Sum',[sys,'/','RL load/Sum'])
set_param([sys,'/','RL load/Sum'],...
'inputs','+-',...
'position',[105,62,120,113])
add_block('built-in/Integrator',[sys,'/','RL load/int'])
set_param([sys,'/','RL load/int'],...
'position',[230,70,270,110])
add_block('built-in/Outport',[sys,'/','RL load/iR'])
set_param([sys,'/','RL load/iR'],...
'position',[320,80,340,100])
add_block('built-in/Inport',[sys,'/','RL load/vR'])
set_param([sys,'/','RL load/vR'],...
'position',[35,65,55,85])

add_block('built-in/Gain',[sys,'/','RL load/gain'])
set_param([sys,'/','RL load/gain'],...
'orientation',2,...
'Gain','RL',...
'position',[170,126,230,164])
add_line([sys,'/','RL load'],[275,90;285,90;285,145;235,145])
add_line([sys,'/','RL load'],[165,145;80,145;80,100;100,100])
add_line([sys,'/','RL load'],[275,90;315,90])
% Finished composite block 'RL load'.
set_param([sys,'/','RL load'],...
'position',[415,145,445,195])
add_block('built-in/Sine Wave',[sys,'/','e'])
set_param([sys,'/','e'],...
'amplitude','Epk',...
'frequency','we',...
'phase','pi/2',...
'position',[115,151,145,179])
% Subsystem 'line'.
new_system([sys,'/','line'])
set_param([sys,'/','line'],'Location',[322,88,1015,437])
add_block('built-in/Note',[sys,'/','line/VbS'])
set_param([sys,'/','line/VbS'],...
'position',[180,210,185,215])
add_block('built-in/Sum',[sys,'/','line/Sum2'])
set_param([sys,'/','line/Sum2'],...
'inputs','+-',...
'position',[190,68,205,132])
add_block('built-in/Note',[sys,'/','line/VfS'])
set_param([sys,'/','line/VfS'],...
'position',[220,75,225,80])
add_block('built-in/Transport Delay',[sys,'/','line/S_to_R delay'])

set_param([sys,'/','line/S_to_R delay'],...
'Delay Time','tdelay',...
'Buffer Size:','buffer_size',...
'position',[260,76,305,124])
add_block('built-in/Gain',[sys,'/','line/Zc1'])
set_param([sys,'/','line/Zc1'],...
'orientation',3,...
'Gain','Zc',...
'position',[55,170,95,205])

add_block('built-in/Inport',[sys,'/','line/iS'])
set_param([sys,'/','line/iS'],...
'position',[30,230,50,250])
add_block('built-in/Gain',[sys,'/','line/Gain1'])
set_param([sys,'/','line/Gain1'],...
'orientation',2,...
'Gain','2',...
'position',[115,218,145,252])
'orientation',3,...
'position',[59,125,126,140])
add_block('built-in/Transport Delay',[sys,'/','line/R_to_S delay'])

set_param([sys,'/','line/R_to_S delay'],...
'orientation',2,...
'Delay Time','tdelay',...
'Buffer Size:','buffer_size',...
'position',[270,209,315,261])
add_block('built-in/Gain',[sys,'/','line/atten2'])
set_param([sys,'/','line/atten2'],...
'orientation',2,...
'Gain','atten',...
'position',[200,214,245,256])
add_block('built-in/Note',[sys,'/','line/VbR'])
set_param([sys,'/','line/VbR'],...
'position',[345,210,350,215])
'orientation',2,...
'inputs','-+',...
'position',[370,199,385,266])
add_block('built-in/Gain',[sys,'/','line/atten1'])
set_param([sys,'/','line/atten1'],...
'Gain','atten',...
'position',[340,80,380,120])
add_block('built-in/Note',[sys,'/','line/VfR'])
set_param([sys,'/','line/VfR'],...
'position',[400,75,405,80])
add_block('built-in/Gain',[sys,'/','line/Gain6'])
set_param([sys,'/','line/Gain6'],...
'Gain','2',...
'position',[430,84,465,116])
add_block('built-in/Gain',[sys,'/','line/Zc2'])
set_param([sys,'/','line/Zc2'],...
'orientation',1,...
'Gain','Zc',...
'position',[499,130,541,165])
'orientation',1,...
'inputs','+-',...
'position',[475,200,535,215])
add_block('built-in/Outport',[sys,'/','line/VR '])
set_param([sys,'/','line/VR '],...
'position',[565,240,585,260])
add_block('built-in/Inport',[sys,'/','line/iR'])
set_param([sys,'/','line/iR'],...
'orientation',2,...
'Port','2',...
'position',[560,80,580,100])
add_block('built-in/Outport',[sys,'/','line/VS'])
set_param([sys,'/','line/VS'],...
'orientation',2,...
'Port','2',...
'position',[25,75,45,95])
add_line([sys,'/','line'],[195,235;165,235;165,115;185,115])
add_line([sys,'/','line'],[195,235;150,235])
add_line([sys,'/','line'],[265,235;250,235])
add_line([sys,'/','line'],[385,100;425,100])
add_line([sys,'/','line'],[310,100;335,100])
add_line([sys,'/','line'],[110,235;110,145])
add_line([sys,'/','line'],[470,100;490,100;490,195])
add_line([sys,'/','line'],[75,165;75,145])
add_line([sys,'/','line'],[210,100;255,100])
add_line([sys,'/','line'],[520,170;520,195])
add_line([sys,'/','line'],[365,235;320,235])
add_line([sys,'/','line'],[505,220;505,250;390,250])
add_line([sys,'/','line'],[505,220;505,250;560,250])
add_line([sys,'/','line'],[55,240;75,240;75,210])
add_line([sys,'/','line'],[555,90;520,90;520,125])
add_line([sys,'/','line'],[95,120;95,85;50,85])
add_line([sys,'/','line'],[95,120;95,85;185,85])
add_line([sys,'/','line'],[385,100;410,100;410,215;390,215])
% Finished composite block 'line'.

set_param([sys,'/','line'],...
'position',[310,157,340,208])
% Subsystem 'breaker'.
new_system([sys,'/','breaker'])
set_param([sys,'/','breaker'],'Location',[292,81,1023,687])
add_block('built-in/Scope',[sys,'/','breaker/Scope1'])

set_param([sys,'/','breaker/Scope1'],...
'Vgain','3.000000',...
'Hgain','0.300000',...
'Vmax','6.000000',...
'Hmax','2.000000',...
'Window',[38,803,525,913],...
'position',[695,92,715,118])
add_block('built-in/Switch',[sys,'/','breaker/Switch'])
set_param([sys,'/','breaker/Switch'],...
'Threshold','0.5',...
'position',[530,117,545,163])
add_block('built-in/Sum',[sys,'/','breaker/e-vS-iS*Rcb'])
set_param([sys,'/','breaker/e-vS-iS*Rcb'],...
'inputs','+--',...
'position',[180,99,195,151])
add_block('built-in/Switch',[sys,'/','breaker/IS*Rcb insert'])
set_param([sys,'/','breaker/IS*Rcb insert'],...
'position',[560,46,575,94])
'orientation',2,...
'Vgain','5.000000',...
'Hgain','0.300000',...
'Vmax','10.000000',...
'Hmax','2.000000',...
'Window',[30,547,273,660],...
'position',[40,187,60,213])
add_block('built-in/Logical Operator',[sys,'/','breaker/NOT CB on//off'])

set_param([sys,'/','breaker/NOT CB on//off'],...
'Operator','NOT',...
'Number of Input Ports','1',...
'position',[305,378,335,402])
add_block('built-in/Outport',[sys,'/','breaker/iS'])
set_param([sys,'/','breaker/iS'],...
'position',[695,140,715,160])
add_block('built-in/Logical Operator',[sys,'/',['breaker/open',13,'M at
next',13,'iS zero']])
set_param([sys,'/',['breaker/open',13,'M at next',13,'iS zero']],...
'orientation',1,...
'Operator','AND',...
'Number of Input Ports','3',...
'position',[556,420,604,440])
add_block('built-in/Switch',[sys,'/','breaker/Insert iS*Ro'])
set_param([sys,'/','breaker/Insert iS*Ro'],...
'orientation',2,...

'position',[110,236,130,284])
add_block('built-in/Gain',[sys,'/','breaker/Gain'])
set_param([sys,'/','breaker/Gain'],...
'Gain','1/Ls',...
'position',[340,107,385,143])
add_block('built-in/Gain',[sys,'/','breaker/Ro'])
set_param([sys,'/','breaker/Ro'],...
'orientation',2,...
'Gain','Ro',...
'position',[390,226,435,264])
add_block('built-in/Gain',[sys,'/','breaker/Rc'])
set_param([sys,'/','breaker/Rc'],...
'orientation',2,...
'Gain','Rc',...
'position',[300,166,345,204])
add_block('built-in/Sum',[sys,'/','breaker/Vbreaker'])
set_param([sys,'/','breaker/Vbreaker'],...
'inputs','+-',...
'position',[625,23,645,87])
add_block('built-in/Reset
Integrator',[sys,'/',['breaker/Reset',13,'Integrator']])
set_param([sys,'/',['breaker/Reset',13,'Integrator']],...
'position',[595,133,635,167])
add_block('built-in/Sum',[sys,'/','breaker/e-vS'])
set_param([sys,'/','breaker/e-vS'],...
'inputs','+-',...
'position',[110,14,125,61])
'orientation',2,...
'Vgain','5.000000',...
'Hgain','0.300000',...
'Vmax','10.000000',...
'Hmax','2.000000',...
'Window',[31,320,275,434],...
'position',[40,137,60,163])
add_block('built-in/Inport',[sys,'/','breaker/e'])
set_param([sys,'/','breaker/e'],...
'position',[40,14,65,36])
add_block('built-in/Inport',[sys,'/','breaker/vS'])
set_param([sys,'/','breaker/vS'],...
'Port','3',...
'position',[40,58,65,82])
add_block('built-in/Note',[sys,'/','breaker/M closed '])

set_param([sys,'/','breaker/M closed '],...

'position',[440,300,445,305])
% Subsystem ['breaker/CB_on',13,'status'].
new_system([sys,'/',['breaker/CB_on',13,'status']])
set_param([sys,'/',['breaker/CB_on',13,'status']],'Location',[102,336,551,502
])
add_block('built-in/Fcn',[sys,'/',['breaker/CB_on',13,'status/Fcn']])
set_param([sys,'/',['breaker/CB_on',13,'status/Fcn']],...
'orientation',2,...
'Expr','u[1]>.2',...
'position',[170,123,205,147])
add_block('built-in/Demux',[sys,'/',['breaker/CB_on',13,'status/Demux']])
set_param([sys,'/',['breaker/CB_on',13,'status/Demux']],...
'outputs','2',...
'position',[275,55,315,90])
add_block('built-in/Combinatorial
Logic',[sys,'/',['breaker/CB_on',13,'status/Logic']])
set_param([sys,'/',['breaker/CB_on',13,'status/Logic']],...
'Truth Table','[0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
'position',[195,55,250,95])
add_block('built-in/Transport
Delay',[sys,'/',['breaker/CB_on',13,'status/Transport Delay']])
set_param([sys,'/',['breaker/CB_on',13,'status/Transport Delay']],...
'orientation',2,...
'Initial Input','ini',...
'position',[250,120,295,150])
add_block('built-in/Outport',[sys,'/',['breaker/CB_on',13,'status/out_2']])
set_param([sys,'/',['breaker/CB_on',13,'status/out_2']],...
'Port','2',...
'position',[395,70,415,90])
add_block('built-in/Outport',[sys,'/',['breaker/CB_on',13,'status/out_1']])
set_param([sys,'/',['breaker/CB_on',13,'status/out_1']],...
'position',[355,55,375,75])
add_block('built-in/Mux',[sys,'/',['breaker/CB_on',13,'status/Mux']])
set_param([sys,'/',['breaker/CB_on',13,'status/Mux']],...
'inputs','3',...
'position',[135,59,165,91])
add_block('built-in/Inport',[sys,'/',['breaker/CB_on',13,'status/in_1']])
set_param([sys,'/',['breaker/CB_on',13,'status/in_1']],...
'position',[20,50,40,70])
add_block('built-in/Inport',[sys,'/',['breaker/CB_on',13,'status/in_2']])
set_param([sys,'/',['breaker/CB_on',13,'status/in_2']],...
'Port','2',...
'position',[50,65,70,85])
add_line([sys,'/',['breaker/CB_on',13,'status']],[320,65;350,65])
add_line([sys,'/',['breaker/CB_on',13,'status']],[335,65;335,135;300,135])
add_line([sys,'/',['breaker/CB_on',13,'status']],[165,135;110,135;110,85;130,
85])
add_line([sys,'/',['breaker/CB_on',13,'status']],[45,60;105,60;105,65;130,65]
)
set_param([sys,'/',['breaker/CB_on',13,'status']],...
'Mask Display','S 1\n\nR 0',...
'Mask Type','Latch',...
'Mask Dialogue','Latch|Initial State for Output "1":',...
'Mask Translate','ini=(@1~=0);')
'Mask Help','Latches the S input. When S (set) is one, the
uncomplemented output (1) becomes one. The output remains one until the R
(reset) input becomes one, forcing the output to zero. If both R and S are
one, the latch will be in an undefined state.')
'Mask Entries','0\/')
% Finished composite block ['breaker/CB_on',13,'status'].
'position',[360,309,395,351])
add_block('built-in/Logical
Operator',[sys,'/',['breaker/Logical',13,'Operator4']])
set_param([sys,'/',['breaker/Logical',13,'Operator4']],...
'orientation',3,...
'Operator','XOR',...
'position',[150,455,190,480])
% Subsystem 'breaker/Latch2'.
new_system([sys,'/','breaker/Latch2'])
set_param([sys,'/','breaker/Latch2'],'Location',[102,336,551,502])
add_block('built-in/Fcn',[sys,'/','breaker/Latch2/Fcn'])
set_param([sys,'/','breaker/Latch2/Fcn'],...
'orientation',2,...
'Expr','u[1]>.2',...
'position',[170,123,205,147])
add_block('built-in/Demux',[sys,'/','breaker/Latch2/Demux'])
set_param([sys,'/','breaker/Latch2/Demux'],...
'outputs','2',...
'position',[275,55,315,90])
add_block('built-in/Combinatorial Logic',[sys,'/','breaker/Latch2/Logic'])
set_param([sys,'/','breaker/Latch2/Logic'],...
'Truth Table','[0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
'position',[195,55,250,95])

add_block('built-in/Transport Delay',[sys,'/','breaker/Latch2/Transport
Delay'])
set_param([sys,'/','breaker/Latch2/Transport Delay'],...
'orientation',2,...
'position',[250,120,295,150])
add_block('built-in/Outport',[sys,'/','breaker/Latch2/out_2'])
set_param([sys,'/','breaker/Latch2/out_2'],...
'Port','2',...
'position',[395,70,415,90])
'position',[355,55,375,75])
add_block('built-in/Mux',[sys,'/','breaker/Latch2/Mux'])
set_param([sys,'/','breaker/Latch2/Mux'],...
'inputs','3',...
'position',[135,59,165,91])
add_block('built-in/Inport',[sys,'/','breaker/Latch2/in_1'])
set_param([sys,'/','breaker/Latch2/in_1'],...
'position',[20,50,40,70])
'Port','2',...
'position',[50,65,70,85])
add_line([sys,'/','breaker/Latch2'],[320,65;350,65])
add_line([sys,'/','breaker/Latch2'],[335,65;335,135;300,135])
add_line([sys,'/','breaker/Latch2'],[165,135;110,135;110,85;130,85])
set_param([sys,'/','breaker/Latch2'],...
% Finished composite block 'breaker/Latch2'.

'orientation',2,...
'position',[445,490,480,530])
'orientation',2,...
'Expr','u[1]>.2',...
'position',[170,123,205,147])
'outputs','2',...
'position',[275,55,315,90])
'Truth Table','[0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
'position',[195,55,250,95])
Delay'])
'orientation',2,...
'position',[250,120,295,150])
'Port','2',...
'position',[395,70,415,90])
'position',[355,55,375,75])
'inputs','3',...
'position',[135,59,165,91])
'position',[20,50,40,70])
'Port','2',...
'position',[50,65,70,85])
'position',[310,435,345,475])
add_block('built-in/Transport Delay',[sys,'/','breaker/delay to'])

set_param([sys,'/','breaker/delay to'],...
'orientation',2,...
'Delay Time','to',...
'position',[345,507,400,543])
add_block('built-in/Fcn',[sys,'/','breaker/abs(iS)'])
set_param([sys,'/','breaker/abs(iS)'],...
'orientation',2,...
'Expr','abs(u[1])',...
'position',[615,483,650,517])
add_block('built-in/Logical Operator',[sys,'/',['breaker/t0
delay',13,'enable']])
set_param([sys,'/',['breaker/t0 delay',13,'enable']],...
'orientation',2,...
'position',[285,516,320,554])
'orientation',2,...
'Expr','u[1]>.2',...
'position',[170,123,205,147])

'outputs','2',...
'position',[275,55,315,90])
'Truth Table','[0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
'position',[195,55,250,95])
Delay'])
'orientation',2,...
'position',[250,120,295,150])
'Port','2',...
'position',[395,70,415,90])
'position',[355,55,375,75])
'inputs','3',...
'position',[135,59,165,91])
'position',[20,50,40,70])
'Port','2',...
'position',[50,65,70,85])


'orientation',2,...
'position',[175,525,210,565])
add_block('built-in/Relational Operator',[sys,'/','breaker/|iS|<=eps'])
set_param([sys,'/','breaker/|iS|<=eps'],...
'orientation',2,...
'Operator','<=',...
'position',[545,526,575,564])
add_block('built-in/Constant',[sys,'/','breaker/eps'])
set_param([sys,'/','breaker/eps'],...
'orientation',2,...
'position',[615,541,635,569])
add_block('built-in/Switch',[sys,'/','breaker/Insert iS*Rc'])
set_param([sys,'/','breaker/Insert iS*Rc'],...
'orientation',2,...
'position',[175,175,195,225])
% Subsystem 'breaker/delay tc'.
new_system([sys,'/','breaker/delay tc'])
set_param([sys,'/','breaker/delay tc'],'Location',[485,451,992,690])
add_block('built-in/Note',[sys,'/',['breaker/delay tc/AND used to

suppress',13,'spurious operation when',13,'input goes from high to low']])
set_param([sys,'/',['breaker/delay tc/AND used to suppress',13,'spurious
operation when',13,'input goes from high to low']],...
'position',[350,178,355,183])
add_block('built-in/Logical Operator',[sys,'/',['breaker/delay
tc/Logical',13,'Operator1']])
set_param([sys,'/',['breaker/delay tc/Logical',13,'Operator1']],...
'position',[320,42,365,138])
add_block('built-in/Outport',[sys,'/','breaker/delay tc/out_1'])
set_param([sys,'/','breaker/delay tc/out_1'],...
'position',[405,80,425,100])
add_block('built-in/Inport',[sys,'/','breaker/delay tc/in_1'])

set_param([sys,'/','breaker/delay tc/in_1'],...
'position',[20,90,40,110])
add_block('built-in/Logical Operator',[sys,'/',['breaker/delay
tc/Logical',13,'Operator']])
set_param([sys,'/',['breaker/delay tc/Logical',13,'Operator']],...
'Operator','XOR',...
'position',[225,85,275,145])
add_block('built-in/Transport Delay',[sys,'/',['breaker/delay
tc/Transport',13,'Delay1']])
set_param([sys,'/',['breaker/delay tc/Transport',13,'Delay1']],...
'Delay Time','tc',...
'position',[105,110,170,150])
add_line([sys,'/','breaker/delay tc'],[175,130;220,130])
add_line([sys,'/','breaker/delay tc'],[45,100;60,100;60,130;100,130])
add_line([sys,'/','breaker/delay tc'],[60,100;60,65;315,65])
% Finished composite block 'breaker/delay tc'.
set_param([sys,'/','breaker/delay tc'],...
'orientation',3,...
'position',[230,340,280,370])
add_block('built-in/Inport',[sys,'/',['breaker/CB on//off',13,'signal']])
set_param([sys,'/',['breaker/CB on//off',13,'signal']],...
'Port','2',...
'position',[55,380,75,400])
add_block('built-in/Outport',[sys,'/','breaker/vb'])
set_param([sys,'/','breaker/vb'],...
'Port','2',...
'position',[675,45,695,65])
add_line([sys,'/','breaker'],[650,55;670,55])
add_line([sys,'/','breaker'],[105,260;95,260;95,125;175,125])
add_line([sys,'/','breaker'],[670,150;670,185;350,185])

add_line([sys,'/','breaker'],[580,445;580,455;550,455;550,150;590,150])
add_line([sys,'/','breaker'],[95,390;95,585;505,585;505,520;485,520])
set_param([sys,'/','breaker'],...
'Mask Display','')
% Finished composite block 'breaker'.
set_param([sys,'/','breaker'],...
'position',[195,154,225,206])
add_block('built-in/Mux',[sys,'/','Mux2'])
set_param([sys,'/','Mux2'],...
'orientation',3,...
'inputs','7',...
'position',[125,85,515,100])
add_block('built-in/Note',[sys,'/',['Double click on masked block m2 in this

screen or run m2.m in ',13,'MATLAB command window to initialize this
simulation. ',13,'After the simulation, type return after the K>> prompt in
the ',13,'MATLAB command window to plot results.']])
set_param([sys,'/',['Double click on masked block m2 in this screen or run
m2.m in ',13,'MATLAB command window to initialize this simulation.
',13,'After the simulation, type return after the K>> prompt in the
',13,'MATLAB command window to plot results.']],...
'position',[315,250,320,255])
% Subsystem 'm2'.

new_system([sys,'/','m2'])
set_param([sys,'/','m2'],'Location',[-10,4391136,201,4391244])
add_block('built-in/Note',[sys,'/',['m2/Masked block of m2.m to initalize

s2.m ',13,'and plot results']])
set_param([sys,'/',['m2/Masked block of m2.m to initalize s2.m ',13,'and plot
results']],...
'position',[125,45,130,50])
set_param([sys,'/','m2'],...
'Mask Display','Initialize\nand plot',...
'Mask Type','Masked block of m2.m',...
'Mask Dialogue','eval(''m2'')',...
'Mask Help','Uses m2.m to initialize and plot')
% Finished composite block 'm2'.
set_param([sys,'/','m2'],...
'Drop Shadow',4,...
'position',[120,26,194,64])
add_block('built-in/Scope',[sys,'/','Scope'])
set_param([sys,'/','Scope'],...
'orientation',2,...
'Vgain','450000.000000',...
'Hgain','0.250000',...
'Vmax','900000.000000',...
'Hmax','0.500000',...
'Window',[79,364,702,581])
open_system([sys,'/','Scope'])
set_param([sys,'/','Scope'],...
'position',[250,39,270,61])
add_block('built-in/To Workspace',[sys,'/','To Workspace'])

set_param([sys,'/','To Workspace'],...
'mat-name','y',...
'buffer','15000',...
'position',[380,42,430,58])
add_line(sys,[450,170;485,170;485,245;290,245;290,195;305,195])
add_line(sys,[230,170;305,170])
add_line(sys,[345,170;410,170])
add_line(sys,[150,165;190,165])
add_line(sys,[345,195;375,195;375,235;175,235;175,195;190,195])
add_line(sys,[320,80;320,50;375,50])
add_line(sys,[150,120;155,120;155,105])
add_line(sys,[145,210;160,210;160,180;190,180])
add_line(sys,[320,80;320,50;275,50])
add_line(sys,[150,165;160,165;160,145;210,145;210,105])
add_line(sys,[230,195;265,195;265,105])
add_line(sys,[230,170;255,170;255,140;320,140;320,105])
add_line(sys,[345,195;375,195;375,105])
add_line(sys,[345,170;385,170;385,135;430,135;430,105])
add_line(sys,[450,170;485,170;485,105])
drawnow

% Return any arguments.

if (nargin | nargout)
% Must use feval here to access system in memory
if (nargin > 3)
if (flag == 0)
eval(['[ret,x0,str,ts,xts]=',sys,'(t,x,u,flag);'])
else
eval(['ret =', sys,'(t,x,u,flag);'])
end
else
[ret,x0,str,ts,xts] = feval(sys);
end
else
drawnow % Flash up the model and execute load callback
end
OUTPUT WAVEFORMS:
Figure 3.37 plot of vb(trace 1), vs(trace 2),vR(trace 3), iS(trace 4), iR(trace 5).

EXPERIMENT - 5
SIMULATION OF A SINGLE-PHASE TWO-WINDING
TRANSFORMER
OBJECTIVE:
To Simulate and verify a single-phase two-winding transformer operating at

following conditions 1) the seconady terminals short circuited 2) the secondary
terminals connected to a non-unty power factor load.

BACKGROUND:
The objectives of this project are to implement a SIMULINK simulation of

a single-phase two-winding transformer, use it to examine two operating
conditions 1) the seconady terminals short circuited 2) the secondary
terminals connected to a non-unty power factor load, and to verify the results
obtained with those predicted from an analysis using the equivelent circuit
given in Fig 5.1.
Fig 5.1 Equivalent circuit of a two-winding transformer.
The circuit parameters and magnetization curve for the 120/240V, 1.5 KVA, 60
Hz, pole-type, two-winding distribution transformer are as follows:
r1= 0.25 Ω, rˊ2 = 0.134 Ω, xl1= 0.056 Ω, xˊl2 = 0.056 Ω, xm1 = 708.8 Ω
All parameters given above are referred to the 120 V, winding 1 side.
The SIMULINK simulation of a two windings transformer can be set up

using the voltage-input, current output model. The core saturation can be
handled using a look up table between And , such as that of Fig 5.2 and
given in slc. The look-up table and memory modules to break the algebraic
loop are found in SIMULINK’s Nonlinear block library.
Use the MATLAB script file ml to set up the parameters of the SIMULINK
simulation slc. Check the parameter settings in ml to make sure that they
correspond to the parameters of the 120/240, 1.5 kVA, 60-Hz, pole type
distribution transformer given above. Begin by trying the ode 15s or the
Adams/gear numerical method with a minimum step size of 0.1msec, a
maximum step size of 1 msec,and an error tolerance of 1e-7. Conducts the
following runs on the simulation using a sinusoidal input voltage of
v1=120√2sin⁡(120𝜋𝑡 + 𝜃)V.
Fig 5.2 Simulation slc of a two-winding transformer using a look-up table for
the saturation curve.
PROCEDURE:
1) With the 240v side terminals short-circuited, that is v’2=0, and no initial
core flux, energize the transformer at the following point of the wave of
the voltage, v1:
a. The peak of the sinusoidal supply voltage, using a θ of π/2.
b. The zeros of the sinusoidal supply voltage, using a θ of zero.
Plot the values of v1,i1, ,v’2, and i’2.
2) Replace the short circuit termination on the secondary terminal wih a
fixed impedance pepresenting 1.5kVA, 0.8 lagging power factor of loading
at rated voltage and repeat the above energization studies with the
transformer on the load.
3) Discuss the result obtained, checking some of yhem against analytical

result based on the same equivalent circuit, for example , check the
decay times of the dc offset in the input current or flux against the
values of the time constant for the corresponding terminal condition on
the secondary side,with saturation and without saturation. Note the
impact that saturation has and explaine it. Compaire the magnitude of
the currents obtained from the simulation when it reaches steady state
with those computed from steady-state calculations.
4) Modify the simulation to allow you to switch in an additional dc
component volatge to v1 desides the main ac component of
v1=120√2sin⁡(120𝜋𝑡)V. Connect 1.5 KVA, 0.8 power factor lagging load to
the secondary terminals. Start the simulation with the transformer with
v1=120√2sin⁡(120𝜋𝑡)V and the load on the secondary. When steady-state is
reached, slowly ramp up the dc voltage component in the primary
volatge, v1, from zero to 10 V and record the behaviour of ψm, i1, and v’2.
5) Sample results for the case of no load on the secondary terminal are
given Figs. 5.4 and 5.5. These results are obtained using the simulation
shown in Fig. 5.2 with an Adams/Gear numerical method, a minimum
step size of 0.1 msec, a maximum step size of 1msec, and an error
tolerance of 1e-7. The open-circuit terminal condition on the secondary
terminals was approximated with a large resistor of 1 kΩ.
MATLAB PROGRAM (m1):
% MATLAB script file m1.m is for Projects 1, and 2 on single-phase

% two-winding transformer in Chapter 4
% m1.m sets up the parameters of a two-winding single-phase unit
% and plots some variables of the unit.
clear all % clear workspace
% Set up circuit parameters and mag. curve of transformer
Vrated = 120; % rms rated voltage

Srated = 1500; % rated VA
Frated = 60; % rated frequency in Hz
Zb = Vrated^2/Srated; % base impedance on primary side
wb = 2*pi*Frated; % base frequency
Vpk = Vrated*sqrt(2); % peak rated voltage
NpbyNs = 120/240; % nominal turns ratio
r1 = 0.25; % resistance of wdg 1 in ohms
rp2 = 0.134; % referred resistance of wdg 2 in ohms
xl1 = 0.056; % leakage reactance of wdg 1 in ohms
xpl2 = 0.056; % leakage reactance of wdg 1 in ohms
xm = 708.8; % unsaturated magnetizing reactance in ohms
xM = 1/(1/xm + 1/xl1 + 1/xpl2);
% mag. curve Dpsi versus psisat

Dpsi=[ -2454.6 -2412.6 -2370.5 -2328.5 -2286.4 -2244.4 -2202.3 ...

-2160.3 -2118.2 -2076.1 -2034.1 -1992.0 -1950.0 -1907.9 -1865.9 ...
-1823.8 -1781.8 -1739.7 -1697.7 -1655.6 -1613.6 -1571.5 -1529.5 ...
-1487.4 -1445.3 -1403.3 -1361.2 -1319.2 -1277.1 -1235.1 -1193.0 ...
-1151.0 -1108.9 -1066.9 -1024.8 -982.76 -940.71 -898.65 -856.60 ...
-814.55 -772.49 -730.44 -688.39 -646.43 -604.66 -562.89 -521.30 ...
-479.53 -438.14 -396.75 -355.35 -313.96 -272.56 -231.17 -192.60 ...
-154.04 -116.41 -81.619 -46.822 -19.566 0.0000 0.0000 0.0000 0.0000 ...
0.0000 0.0000 19.566 46.822 81.619 116.41 154.04 192.60 231.17 ...
272.56 313.96 355.35 396.75 438.14 479.53 521.30 562.89 604.66 ...
646.43 688.39 730.44 772.49 814.55 856.60 898.65 940.71 982.76 ...
1024.8 1066.9 1108.9 1151.0 1193.0 1235.1 1277.1 1319.2 1361.2 ...
1403.3 1445.3 1487.4 1529.5 1571.5 1613.6 1655.6 1697.7 1739.7 ...
1781.8 1823.8 1865.9 1907.9 1950.0 1992.0 2034.1 2076.1 2118.2 ...
2160.3 2202.3 2244.4 2286.4 2328.5 2370.5 2412.6 2454.6 ];
psisat=[ -170.21 -169.93 -169.65 -169.36 -169.08 -168.80 -168.52 ...

-168.23 -167.95 -167.67 -167.38 -167.10 -166.82 -166.54 -166.25 ...
-165.97 -165.69 -165.40 -165.12 -164.84 -164.56 -164.27 -163.99 ...
-163.71 -163.43 -163.14 -162.86 -162.58 -162.29 -162.01 -161.73 ...
-161.45 -161.16 -160.88 -160.60 -160.32 -160.03 -159.75 -159.47 ...
-159.18 -158.90 -158.62 -158.34 -157.96 -157.39 -156.83 -156.07 ...
-155.51 -154.57 -153.62 -152.68 -151.74 -150.80 -149.85 -146.08 ...
-142.31 -137.60 -130.06 -122.52 -107.44 -84.672 -42.336 0.0000 ...
0.0000 42.336 84.672 107.44 122.52 130.06 137.60 142.31 146.08 ...
149.85 150.80 151.74 152.68 153.62 154.57 155.51 156.07 156.83 ...
157.39 157.96 158.34 158.62 158.90 159.18 159.47 159.75 160.03 ...
160.32 160.60 160.88 161.16 161.45 161.73 162.01 162.29 162.58 ...
162.86 163.14 163.43 163.71 163.99 164.27 164.56 164.84 165.12 ...
165.40 165.69 165.97 166.25 166.54 166.82 167.10 167.38 167.67 ...
167.95 168.23 168.52 168.80 169.08 169.36 169.65 169.93 170.21 ];
% set up simulation parameters

tstop = 0.2; % stop time
Psi1o = 0; % initial value of wdg l flux linkage
Psip2o = 0; % initial value of wdg 2 flux linkage
repeat_run = 'Y'; % set up repeat run flag

while repeat_run == 'Y'
disp('Setting up transformer simulation')

disp('')
disp('Enter value of RH, the high-gain resistor to develop v2''')

disp('Example: set RH to 0 for short circuit')
disp(' or to 100*Zb for open circuit')
disp('Zb is the base impedance on primary side')
disp('')
RH = input('Enter ohmic value of high gain resistor RH >')
disp('')
disp('Run simulation then type ''return '' for plots')
keyboard
clf;
subplot(3,1,1)
plot(y(:,1),y(:,2),'-')
ylabel('v1 in V')

title('primary voltage')
subplot(3,1,2)
plot(y(:,1),y(:,3),'-')
ylabel('v2'' in V')
title('secondary voltage')
subplot(3,1,3)
plot(y(:,1),y(:,4),'-')
ylabel('psim in Wb/sec')
title('mutual flux')
h2=figure;
clf;
subplot(3,1,1)
plot(y(:,1),y(:,5),'-')
ylabel('i1 in A')
title('primary current')
subplot(3,1,2)
plot(y(:,1),y(:,6),'-')
ylabel('i2'' in A')
title('secondary current')
disp('Save plots before typing return')

keyboard
close (h2)
% prompt for repeat with new system condition

repeat_run = input('Repeat with new system condition? Y/N: ','s');
if isempty(repeat_run) % if empty return a No to terminate
repeat_run = 'N';
end
end % while repeat_run

OUTPUT WAVEFORMS:
Fig 5.3 is a plot of the magnetization curve of the transformer in terms of the
instantaneous values of the flux linkage and magnetizing current on the 120 V,
winding 1 side.
Fig 5.3 Magnetization curve of distribution transformer.
(a) (b)
Fig. 5.4 (a) Transformer energized at the peak of vi (b) at the zero point of vi.

EXPERIMENT-6
MODELING OF THE DELTA-WYE CONNECTED TRANSFORMER
OBJECTIVES:
To simulate the Delta-Wye connected transformer and check the
characteristics.

BACKGROUND:
Fig. 6.1 shows a Delta-Wye connected transformer, where the secondary

neutral point, n, is grounded through resistor Rn. When the windings are
connected as shown, the effective secondary-to-primary turns ratio of the
three-phase connection is √3Ns/Np, and the secondary phasor voltages are
phase-shifted by 30o counter –clockwise to the corresponding primary phasor
voltages.
With the primary windings of the three transformers connected as shown in

6.1, the input voltages to the primary windings can be computed directly from
the sc source phase voltages using
The input voltages to the secondary windings of the transformers, on the other
hand, are a function of the secondary neutral point voltage to system ground,
that is
Where vnG = (ia + ib + ic) Rn. In the simulation, the line currents on the primary
side can be computed from the primary winding output currents using

The objective of this project are to determine the voltage and current ratios of
the delta-wye connected transformer as shown in above Fig 6.1, and to also to
examine the waveforms of the zero sequence current component on both sides
of the transformer.
Fig 6.1 Delta- Wye connected transformer
Set up the SIMULINK simulation s4 of the delta connected transformer

and ac source system shown in in Fig. 6.2, formed by three separate single –
phase units. Lets consider the situation when the situation when load across
each secondary winding is 1.5KVA, unity power factor. Note that the turns
ratio Np/Ns, is 0.5 and that the primed secondary voltages and currents are
reffered to the primary: such as, the load value used within the three load
modules should also be the load impedance reffered to the primary side. The
parametr and magnetization charecteristics of the three single-phase
transformer forming the delta-wye arrengement are identical. The voltages of
the three ac sources on the primary side are

Y U y
Scope Selector To Workspace
Mux Mux
Clock vab
-K-
T
(Ns/Np) iA
vAB T1
iAB
vAO s4 ia
S -K-
S5 1/3
ABan_unit 1/3
(Np/Ns)
v'an i'a
iAB+iBC+iCA
(Np/Ns)/3
-K-
Ref_Load an_
Sum
vBC T2
T3
iBC ia'+ib'+ic' vnG
vBO
S1 -K-
BCbn_unit
R_n(Np/Ns)
v'bn i'b Sum3
Ref_Load bn Initialize
and plot
vCA T4
T5 iCA m4
vCO
S2
CAcn_unit
v'cn i'c
Ref_Load cn
Fig. 6.2 (a) Simulation of s4 of Delta-Wye connected transformer
1
out_psi1
psi1 Mux i1
1 (u[1]-u[2])/xl1 3
1 Mux wb*(u[2]-(r1/xl1)*(u[3]-u[1]))
s out_i1
Fcn4
in_1 psi1_ Mux4
Fcn
Mux
psim
Mux xM*(u[1]/xl1+u[2]/xpl2-u[3]/xm) 2
out_psim
Fcn3
Mux3 Dpsi
Memory Look-Up
Table
1 psi2'
2 Mux wb*(u[2] -(rp2/xpl2)*(u[1]-u[3]))
s i2'
Mux (u[1]-u[2])/xpl2 4
in_2 psi2'_
Fcn2
Fcn5 out_i2'
Mux1 Mux2
Fig. 6.2 (b) Subsystem of ABan_unit, BCbn_unit and CAcn_unit
1 -24 1
out_1 HGR in_1
Fig. 6.2 (c) Subsystem of Ref_Load an, Ref_Load bn and Ref_Load cn

Voltage and current ratios: For this part of the project, we will ignore core
saturation. The core saturation in each transformer module can be deactivated
by opening the Dpsi loop. Use the MATLAB script file m4 to set up the
parameters and initial condition in MATLAB workspace for simulating s4. The
duration of the simulation run, tstop, is set inside m4 to be 1.5 seconds to
allow time for the variables to settle to steady state condition: however the
length of the to workspace array y is purposly kept short so that only the last
few cycle of the waveforms will be plotted. Using ode 15s or the Adams/Gear
numerical method, s4 will run satisfactorily with a minimum step size of 0.2
msec, a maximum step size of 10 msec, and an error tolerance of 2e-6.
Run m4 from the MATLAB command window and respond to itsprompt

to input the ohmic value of the secondary nutral resistor to ground, Rn, to 10
ohm. Run the simulation with the transformer operating with balance supply
and load, and obtain a plot of the line voltages and currents, vAB,vab,iA, and ia,
the zero sequence component of the winding and line current,(iAB+iBc+iCA)/3
and ( ia+ib+ic)/3, and the secondary neutral to ground voltage vnG, from the
circuit daigram in fig 4.17b, the voltage,vnG, may be expressed as
From the plotted waveforms, determine the following:

1. The ratio of the primary to secondary line to line voltages. Check it
against the nominal ratio of Np/√3Ns.
2. The ratio of the primary to secondary line currents. Chech it
against the nominal ratio of
√3Ns/Np..
3. The phase shift between the primary and secondary line to line
voltage vAB and vab.
Compare it with the phase shift between the primary and
secondary line currents, iA and ia. sketch the phasor daigram to
illustrate and cross check these phase shift in the voltages and
currents for the unity power factor load condition. For the primary
winding connection used, show that the sum of the primary line
current, that is ( iA+iB+iC), is zero.
Zero-sequence current: Repeat the above study, but with core saturation by
closing thr Dpsi loops in all three transformer modules. Set Rn to 10Ω and run
the simulation to obtain plot of the same set of variables. Comment on the
difference in the wave shape of the zero-sequence component of the primary
and secondary windings, as well as primary line currents.
Next, unbalance the secondary loading by halving only the resistive

component of RL load on phase a. with Rn still at 10Ω repeat the run and
examine the plots of the zero-sequence components of the winding and line

currents, (iAB+iBc+iCA)/3 and (ia+ib+ic)/3. Is there a change in the zero-sequence

component on the secondary winding due to the single-phase unbalance in
loading? Will there be a similar change in the zero-sequence component of the
primary line currents, ( iA+iB+iC)/3? Why not?
Finally, increase the value of Rn to some large value, say 100 timesthe
base impedance, Zb, of 1202/1500Ω, to approximate an ungrounded neutral of
the wye winding. With the secondary loading still unbalanced, repeat the run to
obtain a plot of the same three zero-sequence currents. Explain the presence or
absence of the zero-sequence current component in the primary and secondary
winding currents and in the primary line currents. Figure 6.3 shows the
voltages and currents of the Delta-wye transformer with the ungrounded
neutral connection of its wye secondary winding approximated by 100Zb when
the load on each secondary phase is 1.5kW.
MATLAB PROGRAM (m4 file):

% M-file for Project 4 on three-phase transformers in Chapter 4
% It sets up the parameter for the three two-winding units
% and plots some variables of the unit.
clear all;
% Set up identical circuit parameters and mag. curve
% for the three single phase transformers
Vrated = 120; % rms rated voltage

Srated = 1500; % rated VA
Frated = 60; % rated frequency in Hz
Zb = Vrated^2/Srated; % base impedance
wb = 2*pi*Frated; % base frequency
Vpk = Vrated*sqrt(2); % peak rated voltage
NpbyNs = 120/240; % nominal turns ratio
r1 = 0.25; % resistance of wdg 1 in ohms
rp2 = 0.134; % referred resistance of wdg 2 in ohms
xl1 = 0.056; % leakage reactance of wdg 1 in ohms
xpl2 = 0.056; % leakage reactance of wdg 1 in ohms
xm = 708.8; % unsaturated magnetizing reactance in ohms
xM = 1/(1/xm + 1/xl1 + 1/xpl2);
% mag. curve Dpsi versus psisat
Dpsi=[ -2454.6 -2412.6 -2370.5 -2328.5 -2286.4 -2244.4 -2202.3 ...

-2160.3 -2118.2 -2076.1 -2034.1 -1992.0 -1950.0 -1907.9 -1865.9 ...
-1823.8 -1781.8 -1739.7 -1697.7 -1655.6 -1613.6 -1571.5 -1529.5 ...
-1487.4 -1445.3 -1403.3 -1361.2 -1319.2 -1277.1 -1235.1 -1193.0 ...
-1151.0 -1108.9 -1066.9 -1024.8 -982.76 -940.71 -898.65 -856.60 ...
-814.55 -772.49 -730.44 -688.39 -646.43 -604.66 -562.89 -521.30 ...
-479.53 -438.14 -396.75 -355.35 -313.96 -272.56 -231.17 -192.60 ...
-154.04 -116.41 -81.619 -46.822 -19.566 0.0000 0.0000 0.0000 0.0000 ...
0.0000 0.0000 19.566 46.822 81.619 116.41 154.04 192.60 231.17 ...
272.56 313.96 355.35 396.75 438.14 479.53 521.30 562.89 604.66 ...
646.43 688.39 730.44 772.49 814.55 856.60 898.65 940.71 982.76 ...

1024.8 1066.9 1108.9 1151.0 1193.0 1235.1 1277.1 1319.2 1361.2 ...
1403.3 1445.3 1487.4 1529.5 1571.5 1613.6 1655.6 1697.7 1739.7 ...
1781.8 1823.8 1865.9 1907.9 1950.0 1992.0 2034.1 2076.1 2118.2 ...
2160.3 2202.3 2244.4 2286.4 2328.5 2370.5 2412.6 2454.6 ];
psisat=[ -170.21 -169.93 -169.65 -169.36 -169.08 -168.80 -168.52 ...

-168.23 -167.95 -167.67 -167.38 -167.10 -166.82 -166.54 -166.25 ...
-165.97 -165.69 -165.40 -165.12 -164.84 -164.56 -164.27 -163.99 ...
-163.71 -163.43 -163.14 -162.86 -162.58 -162.29 -162.01 -161.73 ...
-161.45 -161.16 -160.88 -160.60 -160.32 -160.03 -159.75 -159.47 ...
-159.18 -158.90 -158.62 -158.34 -157.96 -157.39 -156.83 -156.07 ...
-155.51 -154.57 -153.62 -152.68 -151.74 -150.80 -149.85 -146.08 ...
-142.31 -137.60 -130.06 -122.52 -107.44 -84.672 -42.336 0.0000 ...
0.0000 42.336 84.672 107.44 122.52 130.06 137.60 142.31 146.08 ...
149.85 150.80 151.74 152.68 153.62 154.57 155.51 156.07 156.83 ...
157.39 157.96 158.34 158.62 158.90 159.18 159.47 159.75 160.03 ...
160.32 160.60 160.88 161.16 161.45 161.73 162.01 162.29 162.58 ...
162.86 163.14 163.43 163.71 163.99 164.27 164.56 164.84 165.12 ...
165.40 165.69 165.97 166.25 166.54 166.82 167.10 167.38 167.67 ...
167.95 168.23 168.52 168.80 169.08 169.36 169.65 169.93 170.21 ];
% set up simulation parameters

tstop = 1.2; % stop time
Psi1o = 0; % initial value of wdg l flux linkage
Psip2o = 0; % initial value of wdg 2 flux linkage
Rload = 120^2/1500 % referred impedance to primary side of
% the 1.5 kVA, unity power factor load
% connected across each secondary winding
repeat_run = 'Y'; % set up repeat run flag

while repeat_run == 'Y'
disp('Setting up transformer simulation with m4.m')

Rn = input('Enter ohmic value of neutral to ground resistor Rn > ');
disp('Run simulation and return for plots')
keyboard
clf;
subplot(4,1,1)
plot(y(:,1),y(:,2),'-')
ylabel('vAB in V')
title('primary line voltage')
subplot(4,1,2)
plot(y(:,1),y(:,3),'-')
ylabel('vab in V')
title('secondary line voltage')
subplot(4,1,3)
plot(y(:,1),y(:,4),'-')
ylabel('iA in A')
title('primary line current')
subplot(4,1,4)
plot(y(:,1),y(:,5),'-')
ylabel('ia in A')
title('secondary line current')
h2=figure;
subplot(4,1,1)
plot(y(:,1),y(:,6),'-')

ylabel('(iAB+iBC+iCA)/3 in A')
subplot(4,1,2)
plot(y(:,1),y(:,7),'-')
ylabel('(ia+ib+ic)/3 in A')
subplot(4,1,3)
plot(y(:,1),y(:,8),'-')
ylabel('vnG in V')
title('Secondary neutral to ground voltage')
disp('Save plots before typing return')
keyboard
close(h2)
% prompt for repeat with new system condition

repeat_run = input('Repeat with new system condition? Y/N: ','s');
if isempty(repeat_run) % if empty return a No to terminate
repeat_run = 'N';
end
end % while repeat_run
OUTPUT WAVEFORMS:

Fig. 6.3 Voltages and currents of a Delta – Wye transformer

EXPERIMENT-7
SIMULATING TRANSFORMATION OF PHASE (ABC) TO DQ0.
OBJECTIVES:
Simulating transformation of phase (abc) to dq0.

BACKGROUND:
Figure 5.28 shows the overall daigram of s3. It is a Simulink implementation of

the phase to qd transformations as given in equation 5.130 and 5.145. in this
project we will use s3 and its accompanying matlab script file, m3 to examine
the waveform of the qd0 components corresponding to sinusoidal and complex
phase currents. As given in s3, the function blocks are programmed sinusoidal
abc currents of the form:
in s3, time is taken from the clock and multiplied by the value of angular
frequency to obtain the value of ωt, which is then fed to the three fcn function
modules that generate the sinusoidal three phase currents. the template for the
three fcn function module can be found in the Nonlinear library block of
Simulink. the value of m in the three function blocks is to be entered into the
MATLAB command window. fig 5.28b shows the inside of the abc2qd0s block.
this block implements eq 5.130 to transform the input abc phase quantities to
stationary qd0 quantities. fig5.28c shows the inside of the qds2qd block. this
block implements eq. 5.136 to transform the stationary
the inside of the qds2qd block. this block implements eq. 5.136 to transform
the stationary qd quantities to another qd reference frame that is at an angle of
θ to the stationary qds reference frame. The θ input to the qds2qd block can be
made a multiple, nframe, of the ωt input of the phase quantities with or
without some initial offset angle corresponding to the value of ϕ- θ(0) in eq
5.142, ϕ being the phase angle of the phase quantities as defined in eq.5.133
and θ(0) being the initial angle of θ in eq. 5.157 as programmed in s3, with the
currents in eq. 5.158 the value of ϕ is zero.
Shown in fig 5.29 are the qd0 currents for the case of m=1 and ϕ=0 in
eq.5.157, with an nframe of 1 that is rotating at synchronous speed in the
forward direction, and an initial angle, θ(0) of zero. the first three traces are in
the stationary reference frame. in

the synchronously rotating qd synchronous frame, the qd0 components of

fundamental frequency abc current are dc components. the form and
magnitude of these waveforms agree with those predicted by the analytical
expression of the stationary qd0 currents given in eq 5.134 for ϕ=0, and of the
qd components in the synchronously rotating frame given in eq 5.142.

1. run the case with m=1 and ϕ=0, but with nframe first set to -1 and then
to 2. based on the results obtained, deduce what will be the frequency of
the qd components for a balanced set of phase currents also having a
frequency of 5ω in a qd reference frame that is also rotating in the
forward direction at 5ω. use the simulation to verify your answer by
setting m and nframe to 5, and α to zero.

2. repeat the above cases, but with a α of 1, to see the form of the
transformer attenuated sinusoids in the two rotating qd0 reference
frames.
3. run the case of m=1 and nframe=1 for θ(0)=±𝜋/4. verify your results
using the expression given in eq 5.142.
4. run the case of m=2 and nframe=2 and examine the results obtained to
see if you can explain them.(Hint: determine the sequence of the abc
currents and the direction of rotation of their resultant mmf of their
space vector, i1).
5. modify the abc current fuction blocks in a copy of s3 to produce a set of
complex abc phase currents with fundamental and nth time harmonic
components of the form:

obtain the qd0 components in the synchronously rotating reference frame, that
is with nframe=1 and θ(0)=0, for n=5 and n=7.
OUTPUT WAVEFORMS:

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LAB MANUAL

MODELING OF ELECTRICAL SYSTEMS LAB

Department of Electrical Engineering

S. No Name of the Experiment Page

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 2

EQUIPMENT & COMPONENTS:

Fig 1.1 Parallel RLC circuit

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 3

Fig. 1.2 SIMULINK Simulation of RLCcircuit.

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 4

Before we can run the simulation, we must first initialize the

% M-file for Exercise 2 RLC circuit simulation

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 5

Fig. 1.3 RLC circuit response to a 100V step input vS.

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 6

EQUIPMENT & COMPONENTS:

Fig. 2.1 AC energization of an RL circuit.

The circuit equation for the RL circuit with an ac source is

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 7

The above integral equation is implemented in the SIMULINK file s3 using a

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 8

Fig. 2.2 RL circuit response to ac excitation.

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 9

EQUIPMENT & COMPONENTS:

Relative accuracy of circuit models for different line lengths.

Fig. 3.1 Three-phase bundled conductor line.

TABLE 3.1 SENDING END CONDITION

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 10

Thus, with full transposition, the GMD over a transposition cycle is

Real and reactive power transfer :

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 11

% M-file for Project 1 on line parameters and circuit models

% input conductor spacings, length, and resistance

s = (D12p- D1p2)/2; % conductor spacing of bundle in m

% RLC per m of line

% series RL circuit model parameters

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 12

% nominal pi circuit model parameters

% equivalent pi circuit model parameters

% compute sending-end condition

% Locus of PQ at receiving-end with changing angle of VS

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 13

end % end of for Vsm loop

Fig. 3.2 Loci of receiving end’s real and reactive power.

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 14

EQUIPMENT & COMPONENTS:

Figure 4.1: single-phase circuit.

The electrical parameters of the line are

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 15

(a) Overall diagram of S2 simulation

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 16

(b) Inside breaker

(c) Inside delay tc of breaker

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 17

(d) Inside the line block

(e) Inside the RL load block

Fig. 4.2 Simulation S2 of distributed line and breaker.

In figure 4.2a, the thevenin’s source inductance and operational logics of

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 18

Dept of Electrical Engineering |School of Engineering | Central University of Karnataka 19

% M-file for Project 2 on switching transients of a distributed parameter %

% m2.m sets up the parameters and initial condition

% Source voltage magnitude, frequency, and inductance

% Distributed line parameters