XILINX TOOL FLOW

SETUP

You have two options to run the ISE software from xilinx.

The first one is download the free version from Xilinx’s Website; install it on your
personal computer and run it from there. You can download the installation file
from: http://www.xilinx.com/ise/logic_design_prod/webpack.htm

The second one is use the Unix machines at the department; here you have to
source the following file each time you want to run xilinx ISE software:
source synopsys_vhdl_setup.source

Then you just have to write the command xilinx& to run the program. This
tutorial will follow the Unix version, there is no main difference in the procedure
that you have to follow if you use the Windows version.

SYNTHESIS

After you open Xilinx – ISE, you will get the following window that is composed of
four main panels; sources panel, processes panel, main panel and the console at
the bottom of the page.
Once this window is opened, you have to create a new project. Go to File – New
project; you will get a new window as the one shown below, that is the New
Project Wizard.

Make sure you select your cpeg422 directory in the Project Location

Type “isetutorial” in the Project Name field and make sure you have selected
“HDL” as the Top-Level Module Type. Click Next. You will get the following
window:
Make sure the properties on the table are filled as shown; this is the device that
you will be using in this class.

• Device Family: Spartan 2

• Device: XC2S50

• Package: tq144

• Speed Grade: -6

It is also important that you select as a synthesis tool “XST” and that the
generated simulation language is “VHDL”; click Next.

At this point you should have a new directory in your cpeg422 directory called
“isetutorial”; copy to that directory “timer.vhd” (or the vhd file to be synthesizes).
You can download the file from the course website under the downloads section:
www.eecis.udel.edu/~cbarrera/cpeg422/downloads/timer.vhd. Also you will need
the pin mapping file: “watch.ucf” that can be downloaded from:
www.eecis.udel.edu/~cbarrera/cpeg422/downloads/watch.ucf

Given the files are already created, you don’t need to create a new source file;
then you can click Next in the screen shown below:

Now you need to add the sources files to your project; click “Add Source…” in the
following window
You will get a new window showing your isetutorial directory; select the .vhd file
and click Open.

After that you will get another window; select “VHDL Design File” and click OK.
You will have to do the same with the watch.ucf file but this time you will not be
asked about the source type.
After you add all the source files, the Wizard window should look like this:

Click Next; you will get a summary window with the project information. Check
that everything is OK and click Finish. The Project Navigator window should look
like this:
If you double click “watch-watch_arch (timer.vhd)” in the Sources Panel, you will
get the VHDL code in main panel and you will see a list of processes shown in
the Processes Panel; one of them is the “Synthesize – XST” process; double
click it and wait until you get a “green check” next to it. Expand the process
clicking the “+” symbol on the left and you will see a screen identical to the one
shown below:

Double click the “Generate Post-Synthesis Simulation Model”; this will generate a
vhd file called “watch_synthesis.vhd”; this file will be used to do post-synthesis
simulation using Synopsys.

When it finishes you again get the green mark next to it; you can now compress
the Synthesis – XST process. Now you have to implement the design; again,
double click it and wait until you get the green mark. Then generate the bit file
that is the one you will download to the FPGA by double clicking “Generate
Programming File”. At the end you should have a screen as the one shown
below:

Once you have this, you can close the program; check in your
cpeg422/isetutorial directory that files watch_synthesis.vhd and watch.bit were
created.

Create a new directory inside the isetutorial directory; copy to that directory the
following files:
watch_synthesis.vhd – Just generated from Xilinx – ISE Software

timer_tb.vhd – Same testbench used for pre-synthesis simulation

.synopsys_vss.setup – download it from the website at:

www.ece.udel.edu/~cbarrera/cpeg422/downloads/.synopsys_vss.setup

Inside the new directory, create a new directory called WORK and follow tutorial
1 – Introduction to VHDL simulation. Remember, instead of using timer.vhd this
time you are using watch_synthesis.vhd