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NTD5802N, NVD5802N

MOSFET – Power, Single,


N-Channel, DPAK
40 V, 101 A
Features
• Low RDS(on) to Minimize Conduction Losses http://onsemi.com
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses V(BR)DSS RDS(on) ID
• MSL 1/260°C
40 V
4.4 mW @ 10 V 101 A
• 100% Avalanche Tested 7.8 mW @ 5.0 V 50 A
• NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101 D
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
N−Channel
Applications G
• CPU Power Delivery
• DC−DC Converters S
• Motor Driver
4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)


1 2
Parameter Symbol Value Unit 3
Drain−to−Source Voltage VDSS 40 V CASE 369C
DPAK
Gate−to−Source Voltage VGS ±20 V (Bent Lead)
Continuous Drain Cur- TC = 25°C ID 101 A STYLE 2
rent (RqJC) (Note 1)
TC = 85°C 78
MARKING DIAGRAMS
Power Dissipation TC = 25°C PD 93.75 W
(RqJC) (Note 1)
& PIN ASSIGNMENT
Steady
Continuous Drain Cur- State TA = 25°C ID 16.4 A 4
rent (RqJA) (Note 1) Drain
TA = 85°C 12.7
Power Dissipation TA = 25°C PD 2.5 W
AYWW

02NG

(RqJA) (Note 1)
58

Pulsed Drain Current tp=10ms TA = 25°C IDM 300 A


Current Limited by Package TA = 25°C IDmaxPkg 45 A 2
Operating Junction and Storage Temperature TJ, Tstg −55 to °C 1 Drain 3
Gate Source
175
Source Current (Body Diode) IS 50 A A = Assembly Location*
Y = Year
Drain to Source dV/dt dV/dt 6.0 V/ns
WW = Work Week
Single Pulse Drain−to−Source Avalanche En- EAS 240 mJ 5802N = Device Code
ergy (VDD = 32 V, VGS = 10 V, G = Pb−Free Package
L = 0.3 mH, IL(pk) = 40 A, RG = 25 W)
* The Assembly Location code (A) is front side
Lead Temperature for Soldering Purposes TL 260 °C
optional. In cases where the Assembly Location is
(1/8″ from case for 10 s)
stamped in the package, the front side assembly
Stresses exceeding those listed in the Maximum Ratings table may damage the code may be blank.
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:


May, 2019 − Rev. 8 NTD5802N/D
NTD5802N, NVD5802N

THERMAL RESISTANCE MAXIMUM RATINGS


Parameter Symbol Value Unit
Junction−to−Case (Drain) RqJC 1.6 °C/W
Junction−to−Ambient − Steady State (Note 1) RqJA 60
Junction−to−Ambient − Steady State (Note 2) RqJA 105
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)


Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 10 mA 40 V
Drain−to−Source Breakdown Voltage V(BR)DSS/TJ 40 mV/°C
Temperature Coefficient
Zero Gate Voltage Drain Current IDSS VGS = 0 V, TJ = 25°C 1.0 mA
VDS = 40 V TJ = 150°C 50
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA 1.5 3.5 V
Negative Threshold Temperature Co- VGS(TH)/TJ −7.4 mV/°C
efficient
Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 50 A 3.6 4.4 mW
VGS = 5.0 V, ID = 50 A 6.5 7.8
Forward Transconductance gFS VDS = 15 V, ID = 15 A 16.8 S
CHARGES AND CAPACITANCES
Input Capacitance Ciss 5300 pF
Output Capacitance Coss VGS = 0 V, f = 1.0 MHz, 850
VDS = 12 V
Reverse Transfer Capacitance Crss 550
Input Capacitance Ciss VGS = 0 V, f = 1.0 MHz, 5025 pF
VDS = 25 V
Output Capacitance Coss 580
Reverse Transfer Capacitance Crss 400
Total Gate Charge QG(TOT) 75 100 nC
Threshold Gate Charge QG(TH) VGS = 10 V, VDS = 15 V, 6.0
Gate−to−Source Charge QGS ID = 50 A 18
Gate−to−Drain Charge QGD 15
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(on) 14 ns
Rise Time tr VGS = 10 V, VDS = 20 V, 52
Turn−Off Delay Time td(off) ID = 50 A, RG = 2.0 W 39
Fall Time tf 8.5
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.

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NTD5802N, NVD5802N

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued)


Parameter Symbol Test Condition Min Typ Max Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V, TJ = 25°C 0.9 1.2 V
IS = 50 A

VGS = 0 V, TJ = 25°C 0.8 1.0


IS = 20 A

Reverse Recovery Time tRR 25 ns


Charge Time ta VGS = 0 V, dIs/dt = 100 A/ms, 15
Discharge Time tb IS = 50 A 10
Reverse Recovery Charge QRR 15 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.

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NTD5802N, NVD5802N

TYPICAL PERFORMANCE CHARACTERISTICS

200 200
10 V 6V VDS ≥ 10 V
180 VGS = 5 V
7V
160
ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)


150
140 TJ = 25°C
120 4.5 V

100 100
TJ = 25°C
80 4.2 V
60
4V 50 TJ = 100°C
40
3.8 V
20 3.6 V TJ = −55°C
0 0
0 1 2 3 4 5 6 2 3 4 5 6
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

0.010 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.015


VGS = 10 V 0.014 TJ = 25°C
0.013 VGS = 5 V
0.008 0.012
0.011
TJ = 150°C 0.010
0.009
0.006
0.008
0.007
TJ = 25°C 0.006
0.004 0.005
TJ = −55°C 0.004 VGS = 10 V
0.003
0.002 0.002
10 30 50 70 90 110 130 150 170 190 30 50 70 90 110 130 150 170 190
ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Drain Current Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE

1.7 100000
ID = 50 A VGS = 0 V
1.6
VGS = 10 V
1.5
IDSS, LEAKAGE (nA)

1.4
10000 TJ = 150°C
(NORMALIZED)

1.3
1.2
1.1
1000
1
TJ = 100°C
0.9
0.8
0.7 100
−50 −25 0 25 50 75 100 125 150 175 2 6 10 14 18 22 26 30 34 38
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature vs. Voltage

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NTD5802N, NVD5802N

TYPICAL PERFORMANCE CHARACTERISTICS

8000 15 30

VDS, DRAIN−TO−SOURCE VOLTAGE (V)


VGS, GATE−TO−SOURCE VOLTAGE (V)
Ciss VGS = 0 V ID = 50 A
7000 TJ = 25°C TJ = 25°C
12 24
6000 QT
C, CAPACITANCE (pF)

5000 9 VGS 18
VDS
4000
6 12
3000 QGS QDS
2000
Coss 3 6
1000
Crss
0 0 0
10 5 0 5 10 15 20 25 30 35 40 0 20 40 60 80
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLT- Qg, TOTAL GATE CHARGE (nC)
AGE (V) Figure 8. Gate−to−Source and
Figure 7. Capacitance Variation Drain−to−Source Voltage vs. Total Charge

1000 60
VDD = 20 V
ID = 50 A VGS = 0 V
td(off) 50 TJ = 25°C
IS, SOURCE CURRENT (A)
VGS = 10 V
tr
100 40
t, TIME (ns)

tf td(on) 30

10 20

10

1 0
1 10 100 0.4 0.6 0.8 1.0 1.2 1.4
RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current
vs. Gate Resistance

1000
ID, DRAIN CURRENT (A)

100
10 ms

100 ms
10 1 ms
VGS = 10 V 10 ms
Single Pulse
dc
1 TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

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NTD5802N, NVD5802N

TYPICAL PERFORMANCE CHARACTERISTICS

10
r(t), Effective Transient Thermal Resistance

D = 0.5
1
0.2
(°C/W)

0.1
0.05
0.1

0.02
0.01
Single Pulse
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t, PULSE TIME (s)

Figure 12. Thermal Response

ORDERING INFORMATION
Order Number Package Shipping†
NTD5802NT4G DPAK 2500 / Tape & Reel
(Pb−Free)

NVD5802NT4G* DPAK 2500 / Tape & Reel


(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.

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NTD5802N, NVD5802N

PACKAGE DIMENSIONS

DPAK (SINGLE GAUGE)


CASE 369C
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
A Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 MENSIONS b3, L3 and Z.
B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 Z Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D OUTERMOST EXTREMES OF THE PLASTIC BODY.
DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUM
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.

L4 INCHES MILLIMETERS
NOTE 7
DIM MIN MAX MIN MAX
b2 c BOTTOM VIEW BOTTOM VIEW A 0.086 0.094 2.18 2.38
e SIDE VIEW ALTERNATE A1 0.000 0.005 0.00 0.13
b CONSTRUCTION b 0.025 0.035 0.63 0.89
b2 0.028 0.045 0.72 1.14
TOP VIEW 0.005 (0.13) M C H
b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
GAUGE SEATING
L2 PLANE C PLANE
c2 0.018 0.024 0.46 0.61
D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
L H 0.370 0.410 9.40 10.41
A1 L 0.055 0.070 1.40 1.78
L1 L1 0.114 REF 2.90 REF
DETAIL A L2 0.020 BSC 0.51 BSC
ROTATED 905 CW L3 0.035 0.050 0.89 1.27
L4 −−− 0.040 −−− 1.01
Z 0.155 −−− 3.93 −−−

STYLE 2:
SOLDERING FOOTPRINT* PIN 1. GATE
2. DRAIN
3. SOURCE
6.20 3.00 4. DRAIN
0.244 0.118
2.58
0.102

5.80 1.60 6.17


0.228 0.063 0.243

SCALE 3:1 ǒinches


mm Ǔ

*For additional information on our Pb−Free strategy and soldering


details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION


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