IET Renewable Power Generation

Research Article

Multilevel inverter for interfacing renewable ISSN 1752-1416

Received on 17th January 2017
Revised 9th August 2017
energy sources with low/medium- and high- Accepted on 8th September 2017
E-First on 20th October 2017
voltage grids doi: 10.1049/iet-rpg.2016.1034
www.ietdl.org

Rekha Agrawal1 , Shailendra Jain1

1Department of Electrical Engineering, MANIT, Bhopal, Madhya Pradesh, India
E-mail: rekha.agrawal09@gmail.com

Abstract: This study presents a new multilevel inverter (MLI) with reduced devices, for low/medium- and high-voltage
applications. The proposed MLI is evolved from existing cross-connected source-based multilevel inverter (CCS-MLI), results in
reduced switches, driver circuits, diodes, and DC voltage sources when compared with the classical CHB, CCS-MLI, and other
MLIs. Owing to reduced device numbers, the complexity, size, cost, and maintenance of the proposed topology are greatly
reduced. The detailed analysis and working of the proposed topology is presented along with its comparison with classical,
CCS-MLI, and other MLIs. Different algorithms are presented for selecting appropriate magnitudes of DC voltage sources to
generate different voltage levels in the output. The proposed MLI is suitable for grid integration of renewable energy sources.
The concept is presented through modelling and simulation in MATLAB/Simulation environment and validated through real-time
simulator OPAL-RT (OP-4500).

1 Introduction
Recently, grid-connected multilevel inverters (MLIs) have been
researched for integration and utilisation with renewable energy
sources (RES) [1–3]. Numerous MLIs have been investigated for
grid- and microgrid-connected systems successfully [4]. Earlier,
two-level inverters with step-up transformer and output filter were
commonly used for grid integration. Nowadays, MLIs are proposed
without transformers and filters for low/medium-voltage
applications (L/M VA), and with high-frequency transformer for
high-voltage applications (HVA) [5]. As per international
standards, L/M VA are allowed without galvanic isolation, whereas
HVA require high-frequency transformer for isolation [6, 7]. The
size and weight of high-frequency transformer is much less when
compared with fundamental frequency transformer. Hence, MLIs
with high-frequency transformers are commonly known as
transformerless systems [8].
Further, filter requirement reduces with an increase in output
voltage levels in MLIs [9, 10]. As a result, today's MLIs with
increased output levels allow filterless and transformerless
operation for L/M VA and HVA for grid integration. This results in
reduced size, weight, and overall volume of the system
significantly [11, 12].
Three classical MLI topologies commonly used for DC–AC
conversion are diode-clamped, flying capacitor (FC), and cascaded
H-bridge (CHB) [13–18]. However, the increase in the number of
controlled switches, driver circuits, auxiliary components
(clamping diodes or FCs), and DC sources for increase in output
levels are the major drawback associated with classical MLIs.
Therefore, MLIs with reduced component count and less
complexity are researched and developed as a viable alternative.
A review of various MLI topologies with the idea of reduced
component count is presented in [19]. Recently, modular multilevel
converter has generated great interest as they can be extended for
the higher voltage applications with a simple modular structure
[20, 21]. In other topologies, symmetric design of the MLI is
reported [22]. The main advantage of this topology is its fewer
component count compared with CHB. With reduction in
component count, the circuit becomes less complex. Additionally,
the cost and size of system also reduces. However, its implement
ability only with symmetric voltage sources is the main limitation
of this topology. Also, voltage stress across H-bridge switches is
equal to the sum of all operating input DC sources. Another
topology proposed for the reduced number of switches [23], needs
bidirectional switches, increases its component count when
compared with other topologies. The symmetric and asymmetric
MLI topology with reduced number of devices have been
thoroughly explored in the literature with the name cross-
connected source-based multilevel inverter (CCS-MLI) [24, 25].
The main limitation of this topology is that the number of DC
sources and drivers is not reduced. Similarly, the symmetric and
asymmetric MLIs with reduced number of devices have been
presented in [26], but the number of DC sources and drivers is not
reduced.
An attempt has been made to reduce the number of devices in
[27], but the use of single DC source makes them unsuitable for
HVA. In [28], another topology is proposed for both symmetric and
asymmetric configurations, with reduced number of devices, but it
requires bidirectional switches (which utilise a configuration of
single switch with four diodes), increases the voltage drop and
number of diodes in the topology.
In this paper, a new MLI topology is proposed, analysed, and
implemented for L/M VA and HVA, specifically for grid
integration. In addition, the generalised structure of the proposed
topology is also discussed. The main advantages of the proposed
structure are: reduction in component count, size, maintenance, and
complexity, which is confirmed through its comparison with
classical MLI, CCS-MLI, and other MLI topologies. Nearest level
control (NLC) technique is adopted to generate control pulses.
NLC technique generates lower total harmonic distortion (THD)
than other modulation techniques, for the same number of levels.
For grid integration, the THD of output voltage should be <5% (as
per IEEE-519) with minimum number of power components.
Finally, a design example of the proposed topology is presented
and validated through real-time simulation to ascertain its
performance and feasibility.
2 Proposed structure
Fig. 1 shows the fundamental unit of the proposed MLI, which
synthesises AC output from input DC sources, with the proper
combination of switches. The proposed MLI consist of eight
switches (six unidirectional and one bi-directional switch having
two switches), two DC voltage sources, and one voltage divider
which consists of two series capacitors. The main advantages of

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Fig. 1  Fundamental unit of proposed MLI (U, unidirectional switches; B1, bidirectional switch)

Table 1 Source combination, operating mode, and number of component used in fundamental unit of proposed MLI
Proposed MLI
V1:V2  Operation Output No. of switches  No. of diodes  No. of drivers  No. of isolated DC No. of capacitors 
mode  levels  sources 
2 V:V asymmetric 7 8 8 7 2 2
V:V symmetric 9 8 8 7 2 2
2 V:3 V asymmetric 11 8 8 7 2 2

Table 2 Switching states to generate 7, 9, and 11 levels using distinct choices of DC voltage sources in basic block of
proposed MLI
States Switching states Output voltage 7-Level (2 V:V) 9-Level (2 V:2 V) 11-Level (2 V:3 V)
U1 U1′ U2 U2′ U3 U3′ B1
positive level
 a 0 1 1 0 0 1 0 VC1 + VC2 + V2 3 V 4V 5V
 b 0 0 1 0 0 1 1 VC1 + V2 2 V 3 V 4 V
 c 0 1 1 0 1 0 0 VC1 + VC2 2 V 2 V 2 V
 d 1 0 1 0 0 1 0 V2 V 2 V 3 V
 e 0 0 1 0 1 0 1 VC1 V V V
zero level
 f 1 0 1 0 1 0 0 0 0 0 0
 g 0 1 0 1 0 1 0 0 0 0 0
negative level
 h 0 0 0 1 0 1 1 −VC2 −V −V −V
 i 0 1 0 1 1 0 0 −V2 −V −2 V −3 V
 j 1 0 0 1 0 1 0 −VC1 − VC2 −2 V −2 V −2 V
 k 0 0 0 1 1 0 1 −VC2 − V2 −2 V −3 V −4 V
 l 1 0 0 1 1 0 0 −VC1 − VC2 − V2 −3 V −4 V −5 V
Here, V1 = VC1 + VC2, VC1 = VC2

using voltage divider are to reduce the number of DC sources, and
to maintain natural balancing of voltage across the capacitors.
The proposed MLI is capable of generating 7-level, 9-level, and
11-level in the output, using the same number of switches, with the
combination of DC sources V1:V2 in the ratio of 2 V:V, V:V, and 2 
V:3 V.
Table 1 shows that the 7-level, 9-level, and 11-level in output
voltage can be produced using similar number of component count
shown in the proposed MLI fundamental block consisting of eight
switches, eight diodes, seven gate drivers, two isolated DC sources,
and two capacitors. The mode of operation is presented in the next
section depending on the source values.
In this section, operation of the proposed MLI fundamental unit
is described for a single-phase structure. With the proposed MLI
fundamental block, the possible combinations of input DC sources
are: ±(VC1 + VC2 + V2), ±(VC1 + VC2), ±(V2), +(VC1 + V2), +(VC1), 0,
−(VC2 + V2), +(VC2) using positive level states (a, b, c, d, e), zero
level states (f, g), and negative level states (h, i, j, k, l) as shown in
Table 2. The different output levels (7, 9, and 11) can be obtained
by changing the magnitude of the input DC voltage sources in the
ratio of (2 V:V, V:V, 2 V:3 V), respectively.
3 Expanded structure of proposed MLI for L/M VA
In the proposed MLI, the number of levels in the output can be
increased by increasing the capacitor count to ‘n’ with ‘n−1’ bi-
directional switches. The expanded structure of the proposed
single-phase MLI along with switch ‘B’ configuration is shown in
Figs. 2a and b, respectively. The proposed structure can only be
used for L/M VA, because the voltage stresses on switches U2 and
U2′ are equal to the sum of input DC source voltages. Photovoltaic
(PV) panels, fuel cells, and rectified output of wind energy can be
used as DC sources as shown in Fig. 2c. To maintain constant
voltage across PV and fuel cells, suitable DC/DC converters are
used along with it. Table 3 shows the generalised equations for
proposed MLI circuit device count.

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Fig. 2  Configuration of
(a) Expanded configuration of the proposed ‘L-level’ single-phase MLI for L/M VA, (b) Switch ‘B’ configuration, (c) Possible DC sources

Table 3 Generalised equation for circuit device count for L/M VA

Source ratio V1:V2  Output No. of switches  No. of diodes  No. of drivers  No. of isolated Variety of DC
levels  DC sources  sources 
V1 = jV V2 = V j = 2, 3, 4, …, n 2j + 3 2j + 4 2j + 4 j + 5 2 2
V1 = jV V2 = V1 j = 2, 3, 4, …, n 4j + 1 2j + 4 2j + 4 j + 5 2 1
V1 = jV V2 = (j + 1)V j = 2, 3, 4, …, n 4j + 3 2j + 4 2j + 4 j + 5 2 2

Fig. 3  Proposed expanded configuration of ‘L-level’ proposed single-phase MLI for HVA

Table 4 Generalised equation of proposed MLI power components for HVA

V1:V2  Mode  Output levels ‘L’  No. of No. of No. of No. of isolated No. of
switches  diodes  drivers  DC sources  capacitors 
2 V:V asymmetric (M−1) 6n + 1 8n 8n 7n 2n 2n
V:V symmetric (M−2) 8n + 1 8n 8n 7n 2n 2n
2 V:3 V asymmetric (M−3) 10n + 1 8n 8n 7n 2n 2n

Table 5 Parameters comparison of single-phase (1−Ф) MLIs (L number of levels)

Topologies  Proposed MLI (L/M Proposed MLI CHB  CCS-MLI [24, MLI topology MLI topology
VA)  (HVA)  25]  [26]  [28] 
no. of switches (L + 7)/2 L − 1 2(L − 1) 3(L − 1)/2 3(L − 1)/2 3(L − 1)/2
no. of diodes (L + 7)/2 L − 1 2(L − 1) 3(L − 1)/2 3(L − 1)/2 3(L + 18)/2
no. of drivers (L + 19)/4 7(L − 1)/8 2(L − 1) 3(L − 1)/2 3(L − 1)/2 3(L − 1)/2
no. of isolated DC 2 (L − 1)/4 (L − 1)/2 (L − 1)/2 (L − 1)/2 (L − 1)/2
sources
no. of capacitors (L − 1)/4 (L − 1)/4 not required not required not required not required

4 Expanded structure of proposed MLI for HVA
For HVA, the number of levels in the output can be increased by
cascade connection of ‘n’ fundamental blocks of proposed MLI.
Fig. 3 shows the cascaded structure of the proposed MLI. The
generalised equations for proposed MLI power circuit device count
for HVA are illustrated in Table 4.
5 Comparison of proposed structures
To demonstrate the ascendancy of proposed MLI over classical
CHB, CCS-MLI, and other MLIs, a comparative study of these
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topologies for single-phase (1−Ф) configuration is presented in this
section. For the (3−Ф) system, the number of devices will be three
times of a (1−Ф) system. The comparison made in terms of power
circuit device count (number of switches, diodes, drivers, DC
sources, and capacitors), used in terms of number of levels, is
shown in Table 5. This is done for symmetric configuration.
Comparison of different 1−Ф topologies in graphical form is
shown in Fig. 4. Fig. 4a shows the comparison of the number of
switches used against the number of output levels. The graph
shows that the proposed MLI uses lesser number of switches with
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Fig. 4  Comparison of 1−Ф proposed MLI with CHB and other MLIs with variation of
(a) ‘L’ versus number of switches,
(b) ‘L’ versus number of diodes,
(c) ‘L’ versus number of drivers,
(d) ‘L’ versus number of DC supplies
increases in output voltage levels. A reduction in switches is
remarkable in L/M VA-based expanded structure.
Fig. 4b points out the comparison of the number of diodes used.
It is clear from the figure that the utilised number of diodes is much
lower in the proposed MLI than the classical CHB and other MLIs,
mainly for HVA-based expanded structure. Fig. 4c shows the
comparison graph between proposed and other MLIs in terms of
required drivers. This comparison shows that the proposed MLI
requires less number of drivers, especially in L/M VA-based
proposed MLI. This feature of the proposed MLI leads to the
reduction in gate driver protection and cooling circuits also. Fig. 4d
shows comparison in terms of required isolated DC sources versus
the number of levels. As observed, the number of required DC
power supplies in the L/M VA-based proposed MLI is minimum
when compared with other MLI topologies.
From Fig. 4, it can be concluded that the proposed MLI
generates higher number of output levels by using the lower
number of devices, when compared with CHB and other presented
MLIs. This results in reduced component count, size, maintenance,
and complexity of the system.
6 Modulation scheme
Several modulation techniques are available in the literature for
generation of desired voltage levels [29]. These include
multicarrier-pulse width modulation (MC-PWM), space vector
PWM (SVPWM) [30], selective harmonic elimination (SHE) [31],
and NLC [32]. Among these, MC-PWM is the high switching
frequency-based modulation scheme in which sinusoidal reference
signal is compared with triangular carrier signals, also known as
sinusoidal PWM (SPWM). The MC-PWM technique is widely
used due to its simplicity in implementation for any number of
levels, and provides excellent result in many applications. SVPWM
and SHE are high switching frequency and fundamental switching
frequency-based modulation techniques, respectively, with lowest
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THD and reduced switching losses. However, the main challenge
associated with the SVPWM method is the calculation of vector
times and switching patterns, while calculation of switching angles
is a difficult task in the SHE scheme. Therefore, another low
switching frequency-based modulation scheme known as NLC is
used in the proposed work to modulate the proposed MLI [33].
The implementation of the NLC method is simpler when
compared with other low switching frequency-based modulation
schemes. It also has the advantage of generating lowest THD (one
of the requirements of grid integration) for the same number of
levels in the output, and lower switching losses when compared
with MC-PWM or SPWM technique. In the NLC method, the
reference signal is normalised by round function, which gives the
closest output signal. The schematic diagram of the NLC
modulation scheme is shown in Fig. 5a. The reference sinusoidal
signal is normalised by a DC supply voltage, then round it by
round function. The generated synthesise signal has the same
number of output levels as required in the output waveform. Thus,
the derived synthesised signal is used to drive those switches which
have to remain ON for the corresponding voltage level.
Comparison of two modulation schemes: MC-PWM or SPWM
and NLC in terms of THD of output voltage are presented in
Fig. 5b. As observed, THD of output voltage is less when
compared with MC-PWM, for the same number of levels.
7 Results and discussion
7.1 Simulation results
To analyse the performance of the proposed MLI, simulation
model of Figs. 2a and 3 in single phase (1−Ф) and three phase
(3−Ф) is developed in MATLAB/Simulink environment for L/M
VA and HVA, respectively. The 3−Ф configuration of the proposed
MLI can be realised using three 1−Ф legs of Figs. 2a and 3 for
L/M VA and HVA, respectively. Simulation parameters for the
proposed MLI are given in Table 6. A number of levels are chosen,
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Fig. 5  NLC technique
(a) Schematic diagram of NLC modulation scheme for ‘L’ level,
(b) THD comparison of MC-PWM and NLC

Table 6 Simulation parameters of proposed 1−Ф and 3−Ф MLI

application low/medium voltage high voltage
phase 1−Ф 3−Ф 1−Ф 3−Ф
circuit structure Fig. 2a Fig. 3
RMS voltage VL–N = 230 V VL–L = 400 V VL–N = 6.2 kV VL–L = 11 kV
mode symmetric asymmetric
Irms 15 A 400 A
R–L load 20 Ω, 50 mH 20 Ω, 50 mH
apparent output power 10.5 kW 7.6 MW
modulation technique NLC NLC
number of levels 17 29 19 33
THD 4.84% 4.14% 4.29% 3.81%
number of switches/diodes/drivers/DC supply/capacitors 12/12/9/2/4 36/36/27/6/12 24/24/21/6/6 72/72/63/18/18
magnitude of each DC source 164 V 1946 V, 973 V

such that the THD of the output voltage waveform should be <5%
as per IEEE-519 standard. The NLC switching modulation
technique is used for modulation.
In the simulation study, the value of DC voltage sources is set at
164 V for each source to operate the topology in symmetric mode
and load parameters for L/M VA structure are taken as 20 Ω, 50  <5% limit. Voltages across capacitors are shown in Fig. 6c. It is
mH. Whereas for HVA, asymmetric configuration is preferred with
DC sources of values 1946 and 973 V, respectively, for each basic
block and load parameters are taken as 20 Ω, 50 mH.
For HVA, asymmetric mode (M−1) circuit is used because in
this mode, switches bear less voltage stress when compared with
other modes. Details regarding generated levels, THD, RMS
voltage magnitude, number of switches, number of diodes, number
of drivers, number of DC supplies, and number of capacitors are
given in Table 6 for both the application-oriented structures. All the
possible switching states required to generate different levels in the
output are enlisted in Table 7.
It should be noted that in both the circuits, the switch pairs (U2,
U2′) and (U3, U3′) are operated in complimentary manner and switch
pair (U1, U1′) can remain ‘OFF’ simultaneously but cannot remain
‘ON’ at the same time. Fig. 6a shows the 17-level output phase
voltage, output phase current, and corresponding THD of phase
1826
voltage for L/M VA. Current lags the respective phase voltage due
to inductive nature of load. Also, THD of output voltage is found
to be <5%.
Fig. 6b shows the 3−Ф line voltages of 29-level MLI and THD
of one of the output line voltage waveform, which is found to be
found that the voltages across the capacitors are naturally balanced.
Fig. 7 shows the performance of 19-level output phase voltage
and 33-level output line voltage MLI topology for HVA. Line to
neutral voltage and current along with its THD are shown in
Fig. 7a, whereas 3–Ф line-to-line voltages and frequency spectrum
of one voltage are shown in Fig. 7b. Fig. 7c shows the naturally
balanced voltage across the voltage divider capacitors.
7.2 Real-time simulation
The proposed concept is validated with the help of real-time
simulation using RT-LAB real-time simulator (RTS) Opal-RT
(OP-4500). RT-LAB comes with transient solvers and component
libraries. It has the capability of parallel computing in real time and
gives results which are equivalent to hardware results.
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Table 7 Switch states to generate 17-level and 19-level in an output phase voltage of proposed MLI for L/M VA and HVA,
respectively
Output levels ‘ON’ switches
Low/medium-voltage applications High-voltage applications
1st block 2nd block 3rd block
1 U3, U2, B1 B1,1, U2,1, U3,1 U1,2, U2,2, U3,2 U1,3, U2,3, U3,3
2 U3, U2, B2 U1,′ 1, U2,1, U3,1 U1,2, U2,2, U3,2 U1,3, U2,3, U3,3
3 U3, U2, B3 U1,′ 1, U2,1, U3,′ 1 U1,2, U2,2, U3,2 U1,3, U2,3, U3,3
4 U3′, U2, U1/U3, U2, U1′ U1,′ 1, U2,1, U3,′ 1 B1,2, U2,2, U3,2 U1,3, U2,3, U3,3
5 U3′, U2, B1 U1,′ 1, U2,1, U3,′ 1 U1,′ 2, U2,2, U3,2 U1,3, U2,3, U3,3
6 U3′, U2, B2 U1,′ 1, U2,1, U3,′ 1 U1,′ 2, U2,2, U3,′ 2 U1,3, U2,3, U3,3
7 U3′, U2, B3 U1,′ 1, U2,1, U3,′ 1 U1,′ 2, U2,2, U3,′ 2 B1,3, U2,3, U3,3
8 U3′, U2, U1′ U1,′ 1, U2,1, U3,′ 1 U1,′ 2, U2,2, U3,′ 2 U1,′ 3, U2,3, U3,3
9 — U1,′ 1, U2,1, U3,′ 1 U1,′ 2, U2,2, U3,′ 2 U1,′ 3, U2,3, U3,′ 3
0 U3, U2, U1 /U3′, U2′, U1′ U1,1, U2,1, U3,1 U1,2, U2,2, U3,2 U1,3, U2,3, U3,3
−1 U3′, U2′, B3 B1,1, U2,′ 1, U3,′ 1 U1,2, U2,2, U3,2 U1,3, U2,3, U3,3
−2 U3′, U2′, B2 U1,1, U2,′ 1, U3,′ 1 U1,2, U2,2, U3,2 U1,3, U2,3, U3,3
−3 U3′, U2′, B1 U1,1, U2,′ 1, U3,1 U1,2, U2,2, U3,2 U1,3, U2,3, U3,3
−4 U3, U2′, U1′/U3′, U2′, U1 U1,1, U2,′ 1, U3,1 B1,2, U2,′ 2, U3,′ 2 U1,3, U2,3, U3,3
−5 U3, U2′, B3 U1,1, U2,′ 1, U3,1 U1,2, U2,′ 2, U3,′ 2 U1,3, U2,3, U3,3
−6 U3, U2′, B2 U1,1, U2,′ 1, U3,1 U1,2, U2,′ 2, U3,′ 2 U1,3, U2,3, U3,3
−7 U3′, U2′, B3 U1,1, U2,′ 1, U3,1 U1,2, U2,′ 2, U3,2 B1,3, U2,′ 3, U3,′ 3
−8 U3, U2′, U1 U1,1, U2,′ 1, U3,1 U1,2, U2,′ 2, U3,2 U1,3, U2,′ 3, U3,′ 3
−9 — U1,1, U2,′ 1, U3,1 U1,2, U2,′ 2, U3,2 U1,3, U2,′ 3, U3,3

The structures are simulated using the same parameters as

shown in Table 6. ‘Analogue out’ ports of RTS can generate
maximum output signal up to ±16 V. Therefore, the signals of the
simulated models are proportionally reduced to get the output
signals within or ADC signal range. For example, simulated
maximum phase output voltage 325 Vp–p (or 230 Vrms) is divided
by 30 (325/30 = 10.83 V) to get the results in permissible range.
Fig. 8a shows the output voltage (VLN) and respective phase
current waveform obtained through RTS OP-4500 for L/M VA,
whereas Fig. 8b shows the 3−Ф line voltages. The phase voltage
and respective current waveforms and line voltages waveforms are
shown in Figs. 8c and d, respectively, for HVA. This clearly
indicates that the multilevel output voltages are very close to
sinusoidal with THD <5%, and are suitable for grid interface
without the use of the transformer and filter.

8 Conclusion
This paper presents a new MLI topology for L/M VA and HVA
specifically designed for grid interface, using RES as input sources.
The proposed MLI uses less number of switches, diodes, drivers,
and DC sources to reduce circuit size, complexity, cost, and
maintenance. The basic block and generalised structure of
proposed MLI for L/M VA and HVA are presented. To show the
ascendency of proposed MLI, it is compared with CHB, CCS-MLI,
and other MLIs. The low switching frequency-based NLC
modulation technique is also discussed and compared with high-
frequency-based multicarrier PWM to show its suitability.
MATLAB/Simulation and its real-time implementation show
satisfactory performance of the proposed MLI, for grid interface.

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Fig. 6  Simulation results of proposed MLI for L/M VA (shown in Fig. 2a)
(a) Output voltage VL–N, current, and corresponding THD of output voltage VL–N, (b) Output line voltages and corresponding THD of output voltage VL–L, (c) Voltages across
capacitors C1, C2 and C3, C4

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Fig. 7  Simulation results of proposed MLI for HVA (shown in Fig. 3)
(a) Output voltage VL–N, current, and corresponding THD of output voltage VL–N, (b) Output line voltages and corresponding THD of output voltage VL–L, (c) Voltages across
series-connected capacitors (C1,1, C2,1), (C1,2, C2,2), and (C1,3, C2,3)

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Fig. 8  Results of RTS OPAL-RT OP-4500
(a) Output voltage (VLN) and phase current waveform for L/M VA, (b) 3−Ф line voltages for low-voltage 400 V applications, (c) Output voltage (VLN) and phase current waveform
for HVA, (d) 3−Ф line voltages waveform for high-voltage 11 kV applications
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