IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO.
5, MAY 2015 2859
A Modular Multilevel Converter Pulse Generation
and Capacitor Voltage Balance Method
Optimized for FPGA Implementation
Wei Li, Member, IEEE, Luc-André Grégoire, Student Member, IEEE, and Jean Bélanger, Member, IEEE
Abstract—To generate numerous gating signals at a fast
rate, industry controllers of modular multilevel converter
(MMC) usually implement the pulse generation function in
field-programmable gate array (FPGA) boards. Many meth-
ods of submodule (SM) capacitor voltage balance control
(VBC) require knowing the gating signals and are therefore
also implemented in the same FPGA. As the number of
SMs in an MMC increases, both the latency and required
resources for the implementation could become too large
to meet the control requirements or fit into the FPGA.
Conventional methods impose a limitation on the design
of large MMC. This paper presents a pulse generation and
VBC method that is optimized for FPGA implementation.
With least comparison operation, this method produces the
same valve voltage as other modulation methods, and it
removes the need for a sorting operation in VBC, which is
the main difficulty in FPGA implementation. The proposed
method is implemented in the FPGA-based RT-LAB real-
time simulator and tested in a hardware-in-the-loop setup.
The performance of this method is validated in various
tests.
Index Terms—Field-programmable gate array (FPGA),
modular multilevel converter (MMC), power system simu-
lation, real-time systems.
I. I NTRODUCTION
M ODULAR multilever converters (MMCs) are gaining
popularity in high-voltage direct current (HVDC) appli-
cations. Currently, two multiterminal MMC HVDC projects are
being built in Nan’ao and Zhoushan, China. As MMC has many
advantages, including low ac harmonic contents, low switching
loss, fast fault recovery, and high reliability, it also presents
many challenges [1]–[6]. One of them is the implementation
of the pulse generation and capacitor voltage balance control
(VBC) due to the enormous number of submodules (SMs) in
one MMC.
Different gating signal generation techniques are proposed
in the literature for MMC control. Space vector modulation
schemes are used in [7]–[9] for MMC with a low number
of voltage levels. Multicarrier pulsewidth modulation (PWM)
Manuscript received February 13, 2014; revised May 22, 2014,
July 22, 2014, and September 8, 2014; accepted September 17,
2014. Date of publication October 14, 2014; date of current version
April 8, 2015.
The authors are with Opal-RT Technologies, Montréal, QC H3K 1G6,
Canada (e-mail: wei.li@opal-rt.com; luc-andre.gregoire@opal-rt.com;
jean.belanger@opal-rt.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2014.2362879
0278-0046 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
schemes become more applicable as the MMC voltage level in-
creases and, thus, are more commonly proposed in the literature
[10]–[22]. Particularly, the phase-shifted multicarrier PWM is
used in [11]–[17], and the level-shifted multicarrier PWM is
used in [19]–[23]. A comparison and evaluation of the two
categories of PWM is given in [24] and [25]. A PWM scheme
using the moving-average concept is introduced and used in
[26]–[29].
Mainly two capacitor VBC approaches, namely, the individ-
ual control loop approach and the pulse reassignment approach,
are proposed in the literature. In the first approach, capacitor
voltage control loops are added for each SM, and therefore, all
references for pulse generation are different, [10]–[14], [30],
[31]. By using two loops, capacitor voltage balancing among
valves and inside each valve can be achieved. Since the ref-
erence combines the components from different control loops,
tuning the control parameters, which is system dependent,
becomes important but difficult [11]. A large weight of the VBC
signal in the reference could affect other control loops, whereas
a small weight could lead to a slow response.
For the second approach, there is no capacitor voltage control
loop. The voltage reference is the same for all SMs in one
valve. The generated pulses are reassigned to SMs according
to the sorting results of the capacitor voltage and valve cur-
rent direction [8], [15]–[22], [25]–[28], [32]. This approach,
which is effective for balancing inside each valve, is decoupled
from other control loops and does not require tuning control
parameters. It usually has faster response compared with the
individual control loop approach. As this approach is applied
after pulse generation, both the pulse generation and VBC
are usually implemented in the field-programmable gate array
(FPGA) [7], [21], [22], [27], [28]. The difficulty is in the FPGA
implementation since the conventional methods need to sort
the capacitor voltages in ascending or descending order and
reassign the pulses according to the sorting result.
This paper discusses the practical difficulties in implement-
ing the pulse generation and VBC, particularly for MMC with
a large number of SMs. A method optimized for FPGA imple-
mentation is then presented.
II. P ULSE G ENERATION
The MMC topology with a half-bridge SM is given in Fig. 1.
When the capacitor voltages are well controlled to the nominal
value, i.e., Vcap·nom , the valve output voltage, i.e., VMMC , is
expressed as
VMMC = Σ(Ni ∗ Vcap·i ) = Vcap·nom ΣNi (1)
2860 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 5, MAY 2015

Fig. 3. Reindexed carriers and reference for the phase-shifted PWM

method.

Fig. 1. Schematic of MMC and SM.

Fig. 2. Multiple carriers and reference for the phase-shifted PWM Fig. 4. Schematic diagram to achieve the pulse summation NΣ .
method.

where Ni is the gating pulse, Vcap·i is the capacitor voltage,

and subscript i denotes that the value is for the ith SM.
The MMC performance, including its harmonic contents, is
only determined by the pulse summation or the number of
ON -state SM. The selection of the ON -state SM will not affect
the results.
The principle of the proposed pulse generation method is Fig. 5. NΣ is the sum of (a) the reference integer part, and
(b) comparison result between the reference factional part (red) and a
to generate the exact same number of ON-state SMs as other reindexed carrier (black).
modulation methods but with minimal operation. Thus, it is op-

timized for FPGA implementation without any negative impact as the new ith carrier, which is marked as Scar·i (see Fig. 3).

on the MMC performance or harmonic contents. The selection Scar·i takes a value in the range [i − 1, i]. Thus, (2) becomes
of the ON-state SM is made at a later VBC stage.

M
A typical multicarrier phase-shifted PWM is illustrated in 
NΣ = U (Sref , Scar·i )
Fig. 2. The number of triangle carriers is the same as the SM i=1
number in one MMC valve, which is denoted as M . The carriers 
SN  
 
are evenly interleaved, i.e., a 2π/M phase shift between every = U (Sref , Scar·i ) + U Sref , Scar·(SN +1)
two consecutive carriers. The magnitude of all carriers and the i=1
reference are multiplied by M times for easier demonstration. 
M

For each SM, the pulse is determined by comparison between + U (Sref , Scar·i )
the reference and the carrier. The summation, i.e., NΣ , is 
i=SN +2 

given as = SN + U Sref − SN, Scar·(SN +1) − SN (3)

where SN is the integer part of Sref .

NΣ = ΣNi = ΣU (Sref , Scar·i ) (2)
where Sref is the reference, Scar·i is the carrier, and U (x, y) is
the comparison operator, which gives one if the first parameter
x is greater than the second parameter y, or 0 otherwise.
The carriers take the range of [0 M ] on the y-axis, which
can be evenly divided into M number of contiguous bands.
The ith band is between (i − 1) and i on the y-axis, where
i is 1, 2, . . . , M . The carriers cross each other simultaneously
(2 ∗ M ) times per carrier period. The crossing points are all at
the band boundaries. At any time, each band contains only one
carrier.
Since all SMs are not differentiated at this stage, the carriers
can be reindexed without affecting the value of NΣ . At any
time, the carrier currently in the ith band is dynamically indexed
The term (Sref − SN ) represents the fractional parts of Sref ,

which is identified as SR. The waveform of (Scar·(SN +1) −

SN ), which is identified as Scar , is either the same as or the

reverse of Scar1 , depending on if SN is even or odd. Therefore,
the pulse summation, rewritten as

NΣ = SN + U (SR, Scar ) (4)
can be achieved by adding the integer part of the reference with
the comparison result of the fractional part of the reference with
a new carrier, which has a frequency M times of the original
multicarriers. The carrier flips when the integer part of the ref-
erence is an even number. Fig. 4 gives the schematic diagram,
and Fig. 5 gives the new reference and carrier waveforms for
the same case in Fig. 2.
LI et al.: MMC PULSE GENERATION AND CAPACITOR VOLTAGE BALANCE METHOD
Fig. 6. Carriers of level-shifted PWM for (a) the phase disposition
method, (b) the phase-opposition disposition method, and (c) the
alternative-phase-opposition disposition method.
This method can be easily adapted to other modulation meth-
ods. Three typical multicarrier level-shifted PWM methods
are illustrated in Fig. 6. Using the same principle, the pulse
 FPGA resources.
summation can also be achieved by (4), where Scar has the
same frequency as the original level-shifted multicarrier. The
 MMC applications, but the complexity order remains similar.
Scar waveforms for the phase-shifted and the three level-shifted
PWM methods are slightly different, but can be generated by
the same code in the FPGA.
When the number of SMs in a valve increases to a large
number, e.g., 200, the harmonic becomes less of a concern.
Some industry controllers use nearest level control (NLC)
modulation to reduce the switching loss. This method can also
 in the FPGA. The design of the SM number in an MMC is
be adapted to the NLC modulation. By setting Scar in (4) to the
constant of 1, or 0.5, 0, the resulting NΣ gives the floor integer,
rounded integer, or ceiling integer of the reference, respectively.
Therefore, the proposed method can produce the same valve
voltage as other modulation methods, e.g., phase-shifted PWM,
level-shifted PWM, or NLC, without recompilation of the
FPGA program. The user can check the impact of different
methods and carrier frequencies on the system harmonics on-
the-fly.
More important, this method requires the comparison op-
eration only once, regardless of the SM numbers. Compared
with the conventional multicarrier PWM methods, which need
M carriers for M times the comparison operation, it takes
minimum fixed FPGA resources regardless of the MMC size.
III. C APACITOR VOLTAGE B ALANCE
A. Difficulties of Implementing Sorting Algorithm in FPGA
To balance the capacitor voltage, the conventional pulse
reassignment approaches need to sort the capacitor voltage.
In practice, the bubble sort algorithm is often used due to its
simplicity to program in FPGA. For real-time applications,
the algorithm performance in the worst case is considered.
To sort M SMs, the bubble sort needs (M − 1) number of
passes. In the nth pass, (M − n) number of steps consecutively
compare, and swap if necessary, a pair of adjacent voltages.
This algorithm requires a total of 0.5M (M − 1) steps and has
complexity of O(M 2 ), where the big O notation describes
limiting behaviors of a function, and in this case, the complexity
is asymptotically equivalent to M 2 when M tends toward
infinite.
The bubble sort implementation in FPGA can be in series,
e.g., with one function of the compare-and-swap step being
called for 0.5M (M − 1) times, or in partial parallel, e.g.,
with multiple functions being called for fewer times. Each call
2861
of the function will take one FPGA clock. Hence, the series
implementation will take at least 0.5M (M − 1) FPGA clocks.
In a partial-parallel implementation of (M − 1) functions, each
function works for one pass, and the function for the first pass
is called for the most times, i.e., (M − 1) times. Thus, it takes
minimum (M − 1) FPGA clocks. Compared with the series
implementation, the partial-parallel implementation is faster.
However, for a large M , it is still too slow as required by control
and takes too much FPGA resources for the large number of
functions.
Moreover, once the capacitor voltages are sorted, the pulses
have to be reassigned according to the sorting results. This has
to be done individually, which could also take considerable
Improvements on the bubble sort algorithm are proposed for
There exist other sorting algorithms with better worst-case
complexity of O(M log M ).
Due to its nature, the FGPA resources and latency of sorting
algorithm dramatically increase as M increases. The VBC
could become too slow to meet the upper level control require-
ments, or the implementation is too large to be accommodated
limited by the VBC using the sorting method.
B. Flowchart of Proposed Max/Min Method
Without sorting operation, the proposed VBC method only
needs to find the SM of the maximum or minimum capacitor
voltage. The actual number of ON-state SMs, i.e., NΣact , is
calculated and compared with its reference, i.e., NΣref , in each
FPGA cycle, the simulation time step in the FPGA. Depending
on the result and the current direction (the charging direction
is defined as positive), this method changes, if necessary, only
one SM’s state according to the following rules.
• If NΣact < NΣref and positive current, turn on the
OFF-state SM of the minimum capacitor voltage.
• If NΣact < NΣref and nonpositive current, turn on the
OFF-state SM of the maximum capacitor voltage.
• If NΣact > NΣref and positive current, turn off the
ON -state SM of the maximum capacitor voltage.
• If NΣact > NΣref and nonpositive current, turn off the
ON -state SM of the minimum capacitor voltage.
• If NΣact = NΣref , no switching.
The flowchart for the proposed method is given in Fig. 7.
There are seven steps in each FPGA cycle. Step 1 reads the
pulse summation generated in Fig. 4 as the reference number
of ON-state SM. Step 2 initializes the SM states if it is the
first cycle since the MMC pulse is enabled. As all capaci-
tors are charged to a similar voltage in the diode mode, the
first NΣref number of SMs are set to ON-state and others to
OFF-state. In Step 3, the actual number of ON -state SMs is
calculated and compared with the reference value. Steps 4–7
take action according to the rules explained above.
In Step 5, Cmax and zero are the maximum and minimum
possible capacitor voltages. Since this method searches only the
maximum or minimum capacitor voltage of SM with a specific
state, this step is to exclude the SM of the opposite state from
2862
Fig. 7. Flowchart of proposed capacitor voltage balance method.
being selected. For example, to select a previous OFF-state SM
of the minimum voltage, the voltages of all previous ON-state
SMs are set to the value of Cmax. Note in Steps 5 and 6 that the
logic in different paths is similar and can be implemented using
the same function to save FPGA resources.
C. Complexity and Latency of Proposed Method
To find the maximum or minimum among M values, (M −
1) number of comparison operations are required, which has
complexity of O(M ), which is a lower order than the complex-
ity of sorting operations.
The implementation in FPGA can be in series, parallel,
or partial parallel. The series implementation has only one
function being called for (M − 1) time. The parallel implemen-
tation requires f loor(M/2) number of functions and maximum
ceiling(log2 (M )) number of call for one function, where
f loor(x) and ceiling(x) give the floor and ceiling integers of
x. In the partial-parallel implementation, the M voltages are
divided into K groups. Each group is treated in series, and
the K finalists of each group are treated in parallel. It requires
(M/K − 1 + ceiling(log2 (K))) number of FPGA clocks and
(K + f loor(K/2)) number of functions.
The series implementation takes longer time, and the paral-
lel implementation takes more FPGA resources. The partial-
parallel implementation provides a good combination of speed
and resources, which can be adjusted by changing the value K.
For example, when a valve has 1024 SMs, the required FPGA
resources and latency for the implementation of the bubble
sorting and the proposed method are summarized in Table I.
Even taking enormous FPGA resources (1023 functions), the
bubble sorting in partial-parallel implementation takes more
than 10 μs (for a 10-ns FPGA clock), which might not meet the
controller’s requirements. The proposed method (with K = 32)
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 5, MAY 2015
TABLE I
FPGA R ESOURCES AND L ATENCY FOR D IFFERENT M ETHODS
approximately takes 21 times less resource and is 28 times
faster (in less than half μs).
D. Features of Proposed Method
When a big disturbance occurs to the system, the valve volt-
age has to rapidly change according to its reference in order to
recover the system fast. That means the derivative of the valve
voltage has to be large. This method can change the number of
ON -state SMs by one at each FPGA cycle as in Fig. 7, which
is smaller than the switch signal sampling time. For example,
if the sampling time is 10 μs and the FPGA cycle is 500 ns, a
maximum 20 (= 10 μs/500 ns) SMs of the specific state with
the first 20 maximum or minimum capacitor voltages could
change their states at each 10 μs sampling period. Therefore,
this method can achieve a very high valve voltage derivative.
The per-unitized maximum absolute value is given as
 
d  |ΔNΣ |max /M 1/M
 VMMCpu  = = (5)
 dt  Δt T FPGAcycle
max
which is 1000 pu/s for an MMC with 2000 SMs per valve, and
the FPGA cycle, i.e., TFPGAcycle , being 500 ns. For a typical
application with less SM number and equal or smaller FPGA
cycle, the maximum derivative is even larger than 1000 pu/s,
much higher than a control design may require. Therefore, by
changing only one SM’s state at each FPGA cycle, this method
will not decrease the system performance or slow down the
system recovery at big disturbances.
In a phase-shift modulation method with M SMs and carrier
frequency of fcar , each SM has a switching frequency of
fcar and switches twice (one for switching-on and another for
switching-off) in each carrier signal period. The total switching
number is 2M in one valve. As in Fig. 3, the proposed method
only reindexes the carriers without modifying their pattern, the
total switching number in a valve is not changed, 2M in each
period in this case. Although in one period, each individual SM
might switch more or less times, the average switching number
and, thus, the average switching frequency, is the same as in
the original modulation method. For the level-shifted or NLC
modulation method, the adapted method has the same average
switching frequency as the original method.
For multicarrier modulation methods, a reference may cross
an interaction point of two carriers, which means one SM
switches to ON-state and the other switches to OFF-state at
the same instant. For those rare occasions, the total number of
ON -state SMs does not change, and thus, the proposed method
has less total switching number than the original methods. An
LI et al.: MMC PULSE GENERATION AND CAPACITOR VOLTAGE BALANCE METHOD
Fig. 8. Front and back views of the RT-LAB simulator-based HIL test
bench.
Fig. 9. Schematic of the MMC ac–dc–ad system.
optional watchdog can be added as in Step 4 in Fig. 7, to force
one switching if a no-switching period lasts too long, which
only occurs in abnormal conditions such as a constant voltage
reference.
The gating signals are sent from the controller to MMC
devices through fiber optic or copper wires. Note that the
sampling time in the I/O may not be same as the FPGA
cycle. The I/O sampling time is in a few μs to tens of μs
in industrial controllers. Having a much smaller FPGA cycle,
e.g., 500 ns, the same implementation of this method can be
used for different I/O sampling times with minimum aliasing
effect of two sampling time systems. Inside the FPGA, the
synchronization requirement between the pulse generation part
and the I/O driver becomes trivial.
IV. T EST B ENCH S ETUP AND S TUDY S YSTEM
A hardware-in-the-loop (HIL) test bench, based on the
RT-LAB real-time simulation platform, is set up to validate
the proposed method (see Fig. 8). The test system is a two-
terminal MMC HVDC system (see Fig. 9). One MMC terminal
is controlled by an external controller, whereas the other has an
internal controller simulated in the same simulator. The system
parameters of the external controller side are given in Table II.
The SM capacitance is selected to store typically 1.5 cycle of
the energy for HVDC applications.
The external controller is simulated in a second independent
real-time simulator. The MMC valve control, using the pro-
posed pulse generation and VBC method, is implemented in
a Virtex-7 FPGA board with a cycle of 500 ns. The MMC pole
control, explained in [33], is implemented in the CPU with a
sampling rate of 25 μs.
2863
TABLE II
S YSTEM PARAMETER ON THE E XTERNAL C ONTROLLER S IDE
The system measurements, including the ac-side voltages
and currents, dc-link voltages, and valve currents, are sent
from the plant to the controller through copper wires (the
white cables in the back view). They have to be calibrated
to minimize the error and noise introduced in the analog and
digital conversion and in the cables.
The MMC measurements and commands are transferred
through optical fibers. Each pair of fibers is used for one valve,
and thus, six fibers are used for one station (the orange cables
in the front view). For the controller, an outgoing message
includes one valve current and 250 capacitor voltages, and an
incoming message includes 250 MMC commands. No calibra-
tion is required since all signals are transferred in digital format.
The update rates of the outgoing and incoming messages can be
individually adjusted during real-time simulation to study their
impacts on the system performance.
V. C ASE S TUDY AND R ESULTS
A. Performances at System Transient
Fig. 10 provides the MMC waveforms at the system transient
when the reactive power references changes from 0.5 to −0.5 pu
and the active power reference keeps 0. The control has a rate
limiter; hence, the reference ramps to its final value in five cy-
cles for a smooth transient. The frequency carrier is at 300 Hz,
i.e., six times the system frequency. The MMC measurements
and commands are updated every 20 and 2 μs, respectively.
Note that the MMC terminal voltage, terminal current,
and valve currents are highly sinusoidal and well controlled.
Fig. 10(e) gives the individual capacitor voltages of the first
three SMs and the upper and lower boundaries of all capacitor
voltages in one valve. All capacitor voltages are controlled in a
very narrow band within the boundaries and, therefore, are well
balanced.
In the plant simulator, the power grid is simulated in CPU
with a time step of 25 μs, and the MMC is simulated in the
FPGA with at a time step of 500 ns. Therefore, those system
measurements in Fig. 10(a)–(d) have a resolution of 25 μs.
Every 25 μs, a group of 32 capacitor voltages is sent from the
FPGA to the CPU for data logging purposes only. Therefore,
the voltages in Fig. 10(e) have a resolution of 1.5 ms and
might not be simultaneously sampled. The upper and lower
boundaries are calculated by the logged data and, thus, have
a small error due to the consecutive logging manner. The actual
difference between the boundaries should be smaller than the
calculated value.
2864
Fig. 10. Waveforms at a system transient. (a) MMC ac voltages, (b) ac
currents, (c) ac-side active and reactive power, (d) valve currents, and
(e) capacitor voltages of three SMs and the upper and lower boundaries
of one valve.
B. Impact of Carrier Frequency and Signal Rate
The carrier frequency has a significant impact on the VBC
performance. Fig. 11 gives the capacitor voltages and their
boundaries when the carrier frequency is 50 Hz, the active
and reactive power references are 0 and −0.5 pu, respectively.
The other parameters are the same as the previous test. The
voltages vary in a larger band between the upper and lower
boundaries compared with that in Fig. 10. For the two carrier
frequencies, the bandwidth, i.e., the upper boundary minus the
lower boundary, is given in Fig. 12. The time-averaged values
at different carrier frequencies are given in Table III. Note that
increasing the carrier frequency will have a better balance on
the capacitor voltage because each SM switches more often.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 5, MAY 2015
Fig. 11. System waveforms as the carrier frequency is 50 Hz. (a) MMC
valve currents. (b) Capacitor voltages of three SMs and the upper and
lower boundaries of one valve.
Fig. 12. Width of capacitor voltage band when the carrier frequency is
50 Hz (red) and 300 Hz (blue).
TABLE III
W IDTH OF VOLTAGE BAND AT D IFFERENT C ARRIER F REQUENCIES
TABLE IV
AVERAGE W IDTH OF VOLTAGE BAND AT D IFFERENT
S IGNAL C OMMUNICATION R ATES
At a certain carrier frequency, e.g., 200 Hz, it achieved a
good performance. Further increasing the carrier frequency will
improve the performance but slowly.
The effect of the MMC measurements and commands update
rates on the VBC performance is studied and summarized in
Table IV. The results are achieved when the carrier frequency
is 200 Hz, the active and reactive power references are 0 and
−0.5 pu, respectively. It is observed that the signal update rating
between the MMC and its controller has little effect on the
performance.
C. Performances at Single SM Short-Circuit Fault
Normally, the short circuit of a capacitor could cause per-
manent damage of the device, and the faulty SM has to be by-
passed. In this paper, the hypothetical temporary short circuit,
LI et al.: MMC PULSE GENERATION AND CAPACITOR VOLTAGE BALANCE METHOD
Fig. 13. Waveforms at single fault on SM 1. (a) MMC ac voltages,
(b) ac currents, (c) valve currents, and (d) capacitor voltage of SM1,
SM2, SM3, and voltage boundaries of one valve.
Fig. 14. Capacitor voltage of the fault SM at different power conditions.
where the device recovers after the fault is cleared, is used
to examine the effectiveness of the proposed VBC method in
an extreme condition where the capacitor voltage of some SM
deviates far away from others.
The capacitor voltage in the fault SM is completely dis-
charged to 0 before the fault is cleared in 25 μs. In all the
following fault tests, the carrier frequency is 200 Hz; the update
rates of the MMC measurements and commands are 100 and
20 μs, respectively. Since this study is focused on voltage
balancing within each valve, same faults are applied to all six
valves to eliminate the effects from other control loops.
Fig. 13 shows the system response to a temporary fault at
SM 1 when the active and reactive power is 0.5 pu and 0, re-
spectively. The complete discharge of one SM has a negligible
impact on the ac voltages, ac currents, and valve currents. The
SM 1 capacitor voltage, coincident with the lower boundary as
2865
TABLE V
S INGLE FAULT R ECOVERY T IMES AT D IFFERENT P OWER C ONDITIONS
Fig. 15. Waveforms at simultaneous fault on SM1, SM2, and SM3.
(a) MMC ac voltages, (b) ac currents, (c) valve currents, and (d) capacitor
voltage of SM1, SM2, SM3, and the voltage boundaries of one valve.
in Fig. 13(d), recovers fast after the fault. The recovery time,
i.e., the interval between the fault clearance and the instant
that the width of the voltage band reduces to less than 5%, is
49.8 ms, less than three cycles.
In each cycle, the valve current changes its direction twice.
At recovery, the fault SM is switched on at the beginning of
the charging half cycle to increase its capacitor voltage and
is switched off at the beginning of the discharge half cycle to
maintain it voltage. Depending on the fault point on the valve
current waveform, the recovery time may vary for a half cycle,
i.e., 10 ms.
The capacitor voltage charging rate is determined by the
valve current magnitude, which is proportional to the appar-
ent power in the steady state. The capacitor voltages of the
fault SM at different power conditions are given in Fig. 14,
and the recovery times are given in Table V. Generally
speaking, the larger the apparent power is, the faster the fault
SM recovers.
D. Performances at Multiply SM Short-Circuit Fault
Multifault scenarios are studied where simultaneous short-
circuit faults are applied to multiple SMs and cleared after
25 μs. Fig. 15 shows the system response when the SM 1, 2,
2866
Fig. 16. Lower capacitor voltage boundary for cases of multiple SM
faults.
TABLE VI
R ECOVERY T IMES AT M ULTIFAULT C ONDITIONS
and 3 have the faults. In this and following tests, the active and
reactive power values are 0.5 pu and 0, respectively.
Note that the valve current has some disturbance. The three
fault SMs recovers at the same rate as their capacitor voltages are
coincident with the lower voltage boundary. Fig. 16 shows the
lower voltage boundary for cases with the number of the fault
SMs being 1, 2, 3, . . . , 8. The recovery time is given in Table VI.
Although the proposed capacitor VBC method changes only
the state of one SM at each FPGA cycle, it can actually balance
multiple SMs whose voltages deviate far from the average.
From Table VI, when the number of those SMs increases, the
performance of this method remains the same in terms of the
recovery time.
VI. C ONCLUSION
This paper has presented an MMC pulse generation and
capacitor VBC optimized for the FPGA implementation. It is
implemented in an FPGA-based real-time simulator and vali-
dated in an HIL test bench. Its performances in steady states,
transients, and fault conditions are investigated and presented
in terms of the capacitor voltage band and recovery time. The
effects of different system parameters, such as carrier frequency
or signal communication update rates, on the performance are
also studied.
The advantages of the proposed method are summarized
below.
• It significantly reduces the computational complexity and
makes it possible to work for MMC with an extremely
large number of SMs. Compared with conventional meth-
ods, its implementation in FPGA has very short latency
and takes much fewer resources.
• It makes fast updates, in a few μs or even sub-μs, of gating
signal possible.
• The implementation is easy to expand as the SM number
increases. Moreover, the required FPGA resources and
latency can be adjusted to achieve a suitable design.
• It achieves good performance at a low switching fre-
quency, which means less switching losses.
• It is applicable to different modulation methods, such as
multicarrier phase-shifted or level-shifted PWM or NLC
methods.
• It is easy to connect to I/O drivers at different sampling
times.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 5, MAY 2015
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Wei Li (M’06) was born in Hangzhou, China.
He received the B.Eng. degree from Zhejiang
University, Hangzhou, in 1996, the M.Eng. de-
gree from the National University of Singapore,
Singapore, in 2003, and the Ph.D. degree
from McGill University, Montréal, QC, Canada,
in 2010.
Since 2007, he has been a Power System
Simulation Specialist with Opal-RT Technolo-
gies, Montréal. His fields of interest are in power
electronics, renewable energy, and distributed
generation. His current research mainly focuses on real-time simulation
and controls of modular multilevel converter high-voltage direct-current
systems and flexible alternating-current transmission system devices.
2867
Luc-André Grégoire (S’08) received the B.Ing.
and M.Ing. degrees in 2008 and 2010, respec-
tively, from the École de Technologie Supérieure
(ETS), Montreal, QC, Canada, where he has
been working toward the Ph.D. degree with
the Groupe de Recherche en Électronique de
Puissance et Commande Industrielle (GREPCI-
ETS) under the supervision of Prof. Kamla
Al-Haddad and Prof. Handy Fortin Blanchette
since September 2012.
He was with OPAL-RT Technologies as a
Real-Time Simulation Specialist. His main fields of interest are power
converters, real-time simulations, and modular multilevel converters.
Jean Bélanger (M’87) received the Bachelor’s
degree in electrical engineering from Laval Uni-
versity, Québec City, QC, Canada, in 1971 and
the Master’s degree from the École Polytech-
nique de Montréal, Montréal, QC.
He has been with Hydro-Quebec’s System
Planning Division and with the IREQ, where he
was involved in the design and installation of
Hydro-Quebec real-time simulators. He was no-
tably involved in the design of the 765-kV James
Bay transmission system, with such tasks as
insulation and coordination of equipment and the installation of trans-
mission lines, as well as the installation of static VAR compensators
and series capacitors. He is the Cofounder, Chief Executive Officer, and
Chief Technology Officer of Opal-RT Technologies, Montréal. Founded
in 1997, Opal-RT develops and commercializes digital real-time sim-
ulators for system design and electronic controller testing. Under his
direction and technological leadership, Opal-RT has become a well-
known developer of multidomain real-time simulators used in more than
40 countries around the world in the aerospace, automotive, and power
systems industries.