Problems in VLSI design

• wire and transistor sizing

– signal delay in RC circuits
– transistor and wire sizing
– Elmore delay minimization via GP
– dominant time constant minimization via SDP

• placement problems
– quadratic and ℓ1-placement
– placement with timing constraints

1
 Signal delay in RC circuit

vin
1
vk
vin 0.5

t=0 Dk

dv
C = −G(v(t) − 1), v(0) = 0
dt

• capacitance matrix C = C T ≻ 0

• conductance matrix G = GT ≻ 0

Problems in VLSI design 2

• v: node voltages

• as t → ∞, v(t) → 1

• delay at node k:

Dk = inf{T | vk (t) ≥ 0.5 for t ≥ T }

• critical delay: D = maxk Dk

Problems in VLSI design 3

 Transistor sizing

RC model of transistor Rsd ∝ 1/w

G S D

Cg ∝ w Cs ∝ w Cd ∝ w
drain

gate RC model (on)

source G S D

nMOS Cg ∝ w Cs ∝ w Cd ∝ w
transistor
(width w)
RC model (off)

Problems in VLSI design 4

example

vout
CL

Problems in VLSI design 5

• to first approximation: linear RC circuit

• design variable: transistor width w

• drain, source, gate capacitance affine in width

• ‘on’ resistance inversely proportional to width

Problems in VLSI design 6

 Wire sizing
interconnect wires in IC: distributed RC line
lumped RC model: ℓ
i
wi

Ri ∝ ℓi/wi

Ci ∝ w i ℓi Ci

• replace each segment with π model

• segment capacitance proportional to width

Problems in VLSI design 7

• segment resistance inversely proportional to width

• design variables: wire segment widths wi

Problems in VLSI design 8

 Optimization problems involving delay

dv
C(x) = −G(x)(v(t) − 1), v(0) = 0
dt

• design parameters x: transistor & wire segment widths

• capacitances, conductances are affine in x:

C(x) = C0 + x1C1 + · · · + xmCm

G(x) = G0 + x1G1 + · · · + xmGm

Problems in VLSI design 9

tradeoff between
• delay, complicated function of x

• area, affine in x

• dissipated power in transition v(t) = 0 → 1

1T C(x)1
2

affine in x

Problems in VLSI design 10

 Elmore delay

• area above step response

Z ∞
Tkelm = (1 − vk (t))dt
0

• first moment of impulse response

Z ∞
Tkelm = tvk (t)′dt
0

Problems in VLSI design 11

eplacements
Tkelm vk′
vk
1

0.5

Dk Dk Tkelm

• Tkelm ≥ 0.5Dk

• good approximation of Dk only when vk is monotonically increasing

• interpret vk′ as probability density:

Tk is mean, Dk is median

Problems in VLSI design 12

 Elmore delay for RC tree
RC tree R2 R3
2m
r
3m
r

C2 C3
R1
1
r m
R5
5m
r
vin R4
4
r m C6
R6
6m
C1 r

C4 C5

• one input voltage source

• resistors form a tree with root at voltage source
• all capacitors are grounded

Problems in VLSI design 13

Elmore delay to node k:
X X 
Ci R’s upstream from node k and node i
i

R2 2m R3 3m
r r

R1 C2 C3
1
r m
R5 5m
r
vin R4
4 R6
r m C5
6m
C1 r

C4 C6

Example:

T3elm = C3(R1 + R2 + R3) + C2(R1 + R2) + C1R1

+ C4R1 + C5R1 + C6R1

Problems in VLSI design 14

 Elmore delay optimization via GP
in transistor & wire sizing, Ri = αi/xi, Cj = aTj x + bj
(αi ≥ 0, aj , bj ≥ 0)

Elmore delay:

m
α
X X Y
Tkelm = γij Rj Ci = βk xi ik
ij k=1 i=1

(γij = +1 or 0, βk ≥ 0, αij = +1, 0, −1)

. . . a posynomial function of x ≻ 0

hence can minimize area or power, subject to bound on Elmore delay using
geometric programming

commercial software (1980s): e.g., TILOS

Problems in VLSI design 15

 Limitations of Elmore delay optimization

• not a good approximation of 50% delay when step response is not

monotonic
(capacitive coupling between nodes, or non-diagonal C)

• no useful convexity properties when

– there are loops of resistors
– circuit has multiple sources
– resistances depend on more than one variable

Problems in VLSI design 16

 Dominant time constant

dv
C(x) = −G(x)(v(t) − 1), v(0) = 0
dt

• eigenvalues 0 > λ1 ≥ λ2 ≥ · · · ≥ λn given by

det(λiC(x) + G(x)) = 0

• solutions have form X

vk (t) = 1 − αik eλit
i

• slowest (“dominant”) time constant given by T dom = −1/λ1 (related to

delay)

Problems in VLSI design 17

 −1/T dom

• can bound D, T elm in terms of T dom

• in practice, T dom is good approximation of D

Problems in VLSI design 18

 Dominant time constant constraint as linear matrix
inequality

upper bound T dom ≤ Tmax

−1/T dom

−1/Tmax

T dom ≤ Tmax ⇐⇒ TmaxG(x) − C(x)  0

• convex constraint in x (linear matrix inequality)

Problems in VLSI design 19

• no restrictions on G, C

• T dom is quasiconvex function of x, i.e., sublevel sets

dom

x|T (x) ≤ Tmax

are convex

Problems in VLSI design 20

 Sizing via semidefinite programming

minimize area, power s.t. bound on T dom, upper and lower bounds on sizes

minimize fTx
subject to TmaxG(x) − C(x)  0
xmin
i ≤ xi ≤ xmax
i

• a convex optimization problem (SDP)

• no restrictions on topology
(loops of resistors, non-grounded capacitors)

Problems in VLSI design 21

 Wire sizing

minimize wire area subject to

• bound on delay (dominant time constant)

• bounds on segments widths

RC-model: xi

x1 x20

αxi
βxi βxi

Problems in VLSI design 22

as SDP: X
minimize ℓixi
i
subject to TmaxG(x) − C(x)  0
0 ≤ xi ≤ 1

Problems in VLSI design 23

area-delay tradeoff

2000
1
1800 HH
Y
1600
H
(d) 0.5

0
1400
1
Tdom

1200
0.5
1000
(c) 0
800 A
A (b) (a) 0.6

600 U
A A A
0.3
A A
0
400 AU AU 0.2
0
200 0 2 4 6 8 10 12 14 16 18 20
2 4 6 8 10 12 14 16 18

wire area
• globally optimal tradeoff curve

• optimal wire profile tapers off

Problems in VLSI design 24

step responses (solution (a))

0.9

0.8

0.7

voltage 0.6

0.5

0.4

0.3
D dom
0.2
T elm



0.1

T
0 

0 200 400 600 800 1000 1200 1400 1600 1800 2000

time

Problems in VLSI design 25

 Wire sizing and topology
x3 xi

x1 x2
1m 2m 3m

x5 αxi
βixi βixi

x6 4m
x4
not solvable via Elmore delay minimization
min area s.t. max dominant time constant (via SDP):

X
minimize xi
subject to TmaxG(x) − C(x)  0

Problems in VLSI design 26

tradeoff curve
800

700

(c)
600
dominant time constant

500

(b)
400

300

(a)
200

100
0 0.1 0.2 0.3 0.4 0.5 0.6
area

• usually have more wires than are needed

Problems in VLSI design 27

• solutions usually have some xi = 0

• different points on tradeoff curve have different topologies

Problems in VLSI design 28

solution (a) v1(t)
1
 v4(t)
I
@
@
0.9 v3(t)
0.8

0.7

1m 3m 0.6

0.5

0.4

0.3

x4 = 0.15 x6 = 0.11 0.2

T dom
0.1 D
T elm
4m 0
@
R
@




0 100 200 300 400 500 600 700 800 900 1000

Problems in VLSI design 29

solution (b) v1(t)
1

 v4(t)
x3 = 0.02 0.9
I
@
@ v3(t)
0.8

0.7

0.6
1m 3m 0.5

0.4

0.3

x4 = 0.03 x6 = 0.03 0.2

T dom
0.1 D
T elm
4m 0
@
R
@




0 100 200 300 400 500 600 700 800 900 1000

Problems in VLSI design 30

solution (c)
1 v1(t)

x3 = 0.014 0.9

0.8
@
I
@
0.7 v3(t)
0.6

1m 3m 0.5

0.4

0.3

4j 0.2
T dom
0.1 D
T elm
@

0 R
@

0 100 200 300 400 500 600 700 800 900 1000

Problems in VLSI design 31

 Placement

• list of cells: cells i = 1, . . . , N are placeable, cells

i = N + 1, . . . , N + M are fixed (e.g., I/O)

• input and output terminals on boundary of cells

• group of terminals connected together is called a net

Problems in VLSI design 32

Problems in VLSI design 33
• placement of cells determines length of interconnect wires, hence signal
delay

• problem: determine positions (xk , yk ) for the placeable cells to satisfy

delay constraints

• practical problem sizes can involve 100,000s of cells

• exact solution (including delay, area, overlap constraints) is very hard to

compute

• heuristics (often based on convex optimization) are widely used in

practice

Problems in VLSI design 34

 Quadratic placement

assume for simplicity:

• cells are points (i.e., have zero area)

• nets connect two terminals (i.e., are simple wires)

quadratic placement:
X
2 2


minimize wij (xi − xj ) + (yi − yj )
nets (i,j)

weights wij ≥ 0
unconstrained convex quadratic minimization
(called ‘quadratic programming’ in VLSI)

Problems in VLSI design 35

• solved using CG (and related methods) exploiting problem structure
(e.g., sparsity)

• physical interpretation: wires are linear elastic springs

• widely used in industry

• constraints handled using heuristics

(e.g., adjusting weights)

Problems in VLSI design 36

 ℓ1-placement

X
minimize wij (|xi − xj | + |yi − yj |)
nets (i,j)

• measures wire length using Manhattan distance

(wire routing is horizontal/vertical)

• motivation: delay of wire (i, j) is RC with

R = Rdriver + Rwire, C = Cwire + Cload

Rdriver, Cload are given, Rwire ≪ Rdriver,

Cwire ∝ wire length (Manhattan)

Problems in VLSI design 37

 Rdriver

Cwire Cload

• called ‘linear objective’ in VLSI

Problems in VLSI design 38

 Nonlinear spring models

X
minimize h(|xi − xj | + |yi − yj |)
nets (i,j)

h convex, increasing on R+
example h(z)

• flat part avoids ‘clustering’ of cells

Problems in VLSI design 39

• quadratic part: for long wires Rwire ∝ length

• solved via convex programming

Problems in VLSI design 40

 Timing constraints

• cell i has a processing delay Diproc

• propagation delay through wire (i, j) is αℓij , where ℓij is the length of
the wire

• minimize max delay from any input to any output

Problems in VLSI design 41

 ℓ14 ℓ45
D4proc
D1proc

ℓ13
ℓ35
D3proc D5proc

D2proc ℓ23

Problems in VLSI design 42

problem is:

minimize T X
proc
X
subject to Di + αℓij ≤ T
cells wires
in path in path

• one constraint for each path

• variables: T , positions of placeable cells (which determine ℓij )

• a very large number of inequalities

Problems in VLSI design 43

 A more compact representation
• introduce new variable Tiout for each cell

• for all cells j, add one inequality for each cell i in the fan-in of j

Tiout + αℓij + Djproc ≤ Tjout (1)

• for all output cells

Tiout ≤ T (2)

• minimize T subject to (??) and (??)

convex optimization problem:
• with ℓ1-norm, get LP

• with ℓ2-norm, get SOCP

Problems in VLSI design 44

extensions (still convex optimization):
• delay is convex, increasing fct of wire length

• max delay constraints on intermediate cells

• different delay constraints on cells

Problems in VLSI design 45

 Non-convex constraints and generalizations

non-convex constraints
• cells are placed on grid of legal positions

• cells are rectangles that cannot overlap

• reserved regions on chip

Problems in VLSI design 46

generalizations
• multi-pin nets: share interconnect wires

• combine placement with wire and gate sizing

Problems in VLSI design 47