White Paper

FinFET Technology – Understanding

and Productizing a New Transistor
A joint whitepaper from TSMC and Synopsys
April, 2013

Authors Introduction
Andy Biddle The mobile and computing markets continue to innovate at a dramatic rate delivering more and more
Galaxy Platform performance in smaller and smaller form factors with higher and higher power efficiencies. One of the
Marketing, keys to enabling this is the semiconductor technology that provides the platform for building the system
Synopsys Inc.
on a chip (SoC) components at the heart of these devices. The underlying transistor technology most
Jason S.T. Chen SoCs are built on today uses the planar MOSFET transistor. This tiny four terminal electronic device has
Design Methodology been used for amplifying and switching electronic signals for many decades and, until now, has been
and Service shrunk successfully to deliver on Moore’s Law – doubling the capacity of integrated circuits approximately
Technical Marketing
every two years. However, the consumer’s insatiable demand for better power, performance silicon real
Manager,
estate and cost has out grown the capabilities of the planar MOSFETs, the type of transistor used for most
TSMC
of the CMOS process nodes until now.

One of the major challenges with scaling planar MOSFETs over recent process technology generations
has been in delivering on the switching speeds in large SoCs at reduced power consumption levels. One
of the key limitations impacting power in planar MOSFETs is the short channel effects and in particular
the “off-state” leakage current which increases the idle power unnecessarily. Power sensitive electronics
in computing and mobile products spend a large amount of their life in the “off state” preserving battery
life and/or minimizing heat-generating power, a requirement that is proving harder to meet with planar
MOSFET-based designs.

The semiconductor industry has been very innovative finding ways to minimize the shortcomings of planar
FETs over recent process generations, while seeking a strong alternative. Finally, a viable solution has
emerged, the FinFET. This evolution of the MOSFET has proven to be the best choice for next generation
processes but brings with it some new challenges for manufacturing and design that require careful
consideration if the benefits with FinFETs can be capitalized on.

To ensure a smooth fast transition to this new technology, TSMC has partnered with EDA leaders
like Synopsys to fully understand the impact of introducing this new transistor, striving to solve the
design complexities introduced by this new three dimensional or 3-D device introducing new modeling
techniques for tools to use while minimizing the impact on existing design flows and methodologies.
 This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with
Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include
comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The
TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.

FinFET Overview
As the name suggests, a FinFET is comprised of fins that form the source and drain portion of the transistor
and provide the path (channel) for current to flow when switched on. The gate, which controls the switching
operation, wraps around the fins to form a 3-D structure. Figure 1 shows simplified depictions of a planar FET a
single fin FinFET and a multiple fin FinFET, respectively. In the planar FET, the single gate provides inadequate
electrostatic control over the channel region, hence leading to large leakage currents between the source and
the drain when the gate is “off.”

In contrast, the channel of a FinFET transistor is formed in a thin vertical fin that is wrapped and controlled by
the gate from three sides. FinFET devices are sometimes referred to as “multi-gate” transistors. In this device
structure, the fin body often needs to be fully depleted even in the sub-threshold region. This results in much
better electrostatic control of the channel and thus better electrical characteristics, such as faster turning on and
off. In practice, the thin fin body is required in order for the wrapped gate to attain good control of the channel.

Gate Gate Gate

Drain
Drain
Oxide
Oxide
Source Source Source

Silicon substrate Silicon substrate Silicon substrate

Figure 1(a): Planar MOSFET Figure 1(b): FinFET Figure 1(c): Multiple fin FinFET

The most important geometric parameters of a FinFET are its height (HFIN), its width or body thickness (Tfin),
and its gate length (L) as shown in Figure 2. The effective electrical width (Weff) of a FinFET is the planar
width/body thickness Tfin plus twice the fin height HFIN.

Drain

Gate length (L) Gate

Gate Width (Weff)

Source
Fin height (H fin )

Fin thickness (tfin )

Figure 2: FinFET Electrical Dimensions

FinFET Technology 2
 The length, height and thickness are closely controlled parameters set by the foundry, if the fin is too thick
many of the benefits would be lost and the device would behave similar to the planar device with limited
control of the gate. However having very thin fins are lithographically challenging to produce.

TSMC is introducing an advanced FinFET solution with its new 16 nm process technology that provides
several advantages over the preceding planar processes – some of these benefits are listed below.

Lower leakage and dynamic power: Very good electrostatic control of the channel is a key benefit
``
of FinFETs. The channel can be “choked off” more easily. FinFETs boast a near-ideal sub-threshold
behavior (associated to leakage), which is nearly impossible to achieve with planar technology (see
Figure 3). Lower dynamic power is achieved with options to reduce the threshold voltage of the
transistor, enabling lower power supplies and overall dynamic power consumption.
Higher integration: The vertical channel orientation of FinFETs deliver more performance per linear
``
width than planar FETs even after the isolation dead-area between the fins is taken into account

Reduce
Drain current, IDS

feature
size Planar FET
FinFET

0.0 0.3 0.6 0.9

Gate voltage, VGS(V)

Figure 3: Off State Leakage Current comparison

In short, the FinFET transistors can operate faster for a given amount of power consumption or run equally fast
as planar but with much less power. This enables IC design teams to balance throughput, performance and
power to match the needs of various applications.

FinFET Challenges
While FinFETs offer many advantages, new challenges arise for foundries and EDA companies.

Foundry
From a foundry perspective, the main area to focus on for FinFET-based technologies is accurate modeling
of the process and devices. The production-proven BSIM4 models used since the 90-nm node are no
longer sufficient to model the 3D device. Furthermore, the new FinFET structures exacerbate the impact of
parasitic effects on circuit performance. Some of these impacts were secondary for previous nodes but they
are becoming much more prominent. The formation of a complete ecosystem including EDA tools, accurate
simulation models and Intellectual Property (IP) qualification in a timely manner is of key importance to
delivering a complete solution.

FinFET Technology 3
 FinFETs will be introduced by TSMC at the 16nm node. This node leverages the new manufacturing techniques
introduced at the 20-nm node (such as double patterning lithography) but requires enhancements to the
structures providing connectivity between the poly-silicon layers and the first metal routing layer (Metal 1)
which provides designer flexibility (See Figure 4).

A new compact model, BSIM-CMG, has been developed by UC Berkeley to account for the 3D effects and
multi-gate nature of FinFET devices. Foundries need to work closely with model developers, EDA vendors
and standardization committees to ensure numerical robustness of the model and to expand its coverage of
physical effects.

Besides the core FinFET device, the modeling of layout dependent effects of 3D structures requires additional
flexibility that conventional SPICE sub-circuit language syntax is not sufficient to handle. TSMC collaborated
with Synopsys to develop a new device modeling interface called TMI2, standing for TSMC Model Interface
2nd version, that delivers this flexibility. TMI2 also accounts for modeling of device degradation over time
(aging) and the statistical modeling of process variation. TSMC has adopted TMI2 for 16nm model release.

While the structures are small, the impact of the parasitic resistances and capacitances are very important.
Hence, this requires accurate modeling over 3-D geometries, as well as electric biases. Among these
parasitics, the source/drain contact, series resistances and the gate-to-source/drain capacitances are
important to model and extract accurately.

Contact (Cu)

Gate

Source Drain
Fin
"#

Substrate

Figure 4: FinFET Parasitic Capacitances

The FinFET device structures are more significantly different than planar devices, as the geometric structures
have very small dimensions and are often complex. Figure 5 shows the ideal fin structure and some of major
parasitic capacitances that require careful consideration. Due to the impact of lithography steps, the actual
manufactured structure deviates from the ideal, which makes it much more challenging to model this device
accurately. One of the key issues is incorporating the new key parasitics in the technology files without
burdening the EDA tools with requirements that could have a detrimental impact on runtime.

FinFET Technology 4
 3D poly-to-diffusion
capacitance Direction-dependent
Significant poly-end
diffusion-to-diffusion
capacitance
capacitance

Figure 5: Ideal Fin Structure

Traditional 2.5D RC extraction tools use a simple abstract view to model device structures, which may not
fully capture the electrical behavior of actual devices. They will further reduce the desired accuracy for
FinFET devices.

To reduce potential device modeling gaps inherited in 2.5D RC extraction tools, TSMC has closely collaborated
with its EDA partners including Synopsys to develop a new approach to closely model the actual device
structure. Therefore, the new solution improves the overall RC extraction accuracy for timing analysis and
circuit simulation without impacting EDA tool runtime or capacity.

EDA
EDA’s main role as part of the semiconductor ecosystem is to ensure the success of all 3 phases below:

Process development/early exploration (in collaboration with foundry, TCAD, SPICE)

``
Library/IP development (along with SPICE and characterization tools teams)
``
Design and analysis/simulation tools
``

Early process development delivers a good understanding of variations and limitations in the manufacturing
process, the expected structures that will be manufactured and their physical and electrical effects. For
FinFET technologies, the final transistor structures are not standard shapes and require a more sophisticated
modeling of the actual transistor structure. In addition, layout-/design-dependent effects impact the transistor
performance requiring new considerations and parameters for modeling circuit functionality.

During the library and IP development phase, the goal is to build structures that correlate to modeled
characteristics. The resulting foundation libraries and IP and early design kits enable early adopters to get a
head start on learning and using the new technology.

FinFET Technology 5
 Cell libraries, memories, analog IP and custom circuits all require a complete re-design for designs migrating
to FinFET-based process nodes. The performance and options available to circuit designers are different
than what they may be used to with planar MOSFETs. Historically, planar transistors’ performance varies
widely changing the length or width of transistors with a wide range of options. While transistors with very
short channel length (faster) can be built, the options available are less granular, for example getting more
drive current would require paralleling up more fins. While this enables potentially larger widths per equivalent
linear length than planar, the resulting width will be quantized by the fin gate widths. Differences in transistor
thresholds and limitations in the way passive components can be constructed require new considerations.

Providing accurate FinFET parasitic extraction and a generation of good, yet compact SPICE models is one
of the major challenges with FinFETs over planar devices. Enhancements to the foundational EDA tools, in
particular SPICE simulation, extraction and physical verification that operate on part of the design below the
first metal layer are required.

Addressing these new challenges alongside the new, more complex design-for-manufacturing rules, including
double patterning, together with larger designs, requires close collaboration with the foundry and early
adopters to deliver a robust proven solution.

FinFET Design Enablement

Leading-edge semiconductor companies are gaining access to new technology early and are getting their
customers involved at the early design stage in order to harness the full benefits without compromise to flow
or schedule while striving to achieve first-time silicon success.

To ensure the transition to FinFET processes is fast, transparent and as smooth as possible for the design
community, the foundry, EDA and IP industries need to work closely behind the scenes to ensure that the tools
meet foundry’s FinFET requirements and model the complexities involved.

TSMC’s Open Innovation Platform® (OIP) serves as the key to the success of FinFET design enablement, as it
provides a platform to bridge the gaps between TSMC’s FinFET technology requirements and OIP ecosystem’s
existing capabilities, identifies necessary enhancements, provides partners with EDA and IP enablement kits to
effectively implement needed changes in a timely manner for customer needs. Figure 6 depicts the collaboration
model among TSMC, EDA and IP partners and customers within the OIP framework. Throughout the synergy of
combined innovations within the entire OIP ecosystem, it delivers comprehensive solutions that customers can
design into TSMC FinFET technology early with smoother, faster and successful production.

For early technology adopters

Seed
IP

IP
IP partners
enablement Customers
kits
TSMC

EDA
EDA partners
enablement
kits
For early technology adopters

Figure 6: TSMC OIP® Enablement Collaboration Model

FinFET Technology 6
 The collaboration of TSMC’s FinFET enablement through OIP® can be described from the following aspects:

Earlier: To address the trend of increasing complexities and challenges in advanced process technologies,
TSMC is involving its OIP ecosystem partners and customers in FinFET enablement as early as from V0.05
of the process development stage, much earlier compared to the previous pull-in engagement stages of 40
nm from V0.5, 28 nm from V0.1, and 20 nm from pre-V0.1. Following TSMC’s OIP enablement collaboration
model, the availability of process related specifications, together with other components of the enablement
kit, are to ensure the readiness of EDA tools and IPs to fit customers’ early stage design needs. This is a joint
effort throughout the process technology development until it reaches V1.0 maturity for production. During
this early and concurrent engagement, all involved customers, EDA and IP partners will benefit by early
availability of their products that also meet process requirements. In areas such as extraction, SPICE and
rules development, TSMC starts early with EDA vendors such as Synopsys.

Broader: In order to fulfill customer needs at all design stages, and on various design types, the coverage
is now in a much wider range of digital, AMS and RF design flows, process design kits (PDKs), as well as
processor cores, physical and soft IPs. The EDA tools certification includes not only place and route (P&R),
physical verification and extraction of design rule checks (DRC), Layout Versus Schematic (LVS) and RC
Extraction (RCX), but also includes custom design and design analysis tools for statistical timing analysis
(STA), and power analysis tools of electro migration (EM) and IR drop.

Deeper: Quality assurance and productivity enhancement are an integral part of TSMC’s commitment to
customer support. The verification by more stringent quality requirements, validation procedures and intensive
test suites are used to authenticate the quality of results from the enablement. The outcomes of the certified
tools provide customers with clear guidance for their design implementation, as well as higher confidence
in the success of their designs. In additional to the certification of individual EDA tool, TSMC also add a new
layer of certification, called integrated tool certification, using real world multi-core CPU design cases with
pre-defined power, performance and area targets. Its focus is on implementing all certified tools throughout all
design phases that customers would apply in their SoC designs. The completion of individual and integrated
tool certifications, will give customers much higher confidence in achieving first silicon success using TSMC’s
16nm FinFET technology.

The 16 nm FinFET Process Solution

TSMC has developed an optimal solution for FinFET process-based designs through a close collaboration
with leading EDA partners in its OIP ecosystem, such as Synopsys. The advanced TCAD and parasitic
extraction tools with their highly accurate field solvers are implemented to fully understand the behavior of
the FinFET device structures from a physical and electrical perspective. The tight collaboration between
technology teams and TSMC has enabled accurate modeling of complex FinFET devices and interconnect
effects across the 16 nm process flow – including front-end-of-line (FEOL), middle-end-of-line (MEOL) and
back-end-of-line (BEOL), as described below. The comprehensive modeling provides a robust solution for
next-generation IC design using TSMC’s 16 nm process.

FEOL: It refers to process steps related to device transistor formation. The technology features modeled here
are inside the devices, hence layout or design invariant, i.e., the process parameters do not change based on
the impact of the design layout. TSMC provides enhanced SPICE models for FinFET FEOL device features for
simulation tools as explained in detail below.

MEOL: It refers to intermediate process steps that complete the transistor formation before contacts and
interconnect formation (BEOL). This is an area of increasing complexity in advanced process technologies,
especially FinFET processes consisting of new 3D structures and parasitic effects that are more sensitive to
the layout. TSMC provides detailed 3D models of the new context-dependent MEOL parasitic effects using
field solver and RC extraction technologies.

FinFET Technology 7
 BEOL: It refers to processing steps that involve contacts and interconnect formation. The modeling is independent
of the FinFET device process effects and incorporates interconnect parasitic effects only. Thus, for 16 nm
FinFET-based designs, there is minimal impact of the BEOL process to modeling and existing design flows and
tools. The resultant implementation solution will be transparent to the type of FET used with enhancements to
the Logic versus Schematic (LVS) tools providing the connectivity back to the fin structure within the FinFET.

Enhanced SPICE Modeling

The compact models of semiconductor devices are the bridge between design and manufacturing in the
integrated circuit industry. They serve as the “contract” on transistor behavior between foundries and their
many customers. Custom IC design at the transistor-level directly uses compact models as representation
of the transistor behavior. Digital implementation, verification and signoff depend on timing, noise and power
models that are derived from these compact models through library characterization. As such, compact
models play a key role in the IC technology.

The new compact model, BSIM-CMG, developed by UC Berkeley accounts for the 3D effects and multi-gate
nature of FinFET devices. This model is used by SPICE and Fast SPICE simulation tools such as Synopsys
HSPICE®, CustomSim™ and FineSim. Several BSIM-CMG revisions have emerged in the past two years to
account for missing physical effects and to tune the formulation and parameters for numerical robustness and
model extraction feasibility, based on foundry, simulator vendor and IDM user feedbacks

Fast and Accurate FinFET models: UC Berkeley releases BCM-CMG in Verilog-A format. Verilog-A provides
ease of use and flexibility in tuning the model formulation and parameters. However, simulating circuits with
millions of transistors in Verilog-A format leads to impractically long runtime and occupies large memory
footprints. Synopsys worked with TSMC on developing a C-language implementation of BSIM-CMG that is
orders of magnitudes faster than the Verilog-A version. The optimized model run at comparable speeds and
occupies comparable memory footprint as the BSIM4 model used for planar MOS devices. The Synopsys
implementation has additional features on top of the BSIM-CMG standard such as an analytical method to
accurately estimate threshold voltage.

Layout and Process Awareness: SPICE modeling incorporates the design invariant parasitic capacitances
and resistances of the technology accounting for the FEOL part of the SoC design process. Standard models
successfully served this purpose at older process nodes. For finer geometries and 3D shapes, these models
only provide baseline behavior lacking modeling for such complex and yet critical effects as layout-dependent
mechanical stress and proximity effects, parametric variability, restricted design rules, device aging and
reliability. SPICE sub-circuits used in the past to complement standard models are not flexible enough to
handle the layout dependent effects of 3D structures. TSMC and Synopsys jointly developed a new modeling
interface called TMI2 (TSMC Model Interface, version 2) that is capable of encapsulating layout dependent
effects, statistical modeling as well as MOS aging modeling into one single infrastructure. TMI2 provides the
flexibility to add new features on top of the model such as safe operating area (SOA) checks.

Early Access to Libraries and IP: TSMC and Synopsys collaborated to align the TSMC model
development and release with simulator development schedule. This created a smooth process for TMI2-
based FinFET model development, qualification and release. Synopsys also collaborated with TSMC
PDK, library and IP teams for relevant enablement, ensuring solid delivery of simulators, IP and design
methodologies to TSMC customers.

FinFET Technology 8
 Enhanced Techfile Generation and Extraction
Extraction is a foundational part of the SoC design process used during technology and library development
and as a critical part of design implementation and timing analysis. This is the part of the design flow most
impacted by FinFETs being used for:

Process exploration during optimization of the technology and libraries

``
Cell and macro characterization using full SPICE simulation
``
Large transistor-level extraction using full SPICE or Fast SPICE
``
Block or chip-level timing analysis and functional simulation
``

The two key components of the FinFET extraction solution are extraction techfile generation and accurate
RC extraction:

Techfile Generation: TSMC and Synopsys have collaborated to develop a techfile generation API (Application
Protocol Interface), using Synopsys’ QuickCap® field solver technology to handle the TSMC 3D FinFET
structure. QuickCap’s advanced features enable modeling of complex 3D structures and MEOL parasitics
using a uniquely detailed representation of the FinFET silicon profile. The validated techfile generation API
enables experienced technology teams to engage in early process exploration for high-accuracy FinFET
StarRC techfile development.

Accurate RC Extraction: For increased accuracy of signoff extraction and analysis in FinFET processes,
TSMC is providing StarRC technology files with data derived from the QuickCap field solver solution based
on real 3D profiles as inputs to Synopsys’s full-chip extraction StarRC tool. As described above, the field
solver 3D data provide a more accurate representation of the FinFET device and parasitic effects for more
accurate circuit simulation and signoff analysis. In addition, the technology files provide design teams with an
accelerated path to new process library characterization and development. Figure 7 shows the TSMC StarRC
flow for extracting 16 nm FinFET-based designs using integrated 3D models in StarRC technology files.

TSMC

3D characterization

Technology
file Layer
GDSII mapping
3D FinFET file
models

StarRC extraction

Capacitance Parasitic
report netlist

Figure 7: TSMC 16 nm StarRC Extraction flow

FinFET Technology 9
Conclusion
The new TSMC 16 nm technology being introduced to the market in 2013 offers new and exciting
opportunities to the semiconductor industry for continued innovation. The new FinFETs satisfy the
requirements of mobile and high-performance computing applications, delivering a larger reduction in
power consumption, higher switching performance and higher levels of integration than the previous
generation planar transistor-based technologies.

The close collaboration between Synopsys and TSMC through the early stages of technology development
has created a good understanding of the challenges associated with FinFETs and together has developed
innovative solutions that address these challenges.

The result of this collaboration as part of TSMC’s Open Innovation Platform® will ensure the delivery of
solid, proven EDA tools, IPs and design flow methodologies that provide designers with a transparent low-
risk FinFET solution for product development in TSMC’s 16-nm technology. The new TSMC 16-nm design
reference flow based on certified EDA tools when introduced later in 2013 will ensure a smooth adoption of
new FinFET designs and a fast ramp to volume production.

For more information on the TSMC 16-nm technology and the Synopsys EDA tool support please
contact the respective sales representatives.

Synopsys, Inc.  700 East Middlefield Road  Mountain View, CA 94043  www.synopsys.com
©2013 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at http://www.synopsys.com/copyright.html. All other names mentioned herein are trademarks or registered trademarks of their respective owners.
04/13.CE.CS2583.