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Experiment-1
Theory-
The voltage transfer characteristic of a BJT inverter is consisting of threeregions,the cut off when
Vi is low, the active where the characteristic has a slope and the saturation region where the
collector current is the maximum and the output voltage is low equal to VCEsat.
1. Cut-off region.
3. Saturation region.
BJT Inverter can be best expressed by its voltage transfer characteristic (VTC) or DC transfer
characteristic. That relates the output voltage to the input one.
If:
(11)
Circuit Diagram:
5.000V V1
R2 5Vdc
1k
Q1 Rbreak
R1
0
V
V1 = 0v V2 Rbreak
V2 = 5v 40238
V
TD = 0 1k
TR = 0 0
TF = 0
PW = 50ns 0
PER = 100ns
NETLIST DESCRIPTION:
V_V2 N000431 0
Theory :-
Inverter Operation:
INPUT OUTPUT
A NOT A
0 1
1 0
(9)
(a) Transient Analysis of NMOS inverter using step input.
M1 5. 000V V1
5Vdc
M2N 6755
4. 513V 0
M2
V
V1 = 0v V2
V2 = 5v M2N 6755 V
TD = 0
TR = 0 0
TF = 0
PW = 50ns 0
PER = 100ns
Netlist Description:
V_V2 N000291 0
Output Waveform
Theory: CMOS inverters are the some of the most widely used and adaptable MOSFET
inverters used in chip design. They operate with very little power loss and at relatively high
speed,
A CMOS inverter contains a PMOS and a NMOS transiter connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, where Vin is connected to the date terminals and V OUT is connected to
the drain terninals.
When a low voltage (0 volt) is applied at the input , the top transistor (P- Type) is
conducting (switch closed) while the bottom transistor behaves like an open circuit.
Therefore, the supply voltage(5V) appears at the output.
Conversly when high voltage(5V) is applied at the input, the bottom transistor (N-Type)
is conducting (switch close) while the top transistor behaves like an open circuit.
Hence output voltage is low(0V)
The function of this gate can be summrized by the following table.
Input OutPut
High Low
Low High
The ouput is the opposite of the input- this gate inverts the inputs.
Notice that always one of the transistors will be an open circuit and no current flows from
the supply voltage to ground.
(1)
Transistor Switch Model
When Vin is low, the NMOS is “off”, while the PMOS stays on “ON”: Instantly charging
Vout to logic high. When Vin is high , the NMOS is “on” and the PMOS is “ON”: draining
the volatage at Vout to logic low.
Procedure-
(2)
M2 5.000V V1
5Vdc
IRF9520
V1 = 0v 0VM1
V2
V2 = 5v 0
V V
TD = 0
TR = 0 M2N6755
TF = 0
PW = 50ns 0 0
PER = 100ns
OUTPUT Waveform
(3)
(a) Analysis of CMOS inverter using step input.
(b) (b)Transient Analysis of CMOS inverter using step input with parameters.
(c) (b)Transient Analysis of CMOS inverter using step input with parameters.
(d) (b)Transient Analysis of CMOS inverter using step input with parameters.
Experiment-3
Theory:-
V1 V2 OUTPUT
Low Low High
Low High Low
High Low Low
High High Low
If logical 1’s are asssociated with high voltages then the function of this gate is
called NOR for negated OR.
Again, there is never a conducting path from the supply voltage to ground.
Circuit Diagram
(7)
M3 5.000V V1
M4 5Vdc
IRF9241
IRF9241
0V
0
M2
V1 = 0v V2
V2 = 5v V M2N6755
5.000V
TD = 0 M1 1.734uV
TR = 0 V
TF = 0 V
V3
PW = 50ns 0 M2N6755
PER = 100ns 0V TD = 0
TF = 0
0 0PW = 50ns
PER = 100ns
V1 = 5v
TR = 0
V2 = 0v
NETLIST DESCRIPTION:
M_M1 N00413 N00536 0 0 M2N6755
M_M2 N00413 N00570 0 0 M2N6755
M_M3 N000552 N00536 N00626 N00626 IRF9241
M_M4 N00413 N00570 N000552 N000552 IRF9241
V_V1 N00626 0 5Vdc
V_V2 N00536 0
+PULSE 0v 5v 0 0 0 50ns 100ns
V_V3 N00570 0
+PULSE 5v 0v 0 0 0 50ns 100ns
Output Waveform
Experiment-2
Theory-
V1 V2 Output
Low Low High
Low High High
High Low High
High High Low
If logical 1’s are associated with high voltages then the function of this gate is called
NAND for negated AND.
Again ,there is never conducting path from the supply voltage to ground.
(4)
Circuit Diagram
M4
5.000V
IRF9520 IRF9520
M3 V1
5Vdc
V1 = 0v V2 M1 5.000V 5.000V
V2 = 5v 0
V M2
V
TD = 0 0V
TR = 0 M2N6755 M2N6755V V3
TF = 0
PW = 50ns 0 TD = 0
PER = 100ns TF = 0
0PW = 50ns
PER = 100ns
0 V1 = 5v
TR = 0
V2 = 0v
NETLIST DESCRIPTION:
(5)
Output Waveform