A Mini Project Report

on

“Vedic Multiplier using Karatsuba and Urdhva-

Tiryagbhyam Sutra ”
Submitted in partial fulfillment of the requirements for the award of the degree of

BACHELOR OF TECHNOLOGY
in
ELECTRONICS AND COMMUNICATION ENGINEERING

by
A. Vidruma (16wh1a0461)

K. Rukumbai (16wh1a0492)

V. Spandhana (16wh1a04c0)

P. Lavanya (17wh5a0415)

under the guidance of

Ms K. Brunda Devi
Assistant Professor

Department of Electronics and Communication Engineering

BVRIT HYDERABAD College of Engineering for Women
(Approved by AICTE, New Delhi and Affiliated to JNTUH, Hyderabad)
(NBA Accredited – EEE, ECE, CSE and IT)
Bachupally, Hyderabad – 500090
2019-20
 //second page//
DECLARATION

We hereby declare that the work described in this report, entitled “Vedic
Multiplier using Karatsuba and Urdhva-Tiryagbhyam Sutra” which is being
submitted by us in partial fulfillment for the award of the degree of Bachelor of
Technology in the department of Electronics and Communication Engineering at
BVRIT HYDERABAD College of Engineering for Women, affiliated to
Jawaharlal Nehru Technological University Hyderabad, Kukatpally, Hyderabad –
500085 is the result of original work carried out by us under the guidance of Ms K.
Brunda Devi(Assistant Professor). This work has not been submitted for any
Degree/Diploma of this or any other institute/university to the best of our knowledge
and belief.

Place: Hyderabad
Date:
Names and signatures of the students
A. Vidruma (16wh1a0461)
K. Rukumbai (16wh1a0492)
V. Spandhana (16wh1a04c0)
P. Lavanya (17wh5a0415)
Department of Electronics and Communication Engineering
BVRIT HYDERABAD College of Engineering for Women
(Approved by AICTE, New Delhi and Affiliated to JNTUH, Hyderabad)
(NBA Accredited – EEE, ECE, CSE and IT)
Bachupally, Hyderabad – 500090

Certificate

This is to certify that the major/mini project report, entitled “Vedic Multiplier
using Karatsuba and Urdhva-Tiryagbhyam Sutra” is a record of bonafide work
carried out by A.Vidruma(16WH1A0461), K.Rukumbai(16WH1A0492),
V.Spandana(16WH1A04C0), P.Lavanya(17WH5A0415) in partial fulfillment for the
award of the degree of Bachelor of Technology in the department of Electronics and
Communication Engineering at BVRIT HYDERABAD College of Engineering
for Women, affiliated to Jawaharlal Nehru Technological University Hyderabad,
Kukatpally, Hyderabad – 500085.

Supervisor Head of the Department

Ms. K Brunda Devi Dr. J. Naga Vishnu Vardhan
Assistant Professor,ECE Professor, ECE

External Examiner
 ACKNOWLEDGMENT

The satisfaction that accompanies in successful completion of the task would

be incomplete without the mention of the people who made it possible.

We wish to express our deep sense of gratitude to our guide Ms.K. Brunda
Devi, Assistant Professor, Department of Electronics and Communication
Engineering, BVRIT HYDERABAD College of Engineering for Women, for her able
guidance and suggestions, which helped us in completing this project work on time.

We would like to thank Dr. J. Naga Vishnu Vardhan, Professor and Head,
Department of Electronics and Communication Engineering for his guidance, support
and encouragement.

We express our gratitude towards our honorable Principal, Dr. K V N Sunitha

and the management for providing all the facilities.

We also thank all the Faculty and non-teaching staff members of

Electronics and Communication Engineering department, who supported us directly
or indirectly in successful completion of this project work.

Finally, we thank all our friends and family members for their continuous
support and help.

Names of the students

A. Vidruma (16wh1a0461)
K. Rukumbai (16wh1a0492)
V. Spandhana (16wh1a04c0)
P. Lavanya (17wh5a0415)
 ABSTRACT
Vedic Mathematics is the technique to solve complex arithmetic computations.
Multiplication is used in many operations such as division, squaring and many signal
processing applications. It is often implemented using shift and add operations. A
high speed processor depends greatly on the multiplier as it is one of the key hardware
blocks in most digital signal processing as well as in general processors. Currently the
speed of the multipliers is limited by the speed of adders used for partial products.
Our project provides an 8-bit unsigned binary multiplier using the methodology of
Vedic Mathematics. A combination of Urdhva-Tiryagbhyam sutra and Karatsuba
algorithm is used to implement the binary multiplier. Karatsuba algorithm is best
suited for higher bits and Urdhva-Tiryagbhyam algorithm is best suited for lower bit
multiplication. The Urdhva-Tiryagbhyam algorithm reduces the complexity of the
mathematical process and improves the speed. The Karatsuba algorithm minimizes
the iterative steps in multiplication process.

//sixth page//
CONTENTS
 //seventh page//
LIST OF FIGURES AND TABLES
 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

1. INTRODUCTION

Multiplication is the most important arithmetic operation in signal processing

applications. All the signal and data processing operations involve multiplication.
As speed is always a constraint in the multiplication operation, increasing speed
can be achieved by reducing the number of steps in computation process. The
speed of multiplier determines the efficiency of such a system. In any system
design, the three main constraints which determine the performance of the system
are speed, area and power requirement.

Vedic Mathematics was reconstructed from the ancient Indian scriptures (Vedas).
It is mainly based on sixteen principles or word-formulae which are termed as
sutras. This is very interesting field and presents some effective algorithms which
can be applied to various branches of engineering such as computing and digital
signal processing. Integrating multiplication with Vedic Mathematics techniques
would result in saving of computational time. Thus, integrating Vedic
Mathematics for the multiplier design will enhance the speed of multiplication
operation. Multiplier based on Vedic Mathematics is one of the fast and low
power multiplier. Minimizing power consumption for digital systems involves
optimization at all levels of the design. This optimization includes the technology
used to implement the digital circuits, the circuit style and topology, the
architecture for implementing the circuits and at the highest level the algorithms
that are being implemented. Digital multipliers are the most commonly used
components in any digital circuit design. They are fast, reliable and efficient
components that are utilized to implement any operation. Depending upon the
arrangement of the components, there are different types of multipliers available.
Particular multiplier architecture is chosen based on the application.

Sixteen Sutras of Vedic Mathematics

1. (Anurupye) Shunyamanyat –If one is in ratio, the other is zero.

2. Chalana-Kalanabyham –Differences and Similarities.

3. Ekadhikina Purvena –By one more than the previous One.

Department of ECE, BVRIT HYDERABAD Page 1

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

4. Ekanyunena Purvena –By one less than the previous one.

5. Gunakasamuchyah –The factors of the sum is equal to the sum of the factors.

6. Gunitasamuchyah –The product of the sum is equal to the sum of the product.

7. Nikhilam Navatashcaramam Dashatah –All from 9 and last from 10

8. Paraavartya Yojayet –Transpose and adjust.

9. Puranapuranabyham –By the completion or no completion.

10. Sankalana- vyavakalanabhyam – By addition and by subtraction.

11. Shesanyankena Charamena –The remainders by the last digit.

12. Shunyam Saamyasamuccaye –When the sum is the same that sum is zero.

13. Sopaantyadvayamantyam –The ultimate and twice the penultimate.

14. Urdhva-tiryakbhyam –Vertically and crosswise.

15. Vyashtisamanstih –Part and Whole.

16. Yaavadunam –Whatever the extent of its deficiency.

The multiplier architecture can be generally classified into three categories. First
is the serial multiplier which emphasizes on hardware and minimum amount of
chip area. Second is parallel multiplier (array and tree) which carries out high
speed mathematical operations. But the drawback is the relatively larger chip area
consumption. Third is serial- parallel multiplier which serves as a good trade-off
between the times consuming serial multiplier and the area consuming parallel
multiplier

Department of ECE, BVRIT HYDERABAD Page 2

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

2. ALGORITHMS OF VEDIC MATHEMATICS

URDHVA TIRYAGBHYAM SUTRA

A Vedic Sutra, the word “Urdhva-Tiryakbhyam” resources vertical and crosswise

multiplication. This multiplication formula is pertinent to all cases of algorithm for N
bit numbers . The generation of all partial products can be done with the concurrent
addition of these partial products. Conventionally this sutra is used for the
multiplication of two numbers in decimal and binary number system. Advantage of
using this type of multiplier is that as the number of bits increases, delay and area
increases very slowly as compared to other multipliers. The figure 1 explains
parallelism in generation of partial products and their summation. The algorithm can
be generalized for n x n bit number. This multiplier is independent of the clock
frequency of the processor as the partial products and their sums are calculated in
parallel. The same amount of time will require by this multiplier to calculate the
product and thus it is independent of the clock frequency. There is an increase in
processing power as a result of high clock frequency. The power dissipation is also
increases which is a disadvantage results in higher device operating temperatures.
Through the implementation of Vedic multiplier in processor design the problems are
easily over comed and hence the device failure may be avoided. The great advantage
of this multiplier is gate delay and area increases very slowly with the number of bits
increases as compared to conventional multipliers. Hence it is more efficient than
conventional multipliers. This architecture is quite efficient in terms of silicon
area/speed.

Algorithm for 4 x 4 bit Vedic multiplier Using Urdhva Tiryakbhyam

for two Binary numbers

A3 A2 A1 A0 (Multiplicand)

* B3 B2 B1 B0 (Multiplier)

------------------------------------------------------------

P7 P6 P5 P4 P3 P2 P1 P0 (Product)

Department of ECE, BVRIT HYDERABAD Page 3

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

Figure 1

A0B0 P0
A0B1 + A1B0 P1
A0B2 + A1B1 + A2B0 P2
A0B3 + A1B2 + A2B1 + A3B0 P3
A3B1 + A2B2 + A1B3 P4
A3B2 + A2B3 P5
A3B3 P6
LEFT OUT CARRY BIT P7

Department of ECE, BVRIT HYDERABAD Page 4

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

Karatsuba Sutra

The Karatsuba algorithm is a fast multiplication algorithm that uses a divide and
conquer approach to multiply two numbers. The naive algorithm for multiplying two
numbers has a running time of ‫(סּ‬n2). while this algorithm has a running time of ‫(סּ‬nlog
3
2 ). Being able to multiply numbers quickly is very important. Computer scientists
often consider multiplication to be a constant time O(1)O(1) operation, and this is a
reasonable simplification for smaller numbers; but for larger numbers, the actual
running times need to be factored in, which is O(n2). The point of the Karatsuba
algorithm is to break large numbers down into smaller numbers so that any
multiplications that occur happen on smaller numbers. Karatsuba can be used to
multiply numbers in all base systems (base-10, base-2, etc.).

The Karatsuba algorithm decreases the number of subproblems to three and ends up
calculating the product of two nn-bit numbers in ‫(סּ‬nlog 23) time--a vast improvement
over the naive algorithm.To multiply two nn-bit numbers, x and y, the Karatsuba
algorithm performs three multiplications and a few additions, and shifts on smaller
numbers that are roughly half the size of the original x and y.

Here’s how the Karatsuba method works to multiply two n-bit numbers x and y which
are in base b.

Considering two 16-bits wide binary variables, X and Y for the example. The
numbers are broken down as follows into the two significant halves:

X = XH  2 8 + XL--------------------------------------------------------- (1)

Y = YH  2 8 + YL ----------------------------------------------------- (2)

where, XH and YH represent the two most significant halves of X and Y respectively while
XL and YL represent their two least significant halves. Hence,

XY = (XH  2 8 + XL)(YH  2 8 + YL)---------------------------------- (3)

The above expression shows the multiplication of the two binary numerals and when
expanded they yield four multiplication terms, each N-bits wide as shown below:

Department of ECE, BVRIT HYDERABAD Page 5

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

A = XHYH------------------------------------------------- (4)

B = XHYL +XL YH--------------------------------------- (5)

C = XLYL------------------------------------------------- (6)

XY = A2 16 + B2 8 + C ------------------------------(7)

where, A, B and C represent the three combinatorial expressions. A and C each require one
multiplier while B requires two.

So, the long multiplication technique here requires a total of four 8-bit multipliers for proper
implementation. However, going by the Karatsuba approach, the multiplication terms shall be
reduced by substituting one stage of multiplier with adders and subtractors as follows:

B = (XH+XL)(YH +YL) - A - C = B ---------------------(8)

Here, B represents an alternative manner of representing the same term B with the
calculation of just one multiplication term as opposed to the two terms in case of B.

XY = A2 16 + B2 8 + C--------------------------- (9)

The above expression depicts the numerical representation of the Karatsuba algorithm
involving the calculation of three multiplicands as opposed to the four required in case of any
classical approach.

Mathematically, the Karatsuba algorithm thus effectively reduces the operational overheads
of the multiplier in terms of area and power. However, the algorithm alone doesn’t really
simplify the design of the multiplier core in the design.

Department of ECE, BVRIT HYDERABAD Page 6

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

TOOLS USED

Simulation Software: Modelsim6.1e has been used for simulation. For synthesis and
verification ISE14.3i (Integrated system environment) has been used.

Hardware used: Xilinx Spartan3E (Family), XC3S100(Device),VQ100(Package), -5

(Speed Grade) FPGA devices.

DIGITAL CIRCUIT DESIGN USING XILINX ISE TOOLS

Xilinx Tools is a suite of software tools used for the design of digital circuits
implemented using Xilinx Field Programmable Gate Array (FPGA) or Complex
Programmable Logic Device (CPLD). The design procedure consists of (a) design
entry, (b) synthesis of the design and implementation of the design, (c) functional
simulation and (d) testing and verification. The following CAD tools are used for
digital designs by entering the code in various ways: using a schematic entry tool,
using a hardware description language (HDL) – Verilog or VHDL or a combination
of both Verilog and VHDL .This thesis implement programs using the design flow
that involves the use of Verilog HDL. The CAD tools enable you to design
combinational and sequential circuits starting with Verilog HDL design
specifications. The steps of this design procedure are listed below: 1. Create Verilog
design input file(s) using template driven editor. 2. Compile and implement the
Verilog design file(s). 3. Create the test-vectors and simulate the design (functional
simulation) without using a PLD (FPGA or CPLD). 4. Assign input/output pins to
implement the design on a target device. 5. Download bit stream to an FPGA or
CPLD device. 6. Test design on FPGA/CPLD device

The following segments are contained within the Xilinx software environment of a
Verilog input file. Header: module name, list of input and output ports. Declarations:
input and output ports, registers and wires. Logic Descriptions: equations, state
machines and logic functions. End: end module

Verilog input format must be used for all the designs. For combinational logic designs
the state diagram segment is not exist.

Department of ECE, BVRIT HYDERABAD Page 7

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

Programmable Logic Device:

FPGA The digital designs of proposed multiplier are implemented in the Basys2
board which has a Xilinx Spartan3E –XC3S100E FPGA with VQ100 package. This
FPGA part belongs to the Spartan family of FPGAs. These are a variety of packages
for these device families. This thesis uses devices that are packaged in 100 pin
package with the following part number: XC3S100E-VQ100. There are about 50K
gates in this FPGA device.

Creating a New Project

Click on the Project Navigator Icon on the Windows desktop for starting Xilinx
Tools. Then a Project Navigator window is opened on desktop screen. The last
accessed project is shown by this window

Showing Xilinx Project Navigator window

Department of ECE, BVRIT HYDERABAD Page 8

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

Opening a project

To create a new project select File->New Project. A new project window is opened on
the desktop.

Showing New Project Initiation window (snapshot from Xilinx ISE software)

Project Name: Give the name to your project

Project Location: Give the storage location.

Leave the top level module type as HDL. Example: If the project name is “or_gate”,
enter “or_gate” as the project name and then click on “Next” button.

This brings up the following window:

Department of ECE, BVRIT HYDERABAD Page 9

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

Figure 6.3 Showing Device and Design Flow of Project (snapshot from Xilinx ISE
software)

Click on the „value‟ area and select from the list of values that appear for each of the
properties given below then click on the „value‟ area and select from the list of values
that appear.

 Device Family: Family of the FPGA select the Spartan3E FPGA‟s.

 Device: The number of the actual device enter XC3S100E.

 Package: The type of package with the number of pins. The Spartan FPGA used in
this lab is packaged in VQ100 package.

 Speed Grade: The Speed grade is “-5”.

Synthesis Tool: XST [VHDL/Verilog]

 Simulator: This tool is used to simulate and verify the functionality of the design.
Modelsim simulator is integrated in the Xilinx ISE. Hence choose “Modelsim-XE
Verilog” as the simulator or even Xilinx ISE 14.3i Simulator can be used.

 Then save the entries by clicking on NEXT button

Department of ECE, BVRIT HYDERABAD Page 10

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

Creating a Verilog HDL input file for a combinational logic design

A design entry can be done using a structural or RTL description using the Verilog
HDL. The HDL Editor is used which is available in the Xilinx ISE Tools to create a
Verilog HDL input file (.v file). Click on the NEW SOURCE then a window pops up as
shown in Figure

Showing Creating Verilog-HDL source file (snapshot from Xilinx ISE software)

Select Verilog Module and enter the name of the Verilog source file in the File Name
option. Select Add to project option so that the source need not be added to the project
again. To accept the entries click on Next. And then click on FINISH.

The following window appears

Department of ECE, BVRIT HYDERABAD Page 11

 Vedic Multiplier using Karatsuba and Urdhva-Tiragbhyam Sutra

Verilog Source code editor window in the Project Navigator (from Xilinx ISE
software)

The module name, the list of ports and also the declarations (input/output) for each
port are shown by the generation of Verilog source code template. After the
declarations and before the end module line the combinational logic code can be
added to the verilog code. For example, an output x in an AND gate with inputs a and
b can be described as, assign x= a & b; the names are case sensitive. Other constructs
for modeling the logic function: A given logic function can be modeled in many ways
in verilog.

Department of ECE, BVRIT HYDERABAD Page 12