1

Microcontroller 8051
2 A microcomputer system

ADDRESS BUS

CONTROL BUS
CPU
ROM RAM Interfacing Circuits
(Microprocessor)
IO and other
peripheral devices
(Timers, UART, KBDC,
Interrupt controllers,

DATA BUS
3 Microprocessors

 General Purpose architecture

 General purpose instructions
 Comprehensive and flexible instruction set
 Read data from external memory, perform extensive calculations on data, store
the result in mass storage device (external memory) or display the results
 Programs to be executed are loaded in RAM
 Very few programs are stored in ROM (ROM/RAM usage ratio is low)
 ROM based programs are generally monitor programs which operate the
peripherals and provide basic IO services
 Philosophy: The design of microprocessor is made as flexible and as general
purpose as possible to solve large number of problems using the same device
4 Microprocessors

ALU

ACCUMULATOR
PROGRAM
STACK POINTER
COUNTER REGISTERS

TIMING AND INTERRUPT

CONTROL UNIT CIRCUITS
 Micro-controllers
5
ADC/DAC

IO PORTS
TIMER/COUNTER
ALU

ACCUMULATOR IO PORTS

REGISTERS
INTERNAL SERIAL IO PORT
ROM
INTERNAL RAM
INTERRUPT
CIRCUITS
STACK POINTER

PROGRAM COUNTER CLOCK CIRCUITS

6 Micro-controllers
 A general purpose programmable device with limited processing capabilities as
compared to microprocessor. It can perform the following:
 Read data
 Process data
 Control its environment based on the results of data processing

 The prime use of a micro-controller is to Control the Operation of a machine

and thereby any process (that is controlled via the machines).
 The controlling logic and action to be taken is written in the form of a fixed
program and is stored in ROM. Hence the program do not change over the
lifetime of the system. Thus making the device application-specific.
 Instruction set of microcontroller is designed to be a limited set of single and
double byte instructions for data/code movement from internal memory to ALU.
 Instructions are coupled with pins of IC. The pins of a typical micro-controller are
multifunctional and programmable.
 The architecture and instruction set are optimized to handle data in bit and
byte size
 Comparison of microprocessor and microcontroller
7 Sr No Microprocessor
1 Architecture: ALU, registers, TCU
2 Concerned with rapid movement of code
and data from external addresses to chip
3 Large number of instructions to perform data
transfer between microprocessor and
external memory/IO
4 Mostly operates on byte sized data and have
very few bit manipulating instructions
5 Usually require lots of peripheral ICs to
function as a Micro-computer
6 Small ROM:RAM ratio
7 Used for designing General Purpose digital
computing system capable to handle
different type of programmes
Microcontroller
Architecture: All functional blocks of microprocessor +
(Internal ROM, Internal RAM, Parallel IO ports, Serial IO,
Timers/Counters, ADC, DAC)
Concerned with rapid movement of bytes and bits within
the chip
Few instructions for data transfer between microcontroller
and external memory. Instruction set is lean!
Microcontroller often manipulates bits and so have a
large number of bit manipulating instructions
Require less number of supporting ICs as most important
peripheral blocks are already fabricated within micro-
controllers. It is also Loosely termed as “Computer on
chip” or “System on Chip”
Large ROM:RAM ratio
Used to design application specific dedicated systems.
For example special purpose digital controllers or DSP
controllers. They also possess a very well built interrupt
circuitry as it is supposed to work with external inputs from
surrounding processes.
 8 Genesis
Year Family Name Features
1976 MCS48 8748 17000 Tr, 8 bits, 1KB EPROM, 64b RAM, 27 IO pins, 8 bit timer
1980 MCS51 8051 8 Bit, 60K tr, 4K ROM, 128 b RAM, 32 IO pins, 2 nos of 16 bit counters
Survey
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10 MCS51 Family

IC name Features
8031 0 Byte ROM, 128 Byte RAM, 2 – 16 bit counters
8032 0 Byte ROM, 256 Byte RAM, 3 – 16 bit counters
8051 4K Byte MROM, 128 Byte RAM, 2 – 16 bit counters
8052 8K Byte MROM, 256 Byte RAM, 3 – 16 bit counters
8751 4K Byte EPROM, 128 Byte RAM, 2 – 16 bit counters
8752 8K Byte EPROM, 256 Byte RAM, 3 – 16 bit counters
8951 4K Byte Flash ROM, 128 Byte RAM, 2 – 16 bit counters
8952 8K Byte Flash ROM, 256 Byte RAM, 3 – 16 bit counters
11 8051 Microcontroller Features
 First member of MCS51 family of Intel microcontrollers
 40 pin, +5V single supply, 1-16 MHz
 Harvard Architecture
 4K factory masked ROM, 128 Byte RAM
 4 Nos of 8 bit IO ports
 2 nos of 16 bit timers
 Serial Interface (USART)
 64K external code memory space
 64K external data memory space
 Operates on single bits
 210 bit addressable locations available
 4 µs Multiply/Divide facility
 ARCHITECTURE
of
12
Intel 8051
Architecture Block
Diagram
13 of 8051
 Internal ROM and RAM
 I/O Ports with programmable pins
 Timers/counters modules
 Serial data communication modules
 Eight bit CPU with registers A (Accumulator) and B
 Sixteen bit program counter (PC) and Data pointer
(DPTR)
 Eight bit program status word (PSW)
 Eight bit stack pointer (SP)
 Internal ROM or EPROM (8751) of 0 (8031) to 4K (8051)
 Internal RAM of 128 Bytes:
 Four register banks each containing 8 registers
 Sixteen bytes, which may be addressed at bit level
 Eighty bytes of general purpose data memory
 32 I/O pins arranged as 4 eight bit ports P0-P3
 Two 16 bit timers/counters
 Full duplex serial data receiver/transmitter: SBUF
 Control registers TCON, TMOD, SCON, PCON, IP, and IE
 Two external and three internal interrupt sources
 Oscillator and clock circuits
Programming
model
14 of 8051
• ‘*’ indicates the register is
both byte and bit
addressable
• The registers of 8051 can be
identified by their 8 bit
internal address
• Program counter PC do not
have internal 8 bit addresses
assigned to it
• DPTR as a 16 bit register is
not assigned any internal
address. However DPH and
DPL have their internal 8 bit
address
Pin configuration

 Four eight bit ports are available; P0, P1, P2, P3.
The pins of each port are marked by Px.y (P3.0:
port 3 pin 0). Thus 32 pins may be used for I/O
purpose
 Port 0 can also act as 8 bit multiplexed address
data bus when external memory is connected
 Port 1 is a dedicated I/O port
 Port 2 is again multifunctional with IO function
and can also be used to provide higher order
address when external memory is connected.
 Port 3 can be used as an IO port. It can also be
used to provide pins to the external world for
interrupt, timers, USART and memory controls
 Rest of the pins are for connecting crystal, power
supply, ground, enabling external ROM access,
ALE and EA-bar signals
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8051 oscillator and clock
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17 Program counter (PC)
 Points to the 16 bit memory address (internal or external) from where next
instruction word has to be fetched.
 Auto-increments after each and every code fetch operation
 Is not under programmers’ control.
 The status of EA-bar pin affects the operation of memory selection as
follows:
 If EA-bar is tied high (disabled state):
 Internal ROM will be considered for code fetch if address range in PC is (0000H – 0FFFH)
 If PC address is in range (1000H-FFFFH) then external ROM will be selected for code
fetch

 If EA-bar is tied low (enabled state):

 External 64 KB ROM will be considered for code fetch for 0000H-FFFFH address range in
PC

 No internal 8 bit address assigned to PC

18 Data pointer (DPTR)

 Mainly used to point to external RAM

 Also used to point to Internal and External code memory
 Has no address
 Composed of two 8 bit registers DPH and DPL with individual 8 bit addresses
19 Flag register
Internal RAM memory organization
1. Thirty
20 two bytes from address 00H-
1FH make up 32 working registers
organized as four banks of eight
registers each. The four banks are
numbered from 0-3 and are made
up of 8 registers named R0-R7. The
bits RS0 and RS1 in PSW determine
which bank of registers are
currently in use when program is
running
2. A bit/byte addressable area of 16
bytes occupies RAM byte address
20h-2Fh; forming a total of 128 bit
addressable locations. An
addressable bit may be specified
by its bit address 00h-7Fh
3. A general purpose RAM area
above bit area, from 30H-7FH,
addressable as bytes is known as
Scratch Pad area of Internal RAM
21 Special function Registers of 8051
Name of Internal Name of Internal
registers Address registers Address
A E0 IE A8
B F0 IP B8
PSW D0 TMOD 89
DPH 83 TCON 88
DPL 82 TL0 8A
P0 80 TH0 8C
P1 90 TL1 8B
P2 A0 TH1 8D
P3 B0 SCON 98
SP 81 SBUF 99
PCON 87
Stack and stack pointer
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 Stack is a part of internal RAM that is maintained as LIFO manner to store and retrieve data
quickly
 The 8 bit stack pointer (SP) register of 8051 is used to hold the “Top of the stack” address
 The stack of 8051 is fully ascending stack i.e. SP points to a memory location that is filled with
relevant data (full) and when data is placed in stack it grows from lower memory location to
higher memory location (ascending)
 In other words, SP increment by one place before storing data on stack.
 As data is retrieved from stack, then SP decrements to point to the next available byte of stored
data.
 SP is filled with data 07H after reset. That means any new data inserted using PUSH instruction will
overwrite the contents register R0 of bank 1.
 The programmer is responsible to make sure that the stack should not grow and corrupt the
useful contents of register banks, bit addressable area and scratch pad area of internal RAM.
 The content of SP can be set to any internal address by the programmer (MOV SP, #29H).
23
24
IO ports of 8051
25 Ports of 8051
 There are four ports in 8051 each of 8 bit size. The information travels along the ports in
parallel form, hence conceptually they are parallel ports.
 Individual ports or port pins can be configured as input/output or for alternate function.
 All ports supports bit-wise access. That means, each of the port pins may be configured for
input/output or for alternate functions.
 Each of the port pins are preceded by a D-flipflop. Thus eight pins require 8 D-flipflops. The
collection of such a series of D-flipflop is known as port latch. Thus 8051 has four port
latches, namely; P0, P1, P2 and P3. All the port latches support bitwise access.
 During write operation into an output port/pin information is always written in port latches.
The new status of port laches are then reflected on the port pins only after write operation
is complete.
 During read operation:
 The default operation is to read pin by invoking instructions for reading a port/pin. Please
note that the content of port pin and port latches may not be same during read operation.
 Only in case of read-modify write type of instructions, (increment of port value, logical
operation on ports), port pins are read, modified and then followed by usual write operation
of the results into the concerned port latch.
 The ports of 8051 must be configured as an input port by writing logic-1 in the port latches.
26 Ports of 8051

 PORT 0
 Can be configured as input-output port
 If used as an output port, external pull-up resistance must be connected between port
pins and supply to allow valid logic states to appear as output information on the
concerned port/port pins .
 Best use as an input port/pin

 If external memory is connected, port 0 pins can be used as lower order address-
data multiplexed pins (AD7-AD0)
 Internal circuitry of port 0 determines how the pins should behave depending on
the instruction to be executed, memory pointers used, value of address and
status of 𝐸𝐴 signal.
• When data transfer operation is required:
• Input Pin: Port 0 Circuit
• If D=1
27 • Then:
• Q-bar=0
• Both T1 and T2 OFF
• Thus Pin0.x floats and acts as input
pin
• The pin status may be read when
“Read pin data” signal is activated
internally
• Output Pin:
• An external pull-up resistance must be
connected between Pin 0.X and Vcc, so that
pins of port 0 provides a stable voltage output
• If D=1
• Then:
• Q-bar=0
• Both T1 and T2 OFF
• But Pin0.x will produce valid logic
HIGH state if the external pull-up
resistor is connected
• P0.X=HIGH
• If D=0
• Then:
• Q-bar=1
• T1 OFF and T2 ON
• Thus Pin0.x will produce valid logic
LOW state if external pull-up resistor
is connected
• P0.X=LOW
• The best use of PORT0 is as an input port
 28 Port 0 Circuit: Address output operation
• When an external memory has to be connected t0 8051,
PORT0 pins will be used to provide lower order address/data
to port 0 pins
• When address output to external memory operation is
selected:
• No external pull-up resistance is required
• Internal control signals switch the address lines to the
gates of the FET:
• If D=1
• Then:
• Q-bar=0
• T1 ON and T2 OFF
• Thus Pin0.x will produce logic HIGH
• If D=0
• Then:
• Q-bar=1
• T1 OFF and T2 ON
• Thus Pin0.x will produce logic LOW
• After address status is provided on port 0 pins ALE pin
status will change accordingly.
• After ALE again goes low the pins of port 0 are turned
around to be data pins again.
• To read data, internal control logic sets the port pins to
logic -1 (configured as input).
• To write data port latches will supply required logic
states to be written to external memory connected.
29 PORT 1 Circuit
30 PORT 2 Circuit
PORT 3 Circuit
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