NATIONAL INSTITUTE OF TECHNOLOGY CALICUT

Department of Electronics and Communication Engineering

Monsoon 2019

EC6201D DIGITAL INTEGRATED CIRCUIT DESIGN

LAB REPORT

SUBMITTED BY
Reg No Name
M190425EC AKHIL K
M190574EC PRITOM MEDOK
 EXPERIMENT NO:1

QUESTION:
Write Verilog code for 4 bit Ripple Carry Adder. Follow hierarchical structural modelling.

SCHEMATIC:
VERILOG CODE:
module ripple_c_add(s,cout,a,b); //ripple carry adder

output[3:0]s;

output cout;

input [3:0]a,b;

wire w1,w2,w3;

HA HA0(s[0],w1,a[0],b[0]);

FA FA1(s[1],w2,a[1],b[1],w1);

FA FA2(s[2],w3,a[2],b[2],w2);

FA FA3(s[3],cout,a[3],b[3],w3);

endmodule

module tb_ripple_add ; //test bench for ripple carry adder

wire [3:0]s;

wire cout;

reg [3:0]a,b;

ripple_c_add GHY(s,cout,a,b);

initial

begin

for(a=4'd1;a<4'd15;a=a+1'b1)

begin

for(b=4'd1;b<4'd7;b=b+1'b1)

#10;

end
 end

endmodule

module HA(sum,cy,a,b); //half adder

output sum,cy;

input a,b;

xor X1(sum,a,b);

and A1(cy,a,b);

endmodule

module FA(sum,cy,a,b,cin); //full adder using half adder

output sum,cy;

input a,b,cin;

wire w1,w2,w3;

HA HA1(w1,w2,a,b);

HA HA2(sum,w3,w1,cin);

or O1(cy,w2,w3);

endmodule

RESULTS:
SIMULATION WAVEFORM:
SYNTHESIS REPORT:

CONCLUSION:
Structural Verilog code for 4 bit ripple carry adder is written and simulated using Xilinx vivado.

EXPERIMENT NO:2

QUESTION:
Design a Multi-function gate which can work as a two input (A, B) one output (F) logic gate
based on the control values placed on two other inputs X and Y. Control input values and the
corresponding function is given in the table below. After obtaining the schematic, write
structural level verilog code for it.
SCHEMATIC:
VERILOG CODE:
module mux_41_struct(z,s1,s0,a,b,c,d); //4 to 1 multiplexer

output z;
input s1,s0,a,b,c,d;

wire w1,w2,w3,w4,w5,w6;

not N1(w1,s1);

not N2(w2,s0);

and A1(w3,w1,w2,a);

and A2(w4,w1,s0,b);

and A3(w5,w2,s1,c);

and A4(w6,s1,s0,d);

or O1(z,w3,w4,w5,w6);

endmodule

module struct_ckt(F,A,B,X,Y); // code for logic circuit

output F;

input A,B,X,Y;

wire w1,w2,w3,w4;

and A1(w1,A,B);

or O1(w2,A,B);

nor NO1(w3,A,B);

nand NA1(w4,A,B);

mux_41_struct GHT(F,Y,X,w1,w2,w3,w4);

endmodule

module tb_ckt ; //testbench

reg a,b,x,y;

wire f;

struct_ckt FGT(f,a,b,y,x);

initial

begin
 x=0;y=0;setup;

#10 x=0;y=1;setup;

#10 x=1;y=0;setup;

#10 x=1;y=1;setup;

#10;

end

task setup;

begin

a=0;b=0;

#10 a=0;b=1;

#10 a=1;b=0;

#10 a=1;b=1;

end

endtask

endmodule

RESULTS:
WAVEFORM:

SYNTHESIS REPORT:
CONCLUSION:
A multifunction gate is realized using verilog and simulated using Xilinx vivado .

EXPERIMENT NO : 3

QUESTION:
Write Verilog code for 4 X 1 Multiplexer using conditional operator .

TRUTH TABLE:
VERILOG CODE:
module mux_41_data(y,s1,s0,a,b,c,d); //4X1 Multiplexer Verilog code
output y;
input s1,s0,a,b,c,d;
assign y=(s1==0)?((s0==0)?a:b):((s0==0)?c:d);
endmodule

module tb_mux41; //testbench code

reg s1,s0,a,b,c,d;
wire y;
mux_41_data GHY(y,s1,s0,a,b,c,d);
initial
begin
s1=0;s0=0;setup;
#10 s1=0;s0=1;setup;
#10 s1=1;s0=0;setup;
#10 s0=1;s1=1;setup;
end
 task setup;
begin
a=0;b=0;c=0;d=0;
#10 a=1;
#10 a=0;b=1;
#10 c=1;b=0;
#10 c=0;d=1;
end
endtask
endmodule

RESULTS:

SIMULATED WAVEFORM:

SYNTHESIS REPORT:
CONCLUSION:
4 X 1 Multiplexer using conditional operator is realized using verilog and simulated using Xilinx
vivado.

EXPERIMENT NO:4

QUESTION:
Write Verilog code for 8 X 1 mux using 2 X 1 Mux in gate level.

SCHEMATIC:

TRUTH TABLE:
VERILOG CODE:
module mux_21_struct(y,sel,a,b); //Verilog code for 2X1 multiplexer
output y;
input sel,a,b;
wire w1,w2,w3;
and A1(w2,w1,a);
and A2(w3,sel,b);
or O1(y,w2,w3);
not N1(w1,sel);
endmodule

module mux_81_struct(y,s2,s1,s0,a,b,c,d,e,f,g,h); //8X1 multiplexer

 output y;
input s2,s1,s0,a,b,c,d,e,f,g,h;
wire w1,w2,w3,w4,w5,w6;

mux_21_struct M1(w1,s0,a,b);
mux_21_struct M2(w2,s0,c,d);
mux_21_struct M3(w3,s0,e,f);
mux_21_struct M4(w4,s0,g,h);
mux_21_struct M5(w5,s1,w1,w2);
mux_21_struct M6(w6,s1,w3,w4);
mux_21_struct M7(y,s2,w5,w6);
endmodule

module tb_mux81 ; //Test bench code

wire y;
reg s2,s1,s0,a,b,c,d,e,f,g,h;
mux_81_struct FGT (y,s2,s1,s0,a,b,c,d,e,f,g,h);
initial
begin
s2=0;s1=0;s0=0;setup;
s2=0;s1=0;s0=1;setup;
s2=0;s1=1;s0=0;setup;
s2=0;s1=1;s0=1;setup;
s2=1;s1=0;s0=0;setup;
s2=1;s1=0;s0=1;setup;
s2=1;s1=1;s0=0;setup;
s2=1;s1=1;s0=1;setup;
end
task setup;
begin
a=0;b=0;c=0;d=0;e=0;f=0;g=0;h=0;
#10 a=1;
#10 a=0;b=1;
#10 c=1;b=0;
#10 c=0;d=1;
#10 d=0;e=1;
#10 e=0;f=1;
#10 f=0;g=1;
#10 g=0;h=1;
#10 h=0;
end
endtask
endmodule

RESULTS:

SIMULATED WAVEFORM:
SYNTHESIS REPORT:

CONCLUSION:

8 X 1 mux using 2 X 1 Mux in gate level is realized using verilog and simulated using Xilinx
vivado.

EXPERIMENT NO:5
QUESTION:
Design a 4 to 2 Encoder using structural level Verilog coding.

SCHEMATIC:

VERILOG CODE:

module encoder4_2(y0,y1,I0,I1,I2,I3);

output y0,y1;

input I0,I1,I2,I3;

or O1(y0,I3,I1);

or O2(y1,I3,I2);

endmodule
 module tb_encoder ;

wire y0,y1;

reg I0,I1,I2,I3;

encoder4_2 XRT(y0,y1,I0,I1,I2,I3);

initial

begin

I0=0;I1=0;I2=0;I3=0;

#10 I0=1;

#10 I0=0;I1=1;

#10 I1=0;I2=1;

#10 I2=0;I3=1;

#10 I3=0;

end

endmodule

RESULTS:

SIMULATED WAVEFORM:
SYNTHESIS REPORT:

CONCLUSION:
4 to 2 Encoder using Structure level is realized using verilog and simulated using Xilinx
vivado.

EXPERIMENT NO:6

QUESTION:

Write a Verilog code for 1 X 4 Demultiplexer in structural level coding.

SCHEMATIC:
VERILOG CODE:

module demux_14_struct(y,in,s);

output [3:0]y;

input in;

input [0:1]s;

wire w1,w2;
 not N1(w1,s[1]);

not N2(w2,s[0]);

and A1(y[0],w1,w2,in);

and A2(y[1],w1,s[0],in);

and A3(y[2],w2,s[1],in);

and A4(y[3],s[1],s[0],in);

endmodule

module tb_demux ;

wire [3:0]y;

reg in;

reg [0:1]s;

demux_14_struct JKL(y,in,s);

initial

begin

in=1;s[0]=0;s[1]=0;

#10 s[0]=1;s[1]=0;

#10 s[0]=0;s[1]=1;

#10 s[0]=1;s[1]=1;

#10 s[0]=0;s[1]=0;in=0;

end

endmodule

RESULTS:

SIMULATED WAVEFORM:
SYNTHESIS REPORT:

CONCLUSION:

1 X 4 Demultiplexer in structural level coding is realized using verilog and simulated using
Xilinx vivado.
 EXPERIMENT NO:7

QUESTION:

Write a gate level Verilog code for 2 X 4 Decoder

SCHEMATIC:
VERILOG CODE:

module decoder_24_struct(D,A);
 output [3:0]D;

input [1:0]A;

wire w1,w2;

not N1(w1,A[1]);

not N2(w2,A[0]);

and A1(D[3],A[1],A[0]);

and A2(D[2],A[1],w2);

and A3(D[1],w1,A[0]);

and A4(D[0],w1,w2);

endmodule

module tb_decoder ;

wire [3:0]D;

reg [1:0]A;

decoder_24_struct HJKL(D,A);

initial

begin

A[1]=0;A[0]=0;

#10 A[1]=0;A[0]=1;

#10 A[1]=1;A[0]=0;

#10 A[1]=1;A[0]=1;

#10 A[1]=0;A[0]=0;

end

endmodule

RESULTS :

SIMULATED WAVEFORM :
SYNTHESIS REPORT:

CONCLUSION:
2x4 Decoder gate level code is realized using verilog and simulated using Xilinx vivado.
 EXPERIMENT NO:8

QUESTION:
Write a structural level Verilog code for D-Flip flop.

SCHEMATIC:
VERILOG CODE:

module d_ff_struct(q,qbar,D,clk,rst);

output q,qbar;

input D,clk,rst;

wire w1,w2,w3,w4;

nand NA1(w1,w4,w2);

nand NA2(w2,w1,clk,rst);

nand NA3(w3,w2,clk,w4);

nand NA4(w4,w3,D,rst);

nand NA5(q,w2,qbar);

nand NA6(qbar,rst,w3,q);

endmodule

module tb_d_ff ;

wire q,qbar;

reg D,clk,rst;

d_ff_struct HJK(q,qbar,D,clk,rst);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end
 initial

begin

D=1;rst=0;#7 rst=1;

#12 D=1;#10 D=0;

#10 D=1;#10 D=0;

#7 D=1;#10 D=0;

end

endmodule

RESULTS :

SIMULATED WAVEFORM :

SYNTHESIS REPORT:
CONCLUSION:
D-Flip flop structure level code is realized using verilog and simulated using Xilinx vivado.

EXPERIMENT NO:9

QUESTION:

Write a gate level Verilog coding for J-K Flip flop with synchronous reset signal

SCHEMATIC:
VERILOG CODE:

module jk_ff_struct(q,qbar,clk,j,k,clr);

output q,qbar;

input clk,j,k,clr;

wire w1,w2,w3,w4,w5,w6;

nand NA1(w1,qbar,j,clr,clk);

nand NA2(w4,q,k,clk);

nand NA3(w2,w1,w5);
nand NA4(w5,w4,w2,clr);

nand NA5(w3,w2,w7);

nand NA6(w6,w5,w7);

nand NA7(q,w3,qbar);

nand NA8(qbar,w6,q,clr);

not N1(w7,clk);

endmodule

module tb_jk_ff ;

reg clk,j,k,clr;

wire q,qbar;

jk_ff_struct FGT(q,qbar,clk,j,k,clr);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

#7 clr=0;#10 j=0;k=0;

#10 clr=1;

#10 j=1;k=0;

#10 j=0;k=1;

#10 j=1;k=1;

#20 j=0;k=0;

end

endmodule
RESULTS :

SIMULATED WAVEFORM :

SYNTHESIS REPORT:

CONCLUSION:
J-K Flip flop with synchronous reset signal is realized using verilog and simulated using Xilinx
vivado.

EXPERIMENT NO:10

QUESTION:
Write a gate level Verilog code for Ring Counter using J-K Flip flop.

SCHEMATIC:
VERILOG CODE:
module ringcounter(Q,clk,clr);

output [3:0]Q;

input clk,clr;

wire w1,w2,w3,w4,w5;

jk_ff_struct JK1(Q[0],w1,clk,w4,w5,clr);

jk_ff_struct JK2(Q[1],w2,clk,Q[0],w1,clr);

jk_ff_struct JK3(Q[2],w3,clk,Q[1],w2,clr);

jk_ff_struct JK4(Q[3],w6,clk,Q[2],w3,clr);

nor NO1(w4,Q[0],Q[1],Q[2]);

not N1(w5,w4);

endmodule

module jk_ff_struct(q,qbar,clk,j,k,clr);

output q,qbar;

input clk,j,k,clr;

wire w1,w2,w3,w4,w5,w6;

nand NA1(w1,qbar,j,clr,clk);

nand NA2(w4,q,k,clk);

nand NA3(w2,w1,w5);

nand NA4(w5,w4,w2,clr);

nand NA5(w3,w2,w7);

nand NA6(w6,w5,w7);

nand NA7(q,w3,qbar);

nand NA8(qbar,w6,q,clr);
 not N1(w7,clk);

endmodule

module tb_ringcounter ;

wire[3:0]q;

reg clk,clr;

ringcounter FGT(q,clk,clr);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

clr=0;

#15 clr=1;

end

endmodule

RESULTS :

SIMULATED WAVEFORM :
SYNTHESIS REPORT:

CONCLUSION:
Ring Counter using J-K Flip flop is realized using verilog and simulated using Xilinx vivado.

EXPERIMENT NO:11

QUESTION:

Write a gate level Verilog code for Johnsons counter using D- Flip flop

SCHEMATIC:
VERILOG CODE:
module johnsoncounter(Q,clk,rst);
output [3:0] Q;
input clk,rst;
wire w1,w2,w3,w4;
d_ff_struct D1(Q[0],w2,w1,clk,rst);
d_ff_struct D2(Q[1],w3,Q[0],clk,rst);
d_ff_struct D3(Q[2],w4,Q[1],clk,rst);
d_ff_struct D4(Q[3],w1,Q[2],clk,rst);
endmodule

module tb_johnson ;
reg clk,rst;
 wire [3:0]Q;
johnsoncounter HJH(Q,clk,rst);
always
begin
clk=1'b0;
#5 clk=1'b1;
#5;
end
initial
begin
rst=1'b0;#10 rst=1'b1;
end
endmodule

module d_ff_struct(q,qbar,D,clk,rst);
output q,qbar;
input D,clk,rst;
wire w1,w2,w3,w4;
nand NA1(w1,w4,w2);
nand NA2(w2,w1,clk,rst);
nand NA3(w3,w2,clk,w4);
nand NA4(w4,w3,D,rst);
nand NA5(q,w2,qbar);
nand NA6(qbar,rst,w3,q)

RESULTS :

SIMULATED WAVEFORM :

SYNTHESIS REPORT:
CONCLUSION:

Johnsons counter using D- Flip flop is realized using verilog and simulated using Xilinx vivado.
 EXPERIMENT NO:12

QUESTION:
Write a 4-bit Verilog code for synchronous Down counter.

SCHEMATIC:

VERILOG CODE:

module syn_downcounter(Q,clk,rst);

output reg [3:0] Q;

input clk,rst;
always@(posedge clk)

begin

if(rst==1'b1)

Q<=4'b1111;

else

Q<=Q-1'b1;

end

endmodule

module tb_downcounter ;

wire [3:0]Q;

reg clk,rst;

syn_downcounter FGT(Q,clk,rst);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

rst=1'b1;

#7 rst=1'b0;

end

endmodule
RESULTS :

SIMULATED WAVEFORM :

SYNTHESIS REPORT:

CONCLUSION:
4-bit Verilog code for synchronous Down counter is realized using verilog and simulated using
Xilinx vivado.

EXPERIMENT NO:13

QUESTION:
Write a structural level Verilog coding for S-R flip flop.

SCHEMATIC:
VERILOG CODE:
module sr_ff_struct(q,qbar,clk,S,R,rst);

output q,qbar;

input clk,S,R,rst;

wire w1,w2,w3,W4,W5,W6,W7,W8;

nand NA1(w3,S,w1,w2);

nand NA2(w4,R,w2);

nand NA3(w5,w6,w3);

nand NA4(w6,w1,w5,w4);

nand NA5(w7,w5,clk);

nand NA6(w8,w6,clk);

nand NA7(q,w7,qbar);

nand NA8(qbar,w8,w1,q);

not N1(w1,rst);
 not N2(w2,clk);

endmodule

module tb_sr_ff ; //TEST BENCH

reg clk,s,r,rst;

wire q,qbar;

sr_ff_struct FF(q,qbar,clk,s,r,rst);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

rst=1'b0;#10 rst=1'b1;#10 rst=1'b0;

s=1;r=0;

#10 s=0;r=1;

#10 s=1;r=0;

#10 s=0;r=1;

end

endmodule

RESULTS :

SIMULATED WAVEFORM :
SYNTHESIS REPORT:

CONCLUSION:

Verilog coding for S-R flip flop using structural level is realized using verilog and simulated using
Xilinx vivado.
 EXPERIMENT NO:14

QUESTION:
Write a Verilog code for J-K flip flop using S-R flip flop instantiation

SCHEMATIC:
VERILOG CODE:
module jk_using_sr(q,qbar,j,k,clk,rst);

output q,qbar;

input j,k,clk,rst;

wire w1,w2;

and A1(w1,j,qbar);

and A2(w2,k,q);

sr_ff_struct sr(q,qbar,clk,w1,w2,rst);

endmodule

module tb_jk_sr;

wire q,qbar;

reg j,k,clk,rst;

jk_using_sr jk1(q,qbar,j,k,clk,rst);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

rst=1'b1;#10 rst=1'b0;

j=0;k=0;

#10 j=1;k=0;

#10 j=0;k=1;
 #10 j=1;

#50 j=0;

end

endmodule

module sr_ff_struct(q,qbar,clk,S,R,rst);

output q,qbar;

input clk,S,R,rst;

wire w1,w2,w3,W4,W5,W6,W7,W8;

nand NA1(w3,S,w1,w2);

nand NA2(w4,R,w2);

nand NA3(w5,w6,w3);

nand NA4(w6,w1,w5,w4);

nand NA5(w7,w5,clk);

nand NA6(w8,w6,clk);

nand NA7(q,w7,qbar);

nand NA8(qbar,w8,w1,q);

not N1(w1,rst);

not N2(w2,clk);

endmodule

RESULTS :

SIMULATED WAVEFORM :
SYNTHESIS REPORT:

CONCLUSION:

J-K flip flop using S-R flip flop instantiation is realized using verilog and simulated using Xilinx
vivado.

EXPERIMENT NO:15

QUESTION:
Write a Structural level Verilog coding for 4-bit Shift Register using D- flip flop.

SCHEMATIC:
VERILOG CODE:
module shiftreg(q,serial,clk,rst);

output[3:0]q;

input serial,clk,rst;

wire w1,w2,w3,w4;

d_ff_struct DFF1(q[0],w1,serial,clk,rst);

d_ff_struct DFF2(q[1],w2,q[0],clk,rst);
d_ff_struct DFF3(q[2],w3,q[1],clk,rst);

d_ff_struct DFF4(q[3],w4,q[2],clk,rst);

endmodule

module tb_shiftreg ;

wire[3:0]q;

reg serial,clk,rst;

shiftreg FGT(q,serial,clk,rst);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

rst=1'b0;#10 rst=1'b1;serial=1;

#8 serial=0;#6 serial=1;#15 serial=0;

#20 serial=1;

end

endmodule

module d_ff_struct(q,qbar,D,clk,rst); // D flipflop

output q,qbar;

input D,clk,rst;

wire w1,w2,w3,w4;

nand NA1(w1,w4,w2);

nand NA2(w2,w1,clk,rst);

nand NA3(w3,w2,clk,w4);
 nand NA4(w4,w3,D,rst);

nand NA5(q,w2,qbar);

nand NA6(qbar,rst,w3,q);

endmodule

RESULTS:

SIMULATED WAVEFORM :

SYNTHESIS REPORT:

CONCLUSION:
4-bit Shift Register using D- flip flop using structure level is realized using verilog and simulated
using Xilinx vivado.

EXPERIMENT NO:16

QUESTION:
Write a gate level Verilog code for Modulo-10 synchronous up and down counter

SCHEMATIC:

VERILOG CODE:
module up_down_mod10(q,m,clk,rst);

output[3:0]q;
input m,clk,rst;

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18;

jk_ff_struct JK1(q[0],w1,clk,1'b1,1'b1,rst);

jk_ff_struct JK2(q[1],w2,clk,w10,w10,rst);

jk_ff_struct JK3(q[2],w3,clk,w14,w14,rst);

jk_ff_struct JK4(q[3],w4,clk,w18,w18,rst);

and A1(w6,q[3],w1,w5);

and A2(w7,q[0],w4,m);

and A3(w8,q[1],w1,w5);

and A4(w9,q[2],w1,w5);

and A5(w11,q[2],w2,w5,w1);

and A6(w12,q[3],w1,w5);

and A7(w13,q[1],q[0],m);

and A8(w15,w3,w2,w1,w5);

and A9(w16,q[3],q[0],m);

and A10(w17,q[2],q[1],q[0],m);

or O1(w10,w6,w7,w8,w9);

or O2(w14,w11,w12,w13);

or O3(w18,w16,w17,w15);

not N1(w5,m);

endmodule

module tb_up_down ; //TEST BENCH

wire [3:0]q;

reg m,clk,rst;

up_down_mod10 GHY(q,m,clk,rst);

always
 begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

rst=1'b0;#10 rst=1'b1; m=1'b1;

#30 m=1'b0;#50 m=1'b1;

end

endmodule

module jk_ff_struct(q,qbar,clk,j,k,clr);

output q,qbar;

input clk,j,k,clr;

wire w1,w2,w3,w4,w5,w6;

nand NA1(w1,qbar,j,clr,clk);

nand NA2(w4,q,k,clk);

nand NA3(w2,w1,w5);

nand NA4(w5,w4,w2,clr);

nand NA5(w3,w2,w7);

nand NA6(w6,w5,w7);

nand NA7(q,w3,qbar);

nand NA8(qbar,w6,q,clr);

not N1(w7,clk);

endmodule

RESULTS :

SIMULATED WAVEFORM :
SYNTHESIS REPORT:

CONCLUSION:

Modulo-10 synchronous up and down counter Flip flop is realized using verilog and simulated
using Xilinx vivado.
 EXPERIMENT NO:17

QUESTION:
Write a Verilog code for the up/down counter with a control input. If the control input is 1 then the
circuit works as up counter and if the control input is 0 then the circuit works as a down counter.

SCHEMATIC:
VERILOG CODE:
module up_down_counter(q,ctrl,clk,rst);

output reg [3:0]q;

input ctrl,clk,rst;

always@(posedge clk)

begin

if(rst==1)

q<=4'b0000;

else if(ctrl==1)

q<=q+1'b1;

else

q<=q-1'b1;

end

endmodule

module tb_counter ;

wire [3:0]q;

reg ctrl,clk,rst;

up_down_counter HJK (q,ctrl,clk,rst);

always

begin

clk=1'b0;
 #5 clk=1'b1;

#5;

end

initial

begin

ctrl=0;rst=1;

#20 rst=0;

#35 ctrl=0;

#20 ctrl=1;

end

endmodule

RESULTS :

SIMULATED WAVEFORM :

SYNTHESIS REPORT:
CONCLUSION:

Up/Down counter with a control input. If the control input is 1 then the circuit works as up counter
and if the control input is 0 then the circuit works as a down counter is realize using Verilog and
simulated using vivado.

EXPERIMENT NO:18
QUESTION:
Write a behavioral Verilog code for a Universal shift register controlled by S1 S0 with asynchronous
reset signal

S1 S0 ACTION
1 1 Parallel load
0 0 Hold
1 1 Shift right
1 0 Shift left

SCHEMATIC:

VERILOG CODE:

module universal_shift_reg(q,sel,rst,in,clk,serial);
output reg [3:0]q;
input [1:0]sel;
input rst,serial,clk;
input [3:0]in;
always@(posedge clk)
begin
if(rst==1)
q<=4'b0000;
case(sel)
2'b00:begin
q<=q;
end
 2'b01:begin
q[0]<=serial;
q[1]<=q[0];
q[2]<=q[1];
q[3]<=q[2];
end
2'b10:begin
q[3]<=serial;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
2'b11: q<=in;
endcase
end
endmodule

module tb_universal_shift; //TEST BENCH

wire[3:0]q;
reg[1:0]sel;
reg[3:0]in;
reg rst,serial,clk;
universal_shift_reg GHY(q,sel,rst,in,clk,serial);
always
begin
clk=1'b0;
#5 clk=1'b1;
#5;
end
initial
begin
rst=1'b1;serial=0;in=4'b0000;#5 rst=1'b0;
#10 sel=2'b11;in=4'b1010;
#15 sel=2'b00;#10 sel=2'b01;serial=1;
#10 serial=0;
#5 sel=2'b10;serial=1;#10 serial=0;
#5 sel=2'b11;in=4'b1111;
#10 sel=2'b01;
end
endmodule

RESULTS :

SIMULATED WAVEFORM :
SYNTHESIS REPORT:

CONCLUSION:

Universal shift register controlled by S1 S0 with asynchronous reset signal is realized using Verilog
and simulated using Xilinx vivado.
 EXPERIMENT NO:19

QUESTION:
Design a parallel to serial data converter (16-bit to 8-bit) using the waveform below. Write down the
Verilog code for your design.

SCHEMATIC:
VERILOG CODE:

module par2serial(dataout,datain,clk,rst);

output reg [7:0]dataout;

input [15:0]datain;

input clk,rst;

reg [15:0]temp;

reg en=1;

integer count=0;

always@(negedge clk)

temp<=datain;

always@(posedge clk)

begin

en<=~en;

if(rst==1)

dataout<=8'b0;

else

begin

dataout<=temp[15:8];

if(en==0)

dataout<=temp[7:0];

end

end
endmodule

module tb_par2serial ;

wire[7:0]dataout;

reg [15:0]datain;

reg clk,rst;

par2serial DRT(dataout,datain,clk,rst);

always

begin

clk=1'b0;

#5 clk=1'b1;

#5;

end

initial

begin

rst=1;

datain=16'h3524;#20 rst=0; datain=16'h5e81;

#20datain=16'h1609;#20 datain=16'h5663;

#20 datain=16'h7b0d;#20 datain=16'h000;

end

endmodule #5 clk=1'b1;

#5;

end

initial

begin

rst=1;

datain=16'h3524;#20 rst=0; datain=16'h5e81;

#20datain=16'h1609;#20 datain=16'h5663;
 #20 datain=16'h7b0d;#20 datain=16'h000;

end

endmodule

RESULTS :
SIMULATED WAVEFORM :

SYNTHESIS REPORT:
CONCLUSION:

A parallel to serial data converter (16-bit to 8-bit) using the waveform is realized using verilog and
simulated using Xilinx vivado.

EXPERIMENT NO:20

QUESTION:
The following block implements an 8-bit wide register from DFFs. All flops are driven by a
common clock and have a common reset rst. An input mux allows new data to be loaded into the
register when ld is high; otherwise, the old data is recirculated. Write two different code one
structural modelling and another behavioral modelling.
SCHEMATIC:
VERILOG CODE:

STRUCUTURAL MODEL:

module shiftreg_8bit_struct(q,din,id,rst,clk);
output [7:0]q;
input[7:0]din;
input id,rst,clk;
wire [7:0] w1;
mux_21_8bit JKL(w1,din,q,id);
shift8bit GHY(q,w1,rst,clk);
endmodule

module mux_21_8bit(q_nxt,din,q,id);
output [7:0]q_nxt;
input [7:0] din,q;
input id;
mux_21_struct MUX1(q_nxt[0],id,q[0],din[0]);
mux_21_struct MUX2(q_nxt[1],id,q[1],din[1]);
mux_21_struct MUX3(q_nxt[2],id,q[2],din[2]);
mux_21_struct MUX4(q_nxt[3],id,q[3],din[3]);
mux_21_struct MUX5(q_nxt[4],id,q[4],din[4]);
mux_21_struct MUX6(q_nxt[5],id,q[5],din[5]);
mux_21_struct MUX7(q_nxt[6],id,q[6],din[6]);
mux_21_struct MUX8(q_nxt[7],id,q[7],din[7]);
endmodule

module shift8bit(q,q_nxt,rst,clk);
output [7:0]q;
input [7:0]q_nxt;
input rst,clk;
d_ff_struct DFF1(q[0],,q_nxt[0],clk,rst);
d_ff_struct DFF2(q[1],,q_nxt[1],clk,rst);
d_ff_struct DFF3(q[2],,q_nxt[2],clk,rst);
d_ff_struct DFF4(q[3],,q_nxt[3],clk,rst);
d_ff_struct DFF5(q[4],,q_nxt[4],clk,rst);
d_ff_struct DFF6(q[5],,q_nxt[5],clk,rst);
d_ff_struct DFF7(q[6],,q_nxt[6],clk,rst);
d_ff_struct DFF8(q[7],,q_nxt[7],clk,rst);
endmodule

module d_ff_struct(q,qbar,D,clk,rst);
output q,qbar;
input D,clk,rst;
wire w1,w2,w3,w4;
nand NA1(w1,w4,w2);
nand NA2(w2,w1,clk,rst);
nand NA3(w3,w2,clk,w4);
nand NA4(w4,w3,D,rst);
 nand NA5(q,w2,qbar);
nand NA6(qbar,rst,w3,q);
endmodule

module mux_21_struct(y,sel,a,b);
output y;
input sel,a,b;
wire w1,w2,w3;
and A1(w2,w1,a);
and A2(w3,sel,b);
or O1(y,w2,w3);
endmodule

module tb_shiftreg8bit ; //TEST BENCH

wire [7:0]q;
reg [7:0]din;
reg id,clk,rst;
shiftreg_8bit_struct GHY(q,din,id,rst,clk);
always
begin
clk=1'b0;
#5 clk=1'b1;
#5;
end
initial
begin
rst=1'b0;#7rst=1'b1;id=1;
din=8'h34;#10 din=8'hff;#10 id=0;din=8'h1e;
#7 din=8'h99;
#20 id=1;din=8'h55;
end
endmodule

BEHAVIORAL MODEL:

module reg_8bit_beh(q,din,id,rst,clk );
output reg [7:0]q;
input[7:0]din;
input id,rst,clk;
always@(posedge clk)
begin
if(rst==1'b1)
q<=8'b0;
else if(id==1'b1)
q<=din;
else
q<=q;
end
endmodule
 module tb_reg8bit ; //TEST BENCH
wire[7:0]q;
reg [7:0]din;
reg id,rst,clk;
reg_8bit_beh GHY(q,din,id,rst,clk);
always
begin
clk=1'b0;
#5 clk=1'b1;
#5;
end
initial
begin
rst=1'b1;#10 rst=1'b0;
id=1;din=8'h23;#7 din=8'hff;
#10 id=0;#15 id=1;din=8'h33;
#7 din=8'h24;#7 din=8'h89;#7 din=8'ha4;
#10 id=0;din=8'h00;
end
endmodule

RESULTS :

STRUCTURAL MODEL:

SIMULATED WAVEFORM :

SYNTHESIS REPORT:
BEHAVIORAL MODEL:
WAVEFORM:
SYNTHESIS REPORT:

CONCLUSION:

Eight bit register using D flip flop is realized using verilog and simulated using Xilinx Vivado.