TYPE RB GENERAL PURPOSE CORE MEMORIES Offering a combination of features not previously considered feasible in any but custom units, TYPE RB core memories in- corporate such useful characteristies as high speed operation long term, reliability...wide range of capacities...low cost random access, sequential load, sequential unload, or any combination desired. CHARACTERISTICS CAPACITY 198 to 1024 words 4 to 94 bits per word Langer capacities by multiple units OPERATING MODES Sequential load and unload Random access load and unload Random access or sequential access memory with clear/write and read/restore eyeles. Operations can be intermixed in any manner desired without loss of speed SPEED Load or unload a word (all bits in parallel) — Complete memory cycle — 8 microseconds INPUT AND OUTPUT SIGNALS A wide range of reference levels and signal amplitudes is available to assure compatibility with both tube: and. tra sistor cireuits. Input signals may be either polarity and mi be levels or pulses. Output signals are levels, DIMENSIONS Depends on word length. Up to 12 bits per word — 19 x 10% x 16; 14 to 24 bits — 19 x 15% x 16, POWER SUPPLY Self-contained ~ requires 115 volts, 48-63 eps, less than 250 watts ENVIRONMENT Operates over the temperature range from 0°C to 70°C. under humidity conditions to 90f. TELEMETER MAGNETICS Inc. P.O. BOX 329, CULVER CITY, CALIFORNIA ‘Offices ond plant: 9937 JEFFERSON BOULEVARD, CULVER CITY, CALIFORNIA loners in Development and Manotctre of Core Memory Produce In addition to TYPE RB memories, Telemeter Magnetics manufactures a wide range of solid state core memories having cycle times from 24 to 1 microsecond in capacities up to a million bits or more, For buffer storage applications, TMI offers more than 40 models to choose from. The Components Divi sion can deliver from stock a variety of ferrite storage and logic cores, arays, and memory stacks TYPICAL APPLICATIONS FOR TYPE RB GENERAL PURPOSE CORE MEMORIES TYPE RB Memories were de- signed for use in data systems requiring relatively small, fast ‘memories compatible with log- ‘cal control in 100-200 ke region. These versatile units are appli cable to systems designed for ‘automatic control 2 data editing and format revision ‘multiplexing data from several + analog-to-digital conversion and data recording ‘small digital computers 2k complex data processing ‘automatic checkout programming 2 process control 4 machine tool control weapons fire control % digital data communication 1k meteor burst data transmission 2 nuclear energy analysis and {nstramentation pulse height analysis Specification | DF-115.1SPECIFICATIONS FOR TYPE RB GENERAL PURPOSE CORE MEMORIES STORAGE CAPACITY 128 9 1024 words por unit 49 Bits per wor in two-bit increments Lange capeies by combing units ‘OPERATING SPEED ‘Asyichrongus to 200 ke loading or uploading for buller operse thon to 188 ke for teud-estore or eleaerwite memory cycles ENVIRONMENT i ‘Operating ambient teraperture — 0° to 50°C, Wil withstan occasional vexcusons ta" T0°G. Storage conditions ~ from “50°C to 70°C: Relative humidity ~ 02 to BOE All materials used are non-nutrient to fungi and are protected 2yalntcoreenon, Moderate vibration or shock wal aot affect ‘eration. POWER REQUIREMENTS Sllontaved power supply inciting selon fo al nt walagey operstes from 100 v0 190 vel, sige phase $a pele tha 250 wats ar ‘MOUNTING Desi for monoting ina standard hiner rack Sup sel "rth Western Electric notching except on spec order "height “108 inches for all modes up to 12-bit ‘word length; 1 Inches for 14 to 24bit models. FINISH Supplied painted semiglss. gray, baked enamel, Federal StEiea No. is, Code 28831" lhe pel fey ave cn seca order WEIGHT ‘From 40 to 85 Tb net and from 60 to 120 Th shipping INPUT AND OUTPUT SIGNALS ‘A selection of input and omtpit level i offered to provide cmmpatiily with other equipment. The spat voltage level ‘gins estalhed hy th eat vl cote, 2 shown by ous rtiomintine# — y o | -6 Ben +2 to —8 3 File] asian ees |e ee capers mrearei| Ts s2[ 0 | +8044 +14 to 2 roe 4 These linits are absolute values, Output voltages are nominal. The following design toler ‘ances should be applied. Noetinal “Tolerance ° | -0ae -04 ea esa | 010-07 +12, aaa +04 to 1.0 Eis +10 to —1.0 uma current vaslbl fo lth dreton fm any Teel at least 5 ma. Mice or fall ime: depends on loading and can {tary from 0105 10°03 microsecond under normal Ind vari ADDRESS REGISTER ‘The dies register const of 7 to 10 bis according to number of words capacty MEMORY REGISTER The length of the memory register is determined by the word length chosen, Te varies In tworbit increments from 4 e024 bits COUNT NETWORK Optionally available for sequential addressing to a maximum P1021 ord in binary or 400 swords BED. TRANSPOSE REGISTER A register of the sume length as the address register may bé Incorporated to permit storage of a previows addres. during ther «sequential or & random operation SIGNAL LINES ‘There is one wire for each of the following except as indicated. 1. AR addres input and output (4 wices per bit) MR — info input and output (4 wires per bit) 13 —load syne ULS — unload syne MR clear ~ memory register clear AM clear —addrest register clear (0S — operating state (2 wires) CLEAN — bff clear MO ~ memory opera #10. AR strobe — address register "11, MR steohe — memory register * Used omly in models with d-e information levels to AR and MR. ‘The following input signal lines of one wite each are available ‘when a count network or transpose register i used. 12. F forward 13. R—reverse 14. C—eount 15. T—transpore INPUT POLARITY AND IMPEDANCE ‘The d-e currents om each line at the input voltage which stresponds to nominal ouput volage are Positive pulses or double-ended levels — 4 ma Negative pulses or double-ended levels — 1 ma Positive or negative-going single-ended level — 5 ma ‘When the input voltage fs postive with respeet to the memo reference potential, inpat (re enrrent is nero, At other input ‘oltages, current ie from more positive potential into the Input lie In addition to the d-e current, the nie prevents 8 Capacitive input load of 0.0002 microfarad, INPUT POLARITY SELECTION Positive or negative-going pulses may be used for any of the following pair of Functions = J 1. Load Syne and Unload Syne 2. AN Strobe and AR Clear 5. Info Strobe and MR Clear 4. Count and Transpose Positive or negative levels may be used for—~ Forwaud and Reverse Positive level and positive pulse or negative level and negative pile may be wed for aa ‘Memory Operation and Clear Postive pulse, negative pulse, double-ended level, or single tended level may’ be used for “Memory Register and Address RegisterOPERATION TYPE RB general purpose memories offer several operat- ing modes to provide unprecedented versatility and flexi. bility. These units may be operated as random access memories, sequential access buffers, or any combination of both. WRITE OPERATION (Loading) AAs shown by Diagram A, veriting in the memory inthe random aceess mode occurs upon receipt of address signals, the address and information strobe signals, a load sync signal, and the information levels, The operation may be repeated every 5 ‘microseconds, To write in the sequential mode, @ count oF transpose signal is transmitted instead of the address and address strobe signals. The address register is then increased or decreased by one according to the control information, Note ‘that the loaded information s available within about 1,5 mlero- seconds for external checking of control purpose. READ OPERATION (Unloading) Diagram B shows the reading operation, which is similar to writing except that no information i leaded into the amit, Note ‘that unloading is a destructive readout which leaves the stor- age address in the proper state fora subsequent load operation. oma se uc nro on ( sve sreoue MEMORY OPERATION Diagram C illustrates memory operation, A clear/write cycle fe tntatedby'a Toad syne signal with the memery operation line enersized, A tead/restre cycle i tiated by a unload ‘yh signal with the memory upertion Ke energie COUNT OPERATION An optional count network may be included with forward or reverse counting selected by one of two do signals, Utlzing ‘logical hall-adder, the counter prepares the next vaiue during the current yele ‘and trinsmite this value to the address register upon receipt of a count signa. ‘The count network can be set to count in any radix from 1 to 16 the lint of the memory capacity in nutaber of words, Tho eount network i organized in four-bit modes, normally set to binary but may be set to BCD, The network tan be set to count as RyxRaxRy, where Ry and Re are 16 or lew excep in 128¢word models when Ry is 8. Ry is 2 in 512-word models find 4 in 1024-word models, ‘TRANSPOSE OPERATION Upon receipt of a transpose signal, the value in the address realate Is transferred via the count network to the transpose register, simultaneously the vale fom the transpose tester Is transferred to the address register. Thus, the values i the ttanspose and the address registers are exchanged, and. the address register values increased or decreased hy one, de- pending upon whether the forward or reverse line i energized, Hf'neither line is energized, values “are unchonged during ‘ransposition SEQUENTIAL OPERATIONS Incorporating the count network and the transpose register permis great variety of format revision functions typical of Many input/output problems, Among these are Sequential Load ~ Sequential Unload, 5 Heures count network ony Charaterti of locks Tock magnetic tape operations Reversible. featar counter permits reading tape backwards 4 Interlaced Load and Unload Uses count twork and. transpose register. Useful. in character-by-charcter magnetic tape operations ‘He Loud nto One Memory Area Tutelaced with Clear/Wr tr Read/ Restore in Ancther Area User count network and transpone rexister. Characteristic af operations performed in conjunction with punched cards, parallel printing, and meteor burst communication, Write Into One Area; Unload from Another Uses count network and transpose register, Punched card reading applications 1 Interlaced Use of Two Memory Areas Uses count network and transpose register. Performs func tions of two independent buffer memories and is applicable tovall types of data processingTIMING PULSES—To operate the TYPE RB at rated speed, pulses must rise within 0.2 microsecond, have a duration of from 05 to 10 microsecond, and fall within 0.4 microsecond. Slower rise times to one microsecond may be used, but the excess time is added to the clear time and the cycle time. ZERO TIME to — The instant when LS or ULS crosses the input reference voltage. END OF CYCLE—Memory operation, 8 microseconds; buffer operation, 5 microseconds after LS or ULS. ADDRESS AND MEMORY SIGNALS Single ended pulses may be used if the register is cleared one microsecond before transfer. The strobe pulse to AR or MR, either in pulse or level form, must occur by t. Levels must have settled within 0.25 microsecond before an MR or AR pulse begins. A strobe pulse must not occur earlier than 0.5 microsecond before end of eycle. COUNT AND TRANSPOSE SIGNALS Same as for AR and MR signals, oreo cutan —sraoee © Lever an ae A PULSE OR LeveL MEMORY OPERATION—This line must be in the selected state by at least t, 0.5 microsecond and maintain this state until t, + 4.0 microseconds, FORWARD, REVERSE—These lines must be settled within 45 microseconds before a count or transpose pulse has crossed the reference voltage and must not be changed until this occurs. ‘CLEAR—This pulse nist occur after the end of cycle and no other pulses may be transmitted to the unit for an additional 25 microseconds. This pulse may not be trans- ted again for 100 microseconds, and there shall be no more than 40 pulses in any 10 millisecond period. OUTPUT ADDRESS INFORMATION These lines settle within 1.5 microsecond after t, until next t,. OUTPUT INFORMATION These lines settle within 4 microseconds after t, and maintain this state until MR is externally changed or until one microsecond after t, if subsequent operation is unload or read. ee 1 1 eal syne, —"4] WON a. 1 MeMonY & pemore READ ames: o Stare TYPE RB BLOCK DIAGRAM