Full adder encoder

module fulladder(a,b,c,s,c1); module

input a,b,c; encoder(y0,y1,y2,y3,y4,y5,y6,y7,a0,a1,a2);
output c1,s; input y0,y1,y2,y3,y4,y5,y6,y7;
reg x,y,z,s,c1;
always@ (a or b or c) output a0,a1,a2;
begin
x=a^b;
s=x^c; or(a2,y7,y6,y5,y4);
y=c&x;
or(a1,y7,y6,y3,y2);
z=a&b;
c1=y|z; or(a0,y7,y5,y3,y1);
end
endmodule
endmodule

Full subtractor Decoder

Module fullsubtractor (a,b,c,diff,borrow); module
decoder(a1,a2,a0,y0,y1,y2,y3,y4,y5,y6,y7);
input a,b,c;
input a1,a2,a0;
output diff,borrow;
output y0,y1,y2,y3,y4,y5,y6,y7;
reg diff,borrow,l,m,a_n,p,t;
wire ao_n;
always@(a or b or c)
wire a1_n;
begin
wire a2_n;
a_n=~a;

p=~l;
not(a0_n,a0);
t=p&c;
not(a1_n,a1);
l=a^b;
not(a2_n,a2);
m=a_n&b;
and(y0,a0_n,a1_n,a2_n);
diff=p^c;
and(y1,a2_n,a1_n,a0);
borrow=t|m;
and(y2,a2_n,a1,a0_n);
end
and(y3,a2_n,a1,a0);
endmodule
and(y4,a2,a1_n,a0_n);
 and(y5,a2,a1_n,a0); and(y2,d,s0_n,s1);

and(y6,a0_n,a1,a2); and(y3,d,s0,s1);

and(y7,a0,a1,a2);

endmodule

endmodule

Four bit adder

Mux module four_bit_adder(a,b,sum,carry);

module mux(a,b,c,d,s0,s1,y); output[3:0] sum;

input a,b,c d,s0,s1; reg[3:0]sum;

output y; output carry;

reg y; reg carry;

always@(*)
input[3:0]a;
begin
wire[3:0]a;
y=s0?(s1?d:c):(s1?b:a);
input[3:0]b;
end
wire[3:0]b;
end module

DeMux integer i;

module demux(s1,s0,d,y0,y1,y2,y3);

input s1,s0,d; reg[4:0]s;

always @(a or b) begin

output y0,y1,y2,y3;
s[0] = 0;
wire s1_n;
for(i=0;i<3;i=i+1) begin
wire s0_n;
sum[i]=a[i]^b[i]^s[i];

s[i+1] = (a[i] & b[i])|(b[i] & s[i])|(s[i] & a[i]);

not(s1_n,s1);
end
not(s0_n,s0);
carry = s[3];
and(y0,d,s0_n,s1_n);
end
and(y1,d,s0,s1_n);
endmodule
 wire load ;
Shift registers (SISO, reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
SIPO,PIPO,PISO) temp <= 1;
else if (load)
temp <= din;
SISO else begin
dout <= temp[3];
module Serial_in_Serial_out ( din temp <= {temp[2:0],1'b0};
,clk ,reset ,dout ); end
end
output dout ; endmodule
reg dout ;

input din ;
wire din ;
input clk ;
SIPO
wire clk ;
input reset ; module SIPO ( din ,clk ,reset
wire reset ; ,dout );

reg [2:0]s; output [3:0] dout ;

wire [3:0] dout ;
always @ (posedge (clk)) begin
if (reset) input din ;
dout <= 0; wire din ;
else begin input clk ;
s[0] <= din ; wire clk ;
s[1] <= s[0] ; input reset ;
s[2] <= s[1] ; wire reset ;
dout <= s[2];
end reg [3:0]s;
end
always @ (posedge (clk)) begin
endmodule if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
PISO s[1] <= s[2];
s[0] <= s[1];
module parallel_in_serial_out ( end
din end
,clk ,reset ,load ,dout );
output dout ; assign dout = s;
reg dout ;
input [3:0] din ;
wire [3:0] din ; endmodule
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
PIPO Comparator
module PIPO ( din ,clk ,reset module comparator(a,b,a0,b0,y0,y1,y2);
,dout );
output [3:0] dout ; input a,b,a0,b0;
reg [3:0] dout ;
input [3:0] din ; output y0,y1,y2;
wire [3:0] din ;
input clk ; wire a_n;
wire clk ;
wire b_n;
input reset ;
wire reset ; wire a0_n;
always @ (posedge (clk)) begin
if (reset) wire b0_n;
dout <= 0;
else
dout <= din;
end not(a_n,a);
endmodule
not(b_n,b);

not(a0_n,a0);
4 bit up/down counter not(b0_n,b0);
module counter4bit(clk,reset,dout); and(a1,b_n,a);
input clk,reset; and(a2,a0,b_n);
output [3:0]dout; and(a3,a0,a);
reg[3:0]dout; and(a4,b,a_n);
wire clk,reset;
and(a5,b0,b,a0_n);
initial dout=0;
and(a6,a_n,a0_n,b0);
always@(posedge(clk))
xnor(a7,a,b);
begin
xnor(a8,b0,a0);
if(reset)
or(b1,a2,a3);
dout<=0;
and(b2,b1,b0_n);
else
or(y0,b2,a1);
dout<=dout+1;
or(y1,a4,a5,a6);
end
and(y2,a7,a8);

endmodule
endmodule
 wire enable ;

input din ;
4 bit counter wire din ;
module counter4bit(clk,reset,dout); input reset ;
input clk,reset; wire reset ;
output [3:0]dout;

reg[3:0]dout; always @ (enable or din or reset) begin

wire clk,reset; if (reset)

dout = 0;
initial dout=0; else begin

if (enable)
always@(posedge(clk)) dout = din;
begin end
if(reset) end
dout<=0;

else endmodule
dout<=dout+1;

end
decoder
endmodule module d_latch ( enable ,din ,reset ,dout );

output dout ;
d latch reg dout ;

module d_latch ( enable ,din ,reset ,dout );

input enable ;

output dout ; wire enable ;

reg dout ; input din ;

wire din ;

input enable ; input reset ;

wire reset ;

always @ (enable or din or reset) begin

if (reset)
d-flipflop
dout = 0;
module dflipflop (din,clk,reset,dout);
else begin
input din,clk,reset;
if (enable)
output dout;
dout = din;
reg dout;
end
always@(posedge clk)
end
begin

if(reset)
endmodule
dout<=1;

else
demux dout<=din;

module demux(s1,s0,d,y0,y1,y2,y3); end

input s1,s0,d; endmodule

output y0,y1,y2,y3;

wire s1_n;

wire s0_n;

four bit adder

not(s1_n,s1);
module four_bit_adder(a,b,sum,carry);
not(s0_n,s0);
output[3:0] sum;
and(y0,d,s0_n,s1_n);
reg[3:0]sum;
and(y1,d,s0,s1_n);
output carry;
and(y2,d,s0_n,s1);
reg carry;
and(y3,d,s0,s1);

input[3:0]a;
endmodule
wire[3:0]a;
 input[3:0]b; not(a1_n,a1);

wire[3:0]b; not(a_n,a);

and(b2,a,b);

integer i; and(b1,a1_n,c);

or(borrow,b1,b2);

reg[4:0]s;

always @(a or b) begin endmodule

s[0] = 0;

for(i=0;i<3;i=i+1) begin
full subtractor
sum[i]=a[i]^b[i]^s[i]; module fullsubtractor (a,b,c,diff,borrow);

s[i+1] = (a[i] & b[i])|(b[i] & input a,b,c;

s[i])|(s[i] & a[i]); output diff,borrow;
end reg diff,borrow,l,m,a_n,p,t;
carry = s[3]; always@(a or b or c)

begin
end a_n=~a;
endmodule p=~l;

t=p&c;

l=a^b;

full subtractor m=a_n&b;

diff=p^c;
module full_subtractor(a,b,c,diff,borrow);
borrow=t|m;
input a,b,c;
end
output diff,borrow;
endmodule
wire a_n;

wire a1_n; half subtractor

module half_subtractor(a,b,difference,borrow);
xor(a1,a,b); input a,b;
xor(diff,a1,c); output difference,borrow;
 wire a_n; wire j ;

input k ;

xor(difference,a,b); wire k ;

not(a_n,a); input clk ;

and(borrow,a_n,b); wire clk ;

endmodule input reset ;

half subtractor wire reset ;

module halfsubtractor (a,b,diff,borrow);

input a,b; always @ (posedge (clk)) begin

output diff,borrow; if (reset) begin

reg diff,borrow,a_n; q <= 0;

always@(a or b) qb <= 1;

begin end

a_n=~a; else begin

diff=a^b; if (j!=k) begin

borrow=a_n&b; q <= j;

end qb <= k;

endmodule end

else if (j==1 && k==1) begin

q <= ~q;
jk ff qb <= ~qb;
module jk_flipflop ( j ,k ,clk ,reset ,q ,qb ); end

end
output q ; end
reg q ;

output qb ;

reg qb ; endmodule

input j ;
 tflipflop
mux module t_flipflop ( t ,clk ,reset ,dout );

module mux(mux_out,i0,i1,i2,i3,select);
output dout ;
input i0,i1,i2,i3;
reg dout ;
output mux_out;

input[1:0] select;
input t ;
reg mux_out;
wire t ;
always@(select,i0,i1,i2,i3)
input clk ;
case(select)
wire clk ;
2'b00: mux_out=i0;
input reset ;
2'b01: mux_out=i1;
wire reset ;
2'b10: mux_out=i2;

2'b11: mux_out=i3;
initial dout = 0;
endcase

always @ (posedge (clk)) begin

endmodule
if (reset)

dout <= 0;
module muxxx(a,b,c,d,s0,s1,y);
else begin
input a,b,c d,s0,s1;
if (t)
output y;
dout <= ~dout;
reg y;
end
always @(*)
end
begin

y=s0?(s1?d:c):(s1?b:a);
endmodule
end

end module