11/13/2019 SDFDLM, SDFNET, or SDFNEP message: Causes and cures

SDFDLM, SDFNET, or SDFNEP message: Causes and cures

Error Code
SDFNET, SDFNEP, SDFDLM

Error Message
xmelab or ncelab: *W,SDFNEP: Unable to annotate to non-existent path <iopath> of
instance <instance_name> of module <module_name>.

xmelab or ncelab: *W,SDFNET: Unable to annotate to non-existent timing check

<timing_check> of instance <instance_name> of module <module_name>

xmelab or ncelab: *W,SDFDLM: Scope <scope> has delay_mode directive. Skipping

IOPATH/Timing check annotation for scope <scope>.

Definition
The warning mnemonic SDFNEP or SDFNET is reported when the SDF annotator does not find the IO path or the
timing check in the RTL of the instance being annotated. SDFNEP corresponds to the IO path, and SDFNET
corresponds to timing checks.

The SDFDLM warning is reported if the option “-delay_mode zero/unit/distributed” is passed in the
elaboration command. It disables the annotation of IO paths and timing checks.

To avoid the warning mnemonics SDFNEP/SDFNET from being reported and to ensure 100% annotation of SDF
delays, the Verilog specify block and the SDF should correspond to each other in accordance with the IEEE Std
1800-2012 - Section: 32.4 Mapping of SDF constructs to SystemVerilog.

In the SDF design flow, error SDFNET, SDFNEP & SDFDLM can come under different circumstances. Your design
scenario may be one of them so have look to below table:

Scenario Description
1 Signal order mismatch between SDF and Verilog
2 Missing conditions in Verilog
3 SDF with -delay_mode options
4 Edge mismatch between SDF and Verilog
5 Operator mismatch between SDF and Verilog
6 Same timing or path does not exist between SDF and Verilog
7 Condition mismatch between SDF and Verilog
Tool does not annotate '01' (edge_identifiers) in SDF to posedge in
8
HDL
9 Escaped characters in SDF
10 Timings checks are splited
Note - Refer “Related Solutions ” section for other relevant articles.

The testcase is attached for each scenario.

testcases_sdfnep_sdfnet/scenerio<no>

Execution command to see the warning: make run_mismatch

Execution command with the correct mapping: make run_annotate

Solution
Scenario 1: Signal order mismatch between SDF and Verilog

SDF Verilog Comments

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(SETUPHOLD data (posedge clk) $setuphold(data, posedge clk, SDFNET
(0.0865)(0.0654)) 1, 1);

(RECREM (posedge ena) (posedge

$recrem(posedge clk, posedge
clk) (0.227::0.227) SDFNET
ena, 0,0);
(0.085::0.056))

Solution:

The SDF and the Verilog specify block lack the proper signal order to match one another. The
Verilog specify block syntax does not match with the SDF for the "data" signal. It should be the second
argument of the $setuphold check. Similar rules are applicable for $recrem and other timing checks.

$setuphold (reference event, data_event ...) // Verilog $setuphold syntax

(SETUPHOLD data_event clk_event ...) // SDF SETUPHOLD syntax

Refer to the documents "Verilog Timing Checks" and "SDF Timing Annotation" for the signal order syntax of
timing checks and SDF syntax, respectively.

Incorrect order w.r.t. SDF Correct order to match SDF

$setuphold(data, posedge clk , 1, $setuphold(posedge clk , data, 1,

1); 1);

$recrem (posedge clk, posedge ena, $recrem (posedge ena, posedge clk,
1, 1); 1, 1);

Scenario 2: Missing conditions in Verilog

When a conditional statement does not exist in the Verilog specify block for IOPATH or timing checks, the
simulator gives a warning message while checking the constructs of the SDF file with their corresponding cell
modules.

SDF Verilog Comments

(COND A&&B (IOPATH CI

(CI +=> CO) = 1.1 ; SDFNEP
CO(0.192)(0.276)) )

(SETUPHOLD (posedge data)(COND

$setuphold(negedge clk,
my_cond==1'b1 (negedge clk)) SDFNET
posedge data, 1, 1);
(5)(7))

During delay annotation, the simulator does not find the equivalent "if condition" in the specify file to match
the COND in the SDF file.

Solution:

When a conditional statement exists in the SDF file, examine to be certain of an exact match to your cell
modules’ specify block for IOPATH and timing checks. Put the same condition as shown in the following
table:

SDF Verilog

(COND A&&B (IOPATH CI CO(0.192)

if ( A && B ) (CI +=> CO) = 1.1 ;
(0.276)) )

(SETUPHOLD (posedge data)(COND

$setuphold(negedge clk &&&
my_cond===1'b1 (negedge clk))
(my_cond===1'b1), posedge data, 1, 1);
(5)(7))

Note: Missing conditions in the SDF do not issue any warning corresponding to a condition in the specify
block.

Scenario 3: SDF with -delay_mode options can report SDFDLM, SDFNEP, SDFNET

If SDF annotation and the "-delay_mode" switch (zero/unit/distributed) or the similar compiler
directives like "`delay_mode_distributed" are used together, it generates the warning.

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Everything works fine if "-delay_mode path" or "`delay_mode_path" is used with SDF annotation.

Solution:

The switch usage causes the delay path to not exist. This effectively hides the specify block and the SDF
cannot find the proper targets.

For Incisive 14.20 and earlier versions, this scenario creates SDFNEP and SDFNET warnings for IO paths
and timing checks, respectively.
From version 15.10 onward, a new warning SDFDLM is generated to isolate this case from the general
SDFNEP and SDFNET warnings.

The SDF file can be edited to remove the hierarchy affected by the switch or directives as an alternative.

Scenario 4: Edge mismatch between SDF and Verilog

There is an edge specifier in an IOPATH or TIMINGCHECK statement in an SDF file. The SDF construct does
not annotate data to the following statement:

SDF Verilog Comments

(CK => (QN: D)) =

(IOPATH (posedge CK) QN (2) (3)) SDFNEP
(0);

(TIMINGCHECK (SETUP D (posedge

$setup (D, CK, 0); SDFNET
CK) (4)))

Solution:

If there is an edge specifier in an IOPATH or timing checks in an SDF file, there must be an exact match in the
Verilog code.
The tools do have a switch option called -sdf_nopathedge that will ignore the edge specifier in the SDF
IOPATH only and will annotate the last matching SDF statement for a signal pair.

If there is no edge specifier in an IOPATH or TIMINGCHECK statement in an SDF file, the simulator annotates
data to any path (or timing check) from the HDL code that has the same reference and data nets as specified
in the SDF IOPATH or TIMINGCHECK statement. Therefore, non-edge-specified IOPATH and TIMINGCHECK
SDF statements overwrite their corresponding edge-specified paths and checks from the HDL.
Regenerate the SDF to match the path same as in Verilog code or vice-versa.

SDF Verilog Comments

(posedge CK => (QN: D))

(IOPATH (posedge CK) QN (2) (3)) Annotate
= (0);

(TIMINGCHECK (SETUP D (posedge CK) $setup (D, posedge CK,

Annotate
(4))) 0);

$setup (D, posedge CK,

0);
(TIMINGCHECK (SETUP D CK (4))) Annotate
$setup (negedge D, CK,
0);

Note: The option -sdf_nopathedge is applicable for 'COND' and 'CONDELSE' statements also if the
corresponding 'if' and 'ifnone' specify block statements are missing the edge specifier.

Scenario 5: Operator mismatch between SDF and Verilog

SDF Verilog Comments

(COND ~(D0)&D1 (IOPATH S(0.21) if (!D0 & D1) (S => X) =

SDFNEP
(0.30)) ) (0, 0);

Solution:

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The operator mismatch is the source of the back-annotation warning. The operators "~" and "!" may not be
used interchangeably in the Verilog world. In certain limited cases, they can give similar results, but they are
different operators.
The cause of this mismatch is often found in a difference in the Verilog representation used for simulation and
the synthesis tool representation (likely using the "~" operator), and thus the synthesis tool uses the "~"
operator in the SDF it creates as well.

Here is some information of clarification on the two operators. For single-bit inputs, the behavior is the same.

"!" is the logical negation operator; it gives 1, 0, x, x as output to 1, 0, x, z inputs respectively for a single-
bit value.
"~" is the bitwise negation operator; it gives 1, 0, x, x as output to 1, 0, x, z inputs respectively for a
single-bit value.
For multi-bit values, the operators diverge as "~" will give a multi-bit output and "!" will give only a single bit
value.|
Example:
For a =4'b1011, "~a" will be 4'b0100, but "!a" will be 1'b0. If (~a) will evaluate to true and if (!a) will
evaluate to false.

Note: These behaviors are defined by the IEEE 1800-2012 LRM (and all earlier versions as well).

Scenario 6: Same timing or path does not exist between SDF and Verilog

If you specify a module path delay or timing check that does not already exist in the Verilog model or any signal
mismatch, the simulators give the error and do not annotate the timing information.

SDF Verilog Comments

(DELAY (ABSOLUTE (IOPATH a w

(a*>y) = 1; SDFNEP
(1))))

(TIMINGCHECK (HOLD clk k (1))) $hold(clk,j,1); SDFNET

Solution:

If you specify a module path delay or timing check that does not already exist in the Verilog model or any signal
mismatch, the simulators cannot annotate the timing information.
You have a library disconnect between the SDF generating tool library and the simulation library. You must
remove the mismatch between the SDF and the Verilog file for SDF annotation.

Scenario 7: Condition mismatch between SDF and Verilog

SDF Verilog Comments

if (B === 1'b0) (A *> Y) =

(0.01, 0.01);

(COND (1'b0===B) (IOPATH A Y if (B) (A *> Y) = (0.01,

SDFNEP
(0.1::0.1)(0.1::0.1))) 0.01);

if (B == 1’b1) (A *> Y) =
(0.01, 0.01);

Solution:

In the case of State Dependent Path Delays (SDPD), the State Dependent Path is a path that occurs only
when the condition is met.

Place the signal on the LHS of the identity operator instead of the constant in the SDF file to match the
specify block ordering.
You want to see if (1’b0===B) in the SDF matches to (B===1'b0) from the specify block. They are not a
match. The operand order is important in Verilog, VHDL, and everywhere else. Even though the identity
operator does not give a different simulation result if the operands are switched in this simple case, they are
not identical expressions. The expression on the left hand side of the binary operator is not the same in the
SDF (1'b0) and the specify block (B); therefore no match is made. A signal and a constant are not the same
expression.

Here are some spec excerpts to show additional pertinent information.

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SDF spec Annex A.1.5 gives the following:

"conditional_port_expr ::=
simple_expression
| ( conditional_port_expr )
| unary_operator ( conditional_port_expr )
| conditional_port_expr binary_operator conditional_port_expr

This is the case of a binary operator with an expression on each side of the identity operator. Refer to IEEE Std
1497-2001 - Section 5.4.7.

Scenario 8: Tool does not annotate '01' (edge_identifiers) in SDF to posedge in HDL

The following SDF is attempting to match a 01 edge on clk to a posedge on clk in the HDL (or using a 10 edge
to a negedge of clk). This results in a warning message.

SDF Verilog Comments

(TIMINGCHECK (SETUP d (01 clk) $setup(d, posedge

SDFNET
(0.1220:0.1220:0.1220)) clk,2,notifier);

This 01 construct is legal SDF, but it is not a match to a posedge. These are called edge_identifiers in the spec
and require an exact match, not just similar.

Following are all legal forms of edge identifiers. (Refer to IEEE 1497-2001, Section 5.5.2 & A.1.3 Timing
Specifications)

posedge, negedge, 01, 10, 0z, z1, 1z, z0

Solution:

The SDF 3.0 standard and IEEE 1497 allow both "01" and posedge as edge identifiers. They are not
interchangeable with one another in terms of function, such as matching the posedge construct in Verilog.
SDF "01" matches the HDL "edge [01]", not "posedge".

Only posedge in SDF matches posedge in the HDL timing check. Posedge represents three value transitions (
0->1, 0->Z, Z->1) in the simulation, whereas 01 only represents one value transition. The simulator conforms
to the specifications.
The SDF needs to be modified to replace '01' with posedge, and '10' with negedge (row 2 in the table below)

SDF Verilog Comments

(TIMINGCHECK (SETUP d (01 clk) $setup (d, edge [01] clk, 2,

Annotate
(0.1220:0.1220:0.1220)) notifier) ;

(TIMINGCHECK (SETUP d (posedge clk) $setup (d, posedge clk, 2,

Annotate
(0.1220:0.1220:0.1220)) notifier) ;

Note: The design should succeed without warning in the second run; the first run will give a timing violation at
30 ns. The sdf.log files have the actual annotation information in them.

Scenario 9: Escaped character in SDF

The SDF has escaped characters as follows:

(CELL
(CELLTYPE "bpts3chp")
(INSTANCE u1tps_pins\/u1tps_chiptop_iob\/uJTAG_TDO_dp138)
(DELAY
(ABSOLUTE
(IOPATH A IO (3.187:3.187:3.187) (2.312:2.312:2.312))

Solution

One possible cause could be an incorrect hierarchy separator in the SDF file. The SDF standard says that the
default hierarchy separator is a period, but a slash may also be used. The hierarchy divider entry specifies
which of the two permissible characters are used in the file.
Syntax:
hierarchy_divider:= (DIVIDER HCHAR)

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Where HCHAR is either a period (.) or a slash (/). It should not be in quotes. Be certain that the SDF paths and
the DIVIDER entry are aligned.

Scenario 10 : Timings checks are splited

Refer the attached word document (All_scenario_SDFNEP_SDFNET.docx)

Example
None

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