 Component cộng 1 bit đầy đủ

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cong1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end cong1bit;

architecture Behavioral of cong1bit is

begin
s<=(a xor b) xor ci;
co<=(a and b) or ((a xor b) and ci);
end Behavioral;

 Cộng 3 bit sử dụng component

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cong3bit is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b : in STD_LOGIC_VECTOR (2 downto 0);
ci : in STD_LOGIC;
s : inout STD_LOGIC_VECTOR (2 downto 0);
co : inout STD_LOGIC;
led : out std_logic_vector (6 downto 0));
end cong3bit;

architecture Behavioral of cong3bit is

signal c1,c2: std_logic;
signal trong: std_logic_vector (3 downto 0);
component cong1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end component;
begin
u1: cong1bit port map (a(0),b(0),ci,s(0),c1);
u2: cong1bit port map (a(1),b(1),c1,s(1),c2);
u3: cong1bit port map (a(2),b(2),c2,s(2),co);

trong <= co & s;

process(trong)
begin
case trong is
when "0000" => led <= "1000000";
when "0001" => led <= "1111001";
when "0010" => led <= "0100100";
when "0011" => led <= "0110000";
when "0100" => led <= "0011001";
when "0101" => led <= "0010010";
when "0110" => led <= "0000010";
when "0111" => led <= "1111000";
when "1000" => led <= "0000000";
when "1001" => led <= "0010000";
when "1010" => led <= "0001000";
when "1011" => led <= "0000011";
when "1100" => led <= "0000110";
when "1101" => led <= "0100001";
when "1110" => led <= "0000110";
when "1111" => led <= "0001110";
when others => null;
end case;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity chuoibit is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end chuoibit;

architecture Behavioral of chuoibit is

type state is (st0,st1,st2,st3);
signal pr,nx: state;
begin
process(clk,rst)
begin
if(rst='1') then
pr<=st0;
elsif(clk' event and clk='1') then
pr<=nx;
end if;
end process;

process(pr,d)
begin
case pr is
when st0=>
q<='0';
if(d='1') then
nx<=st1;
else
nx<=st0;
end if;
when st1=>
q<='0';
if(d='1') then
nx<=st2;
else
nx<=st0;
end if;
when st2=>
q<='0';
if(d='1') then
nx<=st3;
else
nx<=st0;
end if;
when st3=>
q<='1';
if(d='1') then
nx<=st3;
else
nx<=st0;
end if;
end case;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dem10tien is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (6 downto 0));
end dem10tien;

architecture Behavioral of dem10tien is

begin
process(clk,rst)
variable dem: integer range 0 to 10;
begin
if(rst='1') then
dem:=0;
elsif(clk' event and clk='1') then
dem:=dem+1;
if(dem=10) then
dem:=0;
end if;
end if;

case dem is
when 0 => led <= "1000000";
when 1 => led <= "1111001";
when 2 => led <= "0100100";
when 3 => led <= "0110000";
when 4 => led <= "0011001";
when 5 => led <= "0010010";
when 6 => led <= "0000010";
when 7 => led <= "1111000";
when 8 => led <= "0000000";
when 9 => led <= "0010000";
when others => null;
end case;
case dem is
when 0 => y <= "0000";
 when 1 => y <= "0001";
when 2 => y <= "0010";
when 3 => y <= "0011";
when 4 => y <= "0100";
when 5 => y <= "0101";
when 6 => y <= "0110";
when 7 => y <= "0111";
when 8 => y <= "1000";
when 9 => y <= "1001";
when others => null;
end case;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity de4 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0);
dk : in STD_LOGIC_VECTOR (2 downto 0));
end de4;

architecture Behavioral of de4 is

begin
process(a,b,dk)
begin
if dk="001" then
y <= ('0' & a) + ('0' & b);
elsif dk="010" then
y <= ('0' & a) + 1;
elsif dk="100" then
y <= ('0' & b) + 1;
end if;
 end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity de4 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b : in STD_LOGIC_VECTOR (2 downto 0);
dk : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (6 downto 0));
end de4;

architecture Behavioral of de4 is

signal x: std_logic_vector (3 downto 0);
begin
process(a,b,dk)
begin
if dk="001" then
x<= ('0' & a) + ('0' & b);
elsif dk="010" then
x <= ('0' & a) + 1;
elsif dk="100" then
x <= ('0' & b) + 1;
end if;
y<=x;
end process;

process(x)
begin
case x is
when "0000" => led <="1000000";
when "0001" => led <="1111001";
when "0010" => led <="0100100";
when "0011" => led <="0110000";
when "0100" => led <="0011001";
when "0101" => led <="0010010";
 when "0110" => led <="0000010";
when "0111" => led <="1111000";
when "1000" => led <="0000000";
when "1001" => led <="0001000";
when others => null;
end case;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity de5 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
ci : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (1 downto 0);
co : out STD_LOGIC);
end de5;

architecture Behavioral of de5 is

signal tg : std_logic;
begin
process(a,b,ci)
begin
s(0) <= a(0) xor b(0) xor ci;
tg <= (a(0) and b(0)) or (ci and (a(0) xor b(0)));
end process;

process(a,b,tg)
begin
s(1) <= a(1) xor b(1) xor tg;
co <= (a(1) and b(1)) or (tg and (a(1) xor b(1)));
end process;

end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DE6 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC;
y : out STD_LOGIC);
end DE6;

architecture Behavioral of DE6 is

type state is (st0,st1,st2,st3);
signal pr,nx : state;
begin
process(clk,rst)
begin
if rst='1' then
pr <= st0;
elsif rising_edge(clk) then
pr <= nx;
end if;
end process;

process(pr,d)
begin
 case pr is
when st0 =>
y <='1';
if d='0' then
nx <= st1;
else
nx <= st0;
end if;
when st1 =>
y <='1';
if d='0' then
nx <= st2;
else
nx <= st0;
end if;
when st2 =>
y <='1';
if d='0' then
nx <= st3;
else
nx <= st0;
end if;
when st3 =>
y <='0';
if d='0' then
nx <= st3;
else
nx <= st0;
end if;
end case;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity de7 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end de7;

architecture Behavioral of de7 is

begin
process(clk,rst)
variable dem : integer range 9 downto 0 :=9;
begin
if rst='1' then
dem :=9;
elsif rising_edge(clk) then
if dem=0 then
dem :=9;
else
dem := dem -1;
end if;
end if;
y <= conv_std_logic_vector(dem, 4);
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity de8 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0);
dk : in STD_LOGIC_VECTOR (2 downto 0));
end de8;
architecture Behavioral of de8 is

begin
process(a,b,dk)
begin
if dk="001" then
y <= ('0' & a) + ('0' & b);
elsif dk="010" then
y <= ('0' & a) + 2;
elsif dk="100" then
y <= ('0' & b) + 2;
end if;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity de9 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
ci : in STD_LOGIC;
co : inout STD_LOGIC;
led7 : out STD_LOGIC_VECTOR (7 downto 0);
s : inout STD_LOGIC_VECTOR (1 downto 0));
end de9;

architecture Behavioral of de9 is

signal tg : std_logic;
signal tam : std_logic_vector (2 downto 0);
begin
process(a,b,ci)
begin
s(0) <= a(0) xor b(0) xor ci;
tg <= (a(0) and b(0)) or (ci and (a(0) xor b(0)));
end process;
 process(a,b,tg)
begin
s(1) <= a(1) xor b(1) xor tg;
co <= (a(1) and b(1)) or (tg and (a(1) xor b(1)));
end process;
tam <= co & s;
process(tam)
begin
case tam is
when "000" => led7 <= x"c0";
when "001" => led7 <= x"f9";
when "010" => led7 <= x"a4";
when "011" => led7 <= x"b0";
when "100" => led7 <= x"99";
when "101" => led7 <= x"92";
when "110" => led7 <= x"82";
when "111" => led7 <= x"f8";
when others => null;
end case;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity de11 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end de11;

architecture Behavioral of de11 is

type state is (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9);
signal pr,nx : state;
begin
process(clk,rst)
begin
if rst='1' then
pr <= st0;
elsif rising_edge(clk) then
pr <= nx;
end if;
end process;

process(pr)
begin
case pr is
when st0 =>
y <= "0000";
nx <= st1;
when st1 =>
y <= "0001";
nx <= st2;
when st2 =>
y <= "0010";
nx <= st3;
when st3 =>
y <= "0011";
nx <= st4;
when st4 =>
y <= "0100";
nx <= st5;
when st5 =>
y <= "0101";
nx <= st6;
when st6 =>
y <= "0110";
nx <= st7;
when st7 =>
y <= "0111";
nx <= st8;
when st8 =>
y <= "1000";
nx <= st9;
when st9 =>
y <= "1001";
 nx <= st0;
end case;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity de12 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b : in STD_LOGIC_VECTOR (2 downto 0);
dk : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (6 downto 0));
end de12;

architecture Behavioral of de12 is

signal x: std_logic_vector (3 downto 0);
begin
process ( a,b,dk)
begin
if dk="0001" then
x<=('0'& a) + 1;
elsif dk="0010" then
x<=('0'& b) + 1;
elsif dk="0100" then
x<=('0'& a) and ('0'& b);
elsif dk="1000" then
x<=('0'& a) or ('0'& b);
end if;
y<=x;
end process;

process(x)
begin
 case x is
when "0000" => led <="1000000";
when "0001" => led <="1111001";
when "0010" => led <="0100100";
when "0011" => led <="0110000";
when "0100" => led <="0011001";
when "0101" => led <="0010010";
when "0110" => led <="0000010";
when "0111" => led <="1111000";
when "1000" => led <="0000000";
when "1001" => led <="0001000";
when others => null;
end case;
end process;
end Behavioral;