Documente Academic
Documente Profesional
Documente Cultură
Content
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 3-lines 9 bit Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 4-Line SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.2 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
4.3 I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.2 Starting the communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.3 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.4 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4 Reading mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.1 IIdentification byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/62
STE2007 Content
6 Instruction setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1 Initialization (power on sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2 Display data writing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3 Power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 Display on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2 Display normal/reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3 Display all points on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4 Page address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.5 Column address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.6 Display start line address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.7 Segment driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.8 Common driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.9 Display data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.10 Data reading from driver (Driver TxData–mode) . . . . . . . . . . . . . . . . . . . 46
8.11 Power Control Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.12 VLCD set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.12.1 V0R - Voltage Range Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.12.2 VOP set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.12.3 Electronic volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.13 Power saver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.15 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.16 Image Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/62
Content STE2007
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4/62
STE2007 Introduction
1 Introduction
In this document is specified LCD driver for Black&White full graphic displays with a
resolution of 96x68, 96x65, 96x49, and 96x33 (ColumnsXRows).
Abbreviations
LCD Liquid Crystal Display
COG Chip On Glass –technology
MCU Micro Controller Unit
DDRAM Display Data Random Access Memory
MSB Most Significant Bit
LSB Least Significant Bit
T.B.D. To Be Defined
Memory Size
(Columns x Rows)
96x68
DDRAM capacity:
6528 bits
Mux
1:68
1:65
1:49
1:33
65
70
75
80
5/62
Introduction STE2007
R66
STE2007
BUMP SIDE
(0,0)
Y
! /
!
!
45µm
72µm VSS_AUX
VSS_AUX
VSS_AUX
VSS_AUX
R67
R65
6/62
STE2007 Driver pin description
7/62
Driver pin description STE2007
VSS/VSSAUX IDA=”0”
IDA I
VDDI IDA=”1”
VSS/VSSAUX IDB=”0”
IDB I
VDDI IDB=”1”
8/62
STE2007 Driver pin description
9/62
Electrical characteristics STE2007
3 Electrical characteristics
Note: (*) ESD tests have been performed with VSS, VSS_LCD and VSS_CP shorted together
10/62
STE2007 Electrical characteristics
3.2 DC characteristics
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5 V;
Tamb = 25°C; unless otherwise specified.
Table 8. DC characteristics
Symbol Parameter Test Condition Min. Typ. Max. Unit
Logic inputs
Logic outputs
11/62
Electrical characteristics STE2007
3.3 AC characteristics
Tamb = 25°C; unless otherwise specified.
tcss 60 ns
tcsh !CS Chip select 100 ns
tchw 50 ns
tsds Input Serial Data Data setup time 100 ns
SDAIN
tsdh Interface Data hold time 100 125 ns
tac Access Time 0 100 ns
Output Serial Data
SDAOUT Output Disable
tod interface 25 100 ns
Time
tscyc Serial clock cycle 250 ns
Serial clock H
tshw 100 ns
SCLK Serial clock input pulse width
Serial clock L
tslw 100 ns
pulse width
Note: 1 The input signal rise and fall times must be within 10ns.
2 Every timing is specified on the basis of 30% and 70% of VDDI.
!CS
tscyc
tslw
SCLK
tshw
tf tr
tsds tsdh
SDA/MCU TxData
12/62
STE2007 Electrical characteristics
Note: 1 Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is always 3-8ns
before SCLK pulse falling edge
2 The input signal rise and fall times must be within 10ns.
3 Every timing is specified on the basis of 30% and 70% of VDDI.
Note: 1 The input signal rise and fall times must be within 10ns.
2 Every timing is specified on the basis of 30% and 70% of VDDI.
13/62
Electrical characteristics STE2007
Timing A Timing B
SCLK
Timing A T1 T2
SCLK
MCU TxData
Driver TxData
!CS
Timing B T3 T4
SCLK
Driver TxData
T5
!CS
1/2 SCLK 1/2 SCLK
Note: 1 The input signal rise and fall times must be within 10ns.
2 Every timing is specified on the basis of 30% and 70% of VDDI.
14/62
STE2007 Electrical characteristics
trj trw
!RES
trs
15/62
Interface STE2007
4 Interface
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
16/62
STE2007 Interface
Break
!CS
SCL
SDA D7 D6 D5 D4 D3 D/!C D7 D6 D5 D4
COMMAND/PARAMETER COMMAND/PARAMETER
LR0204
!CS
SCL
SDA D3 D2 D1 D0 D/!C D7 D6 D5 D4 D3 D2 D1 D0
COMMAND/PARAMETER COMMAND/PARAMETER
LR0203
17/62
Interface STE2007
18/62
STE2007 Interface
Timing A T1 T2
SCLK
MCU TxData
Driver TxData
!CS
Timing B T3 T4
SCLK
Driver TxData
T5
!CS
1/2 SCLK 1/2 SCLK
Figure 9. Timing chart for start and stop of data reading from driver
... High Z
MCU TxData D/C='0' 7 1 0 ... D/C 7
0
... ...
!CS
19/62
Interface STE2007
D/!C
SCL
SDA
(input) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA Hi-Z
(output)
LR0189
D/!C
SCL
SDA
(input) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA Hi-Z
(output)
COMMAND DATA to VIDEO RAM DATA to VIDEO RAM DATA to VIDEO RAM
LR0190
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STE2007 Interface
Break
!CS
D/!C
SCL
SDA D7 D6 D5 D4 D3 D7 D6 D5 D4 D3
COMMAND/PARAMETER COMMAND/PARAMETER
LR0192
21/62
Interface STE2007
!CS
D/!C
SCL
SDA D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND/PARAMETER COMMAND/PARAMETER
LR0191
!CS
D!C
SCL
SDA High Z
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(Input)
SDA High Z D0
D7 D6 D5 D4 D3 D2 D1
(Output)
LR0255
MCU Data Tx Start LCD Driver Data Tx Start MCU Data Tx Start
22/62
STE2007 Interface
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer starts with a start condition and terminated with a stop condition. The
number of data bytes transferred between the start and the stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with the ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the signals is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master receiver must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges
has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and
hold time must be taken into account. A master receiver must signal an end-of-data to the
slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.
Having the acknowledge output (SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track
resistance from the SDAOUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is possible that during the acknowledge cycle the STE2007 will not be able to
create a valid logic 0 level. By splitting the SDA input from the output the device could be
used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2007 is able to detect the
special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in
Hs-mode without detecting the master code.
23/62
Interface STE2007
DATA
DATA OUTPUT
BY TRANSMITTER MSB LSB
DATA OUTPUT
BY RECEIVER
D00IN1152
S S R
ADDRESS BYTE 0 1 1 1 1 A A /
1 0 W
READ or WRITE
DESIGNATOR
24/62
STE2007 Interface
CONTROL BYTE Co DC 0 0 0 0 0 0
The Co bit is the control byte MSB and defines if after this control byte will follow a single
byte sequence (Co = 1) or a multiple bytes sequence (Co = 0). The D/C bit defines whether
the following byte (if Co = 1) or the following stream of bytes (if Co = 0) are command (D/C =
0) or DDRAM data (D/C = 1).
Depending on state of flags Co and D/C, four writing sequences are possible:
SINGLE COMMAND BYTE SEQUENCE (Co = 1, D/C = 0): a single byte interpreted as a
command will follow the control byte;
SINGLE DATA BYTE SEQUENCE (Co = 1, D/C = 1): a single byte interpreted as a data to
be written in DDRAM will follow the control byte;
MULTIPLE COMMAND BYTES SEQUENCE (Co = 0, D/C = 0): a stream of bytes will follow
the control byte, with each single byte interpreted as a command;
MULTIPLE DATA BYTES SEQUENCE (Co = 0, D/C = 1): a stream of bytes will follow the
control byte, with each byte interpreted as a data byte to be written in DDRAM.
Every single byte of a sequence must be acknowledged by all addressed units.
A multiple data sequence is terminated only by sending a STOP condition on the I2C bus.
When a sequence is terminated, another sequence of any type can follow or a I2C STOP
condition can be sent to close the communication.
In a single or multiple data bytes sequence, every data byte received is stored in the
DDRAM at the location specified by the current values of data pointers. Data pointers are
automatically updated after each single data byte written.
25/62
Interface STE2007
R/W
SLAVE ADDRESS
READ MODE
STE2007 ACK MASTER ACK
R/W
SLAVE ADDRESS
LR0008d
26/62
STE2007 Interface
STE2007
Power IC
VDDCP
VDD VDD
VDDI VDDI
GND VSS
Command decoder
ASIC(MCU) VSSCP
MCU TxData
RESET
Multi
SDA plexer ID
8 bit register
XCS test
SCLK
Driver TxData
Auto
return
VLCD
Voltage booster
LCD Power
Supply circuit
BaseBand side Driver side
Identification Information
Send rading command (DBh)
27/62
Display Data RAM (DDRAM) STE2007
Each pixel can be selected when page address and column address are specified. The
MCU issues Page address set command to change the page and access to another page.
In DDRAM page address 8 (D3,D2,D1,D0=1,0,0,0) only display data D0,D1,D2 & D3 are
valid.
The DDRAM column address is specified by Column address set command.
The specified column address is automatically incremented by +1 when a Display data write
command is entered. After the last column address (5Fh), column address returns to 00h
and page address incremented by +1. After the very last address (column=5Fh, page=8h),
both column address and page address return to 00h (column address=00h, page
address=0h).
28/62
STE2007 Display Data RAM (DDRAM)
Data can be written to the DDRAM at the same time as data is being displayed, without
causing the LCD to flicker.
Segment driver direction command can be used to reverse the relationship between the
DDRAM column address and segment output. This function is achieved writing data into
DDRAM in reverse order (from Right to left).
Normal
SEG0 SEG1 SEG2 ______ SEG93 SEG94 SEG95
Direction
Reverse
SEG95 SEG94 SEG93 ______ SEG2 SEG1 SEG0
Direction
29/62
Display Data RAM (DDRAM) STE2007
ICONMODE="1" ICONMODE="0"
Display start line does not access 65th, 66th, 67th, 68th line Display start line does not access 65th, 66th, 67th, 68th line
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
30/62
STE2007 Display Data RAM (DDRAM)
ICONMODE="1" ICONMODE="0"
Page addressD COM Output COM Output
a Line Line
D3 D2 D1 D0 at Address Normal Reverse Address Normal Reverse
direction direction direction direction
D0 00H COM0 COM63 00H COM0 COM64
D1 01H COM1 COM62 01H COM1 COM63
D2 02H COM2 COM61 02H COM2 COM62
D3 Page 0 03H COM3 COM60 03H COM3 COM61
0 0 0 0
D4 04H COM4 COM59 04H COM4 COM60
D5 05H COM5 COM58 05H COM5 COM59
D6 06H COM6 COM57 06H COM6 COM58
D7 07H COM7 COM56 07H COM7 COM57
D0 08H COM8 COM55 08H COM8 COM56
D1 09H COM9 COM54 09H COM9 COM55
D2 0AH COM10 COM53 0AH COM10 COM54
D3 Page 1 0BH COM11 COM52 0BH COM11 COM53
0 0 0 1
D4 0CH COM12 COM51 0CH COM12 COM52
D5 0DH COM13 COM50 0DH COM13 COM51
D6 0EH COM14 COM49 0EH COM14 COM50
D7 0FH COM15 COM48 0FH COM15 COM49
D0 10H COM16 COM47 10H COM16 COM48
D1 11H COM17 COM46 11H COM17 COM47
D2 12H COM18 COM45 12H COM18 COM46
D3 Page 2 13H COM19 COM44 13H COM19 COM45
0 0 1 0
D4 14H COM20 COM43 14H COM20 COM44
D5 15H COM21 COM42 15H COM21 COM43
D6 16H COM22 COM41 16H COM22 COM42
D7 17H COM23 COM40 17H COM23 COM41
D0 18H COM24 COM39 18H COM24 COM40
D1 19H COM25 COM38 19H COM25 COM39
D2 1AH COM26 COM37 1AH COM26 COM38
D3 Page 3 1BH COM27 COM36 1BH COM27 COM37
0 0 1 1
D4 1CH COM28 COM35 1CH COM28 COM36
D5 1DH Start COM29 COM34 1DH Start COM29 COM35
D6 1EH COM30 COM33 1EH COM30 COM34
D7 1FH COM31 COM32 1FH COM31 COM33
D0 20H COM32 COM31 20H COM32 COM32
D1 21H COM33 COM30 21H COM33 COM31
D2 22H COM34 COM29 22H COM34 COM30
D3 Page 4 23H COM35 COM28 23H COM35 COM29
0 1 0 0 COM36 COM27
D4 24H 24H COM36 COM28
D5 25H COM37 COM26 25H COM37 COM27
D6 26H COM38 COM25 26H COM38 COM26
D7 27H COM39 COM24 27H COM39 COM25
D0 28H COM40 COM23 28H COM40 COM24
D1 29H COM41 COM22 29H COM41 COM23
D2 2AH COM42 COM21 2AH COM42 COM22
D3 Page 5 2BH COM43 COM20 2BH COM43 COM21
0 1 0 1 COM44 COM19
D4 2CH 2CH COM44 COM20
D5 2DH COM45 COM18 2DH COM45 COM19
D6 2EH COM46 COM17 2EH COM46 COM18
D7 2FH COM47 COM16 2FH COM47 COM17
D0 30H COM48 COM15 30H COM48 COM16
D1 31H COM49 COM14 31H COM49 COM15
D2 32H COM50 COM13 32H COM50 COM14
D3 Page 6 33H COM51 COM12 33H COM51 COM13
0 1 1 0 COM52 COM11
D4 34H 34H COM52 COM12
D5 35H COM53 COM10 35H COM53 COM11
D6 36H COM54 COM9 36H COM54 COM10
D7 37H COM55 COM8 37H COM55 COM9
D0 38H COM56 COM7 38H COM56 COM8
D1 39H COM57 COM6 39H COM57 COM7
D2 3AH COM58 COM5 3AH COM58 COM6
D3 Page 7 3BH COM59 COM4 3BH COM59 COM5
0 1 1 1 COM60 COM3
D4 3CH 3CH COM60 COM4
D5 3DH COM61 COM2 3DH COM61 COM3
D6 3EH COM62 COM1 3EH COM62 COM2
D7 3FH COM63 COM0 3FH COM63 COM1
D0 40H COM64 COM64 40H COM64 COM0
D1 Page 8 41H 41H
1 0 0 0 D2 42H 42H
D3 43H 43H
Column address 00H 01H 02H 03H 04H 05H 06H 59H 5AH 5BH 5CH 5DH 5EH 5FH Display start line does not access 65th, 66th, 67th, 68th line
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
31/62
Display Data RAM (DDRAM) STE2007
ICONMODE="1" ICONMODE="0"
Page addressD COM Output COM Output
a Line Line
D3 D2 D1 D0 at Address Normal Reverse Address Normal Reverse
direction direction direction direction
D0 00H COM0 COM47 00H COM0 COM48
D1 01H COM1 COM46 01H COM1 COM47
D2 02H COM2 COM45 02H COM2 COM46
D3 Page 0 03H COM3 COM44 03H COM3 COM45
0 0 0 0
D4 04H COM4 COM43 04H COM4 COM44
D5 05H COM5 COM42 05H COM5 COM43
D6 06H COM6 COM41 06H COM6 COM42
D7 07H COM7 COM40 07H COM7 COM41
D0 08H COM8 COM39 08H COM8 COM40
D1 09H COM9 COM38 09H COM9 COM39
D2 0AH COM10 COM37 0AH COM10 COM38
D3 Page 1 0BH COM11 COM36 0BH COM11 COM37
0 0 0 1
D4 0CH COM12 COM35 0CH COM12 COM36
D5 0DH COM13 COM34 0DH COM13 COM35
D6 0EH COM14 COM33 0EH COM14 COM34
D7 0FH COM15 COM32 0FH COM15 COM33
D0 10H COM16 COM31 10H COM16 COM32
D1 11H COM17 COM30 11H COM17 COM31
D2 12H COM18 COM29 12H COM18 COM30
1 D3 Page 2 13H COM19 COM28 13H COM19 COM29
0 0 0
D4 14H COM20 COM27 14H COM20 COM28
D5 15H COM21 COM26 15H COM21 COM27
D6 16H COM22 COM25 16H COM22 COM26
D7 17H COM23 COM24 17H COM23 COM25
D0 18H COM24 COM23 18H COM24 COM24
D1 19H COM25 COM22 19H COM25 COM23
D2 1AH COM26 COM21 1AH COM26 COM22
1 D3 Page 3 1BH COM27 COM20 1BH COM27 COM21
0 0 1
D4 1CH COM28 COM19 1CH COM28 COM20
D5 1DH Start COM29 COM18 1DH Start COM29 COM19
D6 1EH COM30 COM17 1EH COM30 COM18
D7 1FH COM31 COM16 1FH COM31 COM17
D0 20H COM32 COM15 20H COM32 COM16
D1 21H COM33 COM14 21H COM33 COM15
D2 22H COM34 COM13 22H COM34 COM14
D3 Page 4 23H COM35 COM12 23H COM35 COM13
0 1 0 0 COM36 COM11 COM36 COM12
D4 24H 24H
D5 25H COM37 COM10 25H COM37 COM11
D6 26H COM38 COM9 26H COM38 COM10
D7 27H COM39 COM8 27H COM39 COM9
D0 28H COM40 COM7 28H COM40 COM8
D1 29H COM41 COM6 29H COM41 COM7
D2 2AH COM42 COM5 2AH COM42 COM6
D3 Page 5 2BH COM43 COM4 2BH COM43 COM5
0 1 0 1 COM44 COM3 COM44 COM4
D4 2CH 2CH
D5 2DH COM45 COM2 2DH COM45 COM3
D6 2EH COM46 COM1 2EH COM46 COM2
D7 2FH COM47 COM0 2FH COM47 COM1
D0 30H 30H COM48 COM0
D1 31H 31H
D2 32H 32H
0 1 0 D3 Page 6 33H 33H
1
D4 34H 34H
D5 35H 35H
D6 36H 36H
D7 37H 37H
D0 38H 38H
D1 39H 39H
D2 3AH 3AH
0 1 1 1 D3 Page 7 3BH 3BH
D4 3CH 3CH
D5 3DH 3DH
D6 3EH 3EH
D7 3FH 3FH
D0 40H COM64 COM64 40H
D1 Page 8 41H 41H
1 0 0 0 D2 42H 42H
D3 43H 43H
Column address 00H 01H 02H 03H 04H 05H 06H 59H 5AH 5BH 5CH 5DH 5EH 5FH Display start line does not access 65th, 66th, 67th, 68th line
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
32/62
STE2007 Display Data RAM (DDRAM)
ICONMODE="1" ICONMODE="0"
Page addressD COM Output COM Output
a Line Line
D3 D2 D1 D0 at Address Normal Reverse Address Normal Reverse
direction direction direction direction
D0 00H COM0 COM31 00H COM0 COM32
D1 01H COM1 COM30 01H COM1 COM31
D2 02H COM2 COM29 02H COM2 COM30
D3 Page 0 03H COM3 COM28 03H COM3 COM29
0 0 0 0
D4 04H COM4 COM27 04H COM4 COM28
D5 05H COM5 COM26 05H COM5 COM27
D6 06H COM6 COM25 06H COM6 COM26
D7 07H COM7 COM24 07H COM7 COM25
D0 08H COM8 COM23 08H COM8 COM24
D1 09H COM9 COM22 09H COM9 COM23
D2 0AH COM10 COM21 0AH COM10 COM22
D3 Page 1 0BH COM11 COM20 0BH COM11 COM21
0 0 0 1
D4 0CH COM12 COM19 0CH COM12 COM20
D5 0DH COM13 COM18 0DH COM13 COM19
D6 0EH COM14 COM17 0EH COM14 COM18
D7 0FH COM15 COM16 0FH COM15 COM17
D0 10H COM16 COM15 10H COM16 COM16
D1 11H COM17 COM14 11H COM17 COM15
D2 12H COM18 COM13 12H COM18 COM14
D3 Page 2 13H COM19 COM12 13H COM19 COM13
0 0 1 0
D4 14H COM20 COM11 14H COM20 COM12
D5 15H COM21 COM10 15H COM21 COM11
D6 16H COM22 COM9 16H COM22 COM10
D7 17H COM23 COM8 17H COM23 COM9
D0 18H COM24 COM7 18H COM24 COM8
D1 19H COM25 COM6 19H COM25 COM7
D2 1AH COM26 COM5 1AH COM26 COM6
0 0 1 1 D3 Page 3 1BH COM27 COM4 1BH COM27 COM5
D4 1CH COM28 COM3 1CH COM28 COM4
D5 1DH COM29 COM2 1DH COM29 COM3
1EH Start COM30 COM1 1EH Start COM30 COM2
D6
D7 1FH COM31 COM0 1FH COM31 COM1
D0 20H 20H COM32 COM0
D1 21H 21H
D2 22H 22H
0 0 0 D3 Page 4 23H 23H
1
D4 24H 24H
D5 25H 25H
D6 26H 26H
D7 27H 27H
D0 28H 28H
D1 29H 29H
D2 2AH 2AH
0 D3 Page 5 2BH 2BH
0 1 1
D4 2CH 2CH
D5 2DH 2DH
D6 2EH 2EH
D7 2FH 2FH
D0 30H 30H
D1 31H 31H
D2 32H 32H
0 1 0 D3 Page 6 33H 33H
1
D4 34H 34H
D5 35H 35H
D6 36H 36H
D7 37H 37H
D0 38H 38H
D1 39H 39H
D2 3AH 3AH
D3 Page 7 3BH 3BH
0 1 1 1 D4 3CH 3CH
D5 3DH 3DH
D6 3EH 3EH
D7 3FH 3FH
D0 40H COM64 COM64 40H
D1 Page 8 41H 41H
1 0 0 0 D2 42H 42H
D3 43H 43H
Column address 00H 01H 02H 03H 04H 05H 06H 59H 5AH 5BH 5CH 5DH 5EH 5FH Display start line does not access 65th, 66th, 67th, 68th line
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
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Display Data RAM (DDRAM) STE2007
Display Display
When Partial Display Mode is enabled the user has to Update the Operative Voltage, Bias
Ratio and Charge Pump Setting to match the new working conditions.
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
34/62
STE2007 Display Data RAM (DDRAM)
ICONMODE="1" ICONMODE="0"
Display start line does not access 65th, 66th, 67th, 68th line
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
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Display Data RAM (DDRAM) STE2007
ICONMODE="1" ICONMODE="0"
Page addressD COM Output COM Output
a Line Line
D3 D2 D1 D0 at Address Normal Reverse Address Normal Reverse
direction direction direction direction
D0 00H COM0 COM63 00H COM0 COM64
D1 01H COM1 COM62 01H COM1 COM63
D2 02H COM2 COM61 02H COM2 COM62
D3 Page 0 03H COM3 COM60 03H COM3 COM61
0 0 0 0
D4 04H COM4 COM59 04H COM4 COM60
D5 05H COM5 COM58 05H COM5 COM59
D6 06H COM6 COM57 06H COM6 COM58
D7
D0
07H
08H
IL[2:0] COM7
COM8
COM56
COM55
07H
08H
IL[2:0] COM7
COM8
COM57
COM56
D1 09H COM9 COM54 09H COM9 COM55
D2 0AH COM10 COM53 0AH COM10 COM54
D3 Page 1 0BH COM11 COM52 0BH COM11 COM53
0 0 0 1
D4 0CH COM12 COM51 0CH COM12 COM52
D5 0DH COM13 COM50 0DH COM13 COM51
D6 0EH COM14 COM49 0EH COM14 COM50
D7 0FH COM15 COM48 0FH COM15 COM49
D0 10H COM16 COM47 10H COM16 COM48
D1 11H COM17 COM46 11H COM17 COM47
D2 12H COM18 COM45 12H COM18 COM46
D3 Page 2 13H COM19 COM44 13H COM19 COM45
0 0 1 0
D4 14H COM20 COM43 14H COM20 COM44
D5 15H COM21 COM42 15H COM21 COM43
D6 16H COM22 COM41 16H COM22 COM42
D7 17H COM23 COM40 17H COM23 COM41
D0 18H COM24 COM39 18H COM24 COM40
D1 19H COM25 COM38 19H COM25 COM39
D2 1AH COM26 COM37 1AH COM26 COM38
D3 Page 3 1BH COM27 COM36 1BH COM27 COM37
0 0 1 1
D4 1CH COM28 COM35 1CH COM28 COM36
D5 1DH COM29 COM34 1DH COM29 COM35
1EH Start COM30 COM33 Start
D6 1EH COM30 COM34
(25)
1FH COM31 COM32
Partial Display Area
(24 +1)
IMAGE lOCATION (IL[2:0]) + Partial display Area Width (19hex) <= Multiplexing Rate (40hex)
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
36/62
STE2007 Display Data RAM (DDRAM)
ICONMODE="1" ICONMODE="0"
Page addressD COM Output COM Output
a Line Line
D3 D2 D1 D0 at Address Normal Reverse Address Normal Reverse
direction direction direction direction
D0 00H COM0 COM63 00H COM0 COM64
D1 01H COM1 COM62 01H COM1 COM63
D2 02H COM2 COM61 02H COM2 COM62
D3 Page 0 03H COM3 COM60 03H COM3 COM61
0 0 0 0
D4 04H COM4 COM59 04H COM4 COM60
D5 05H COM5 COM58 05H COM5 COM59
D6 06H COM6 COM57 06H COM6 COM58
D7
D0
07H
08H
IL[2:0] COM7
COM8
COM56
COM55
07H
08H
IL[2:0] COM7
COM8
COM57
COM56
D1 09H COM9 COM54 09H COM9 COM55
D2 0AH COM10 COM53 0AH COM10 COM54
D3 Page 1 0BH COM11 COM52 0BH COM11 COM53
0 0 0 1
D4 0CH COM12 COM51 0CH COM12 COM52
D5 0DH COM13 COM50 0DH COM13 COM51
D6 0EH COM14 COM49 0EH COM14 COM50
D7 0FH COM15 COM48 0FH COM15 COM49
D0 10H COM16 COM47 10H COM16 COM48
D1 11H COM17 COM46 11H COM17 COM47
D2 12H COM18 COM45 12H COM18 COM46
D3 Page 2 13H COM19 COM44 13H COM19 COM45
0 0 1 0
D4 14H COM20 COM43 14H COM20 COM44
D5 15H COM21 COM42 15H COM21 COM43
D6 16H COM22 COM41 16H COM22 COM42
D7 17H COM23 COM40 17H COM23 COM41
D0 18H COM24 COM39 18H COM24 COM40
D1 19H COM25 COM38 19H COM25 COM39
D2 1AH COM26 COM37 1AH COM26 COM38
D3 Page 3 1BH COM27 COM36 1BH COM27 COM37
0 0 1 1
D4 1CH COM28 COM35 1CH COM28 COM36
D5 1DH COM29 COM34 1DH COM29 COM35
Partial Display
Partial Display
Start Start
Area (16+1)
Area (17)
D0 20H COM32 COM31 20H COM32 COM32
D1 21H COM33 COM30 21H COM33 COM31
D2 22H COM34 COM29 22H COM34 COM30
D3 Page 4 23H COM35 COM28 23H COM35 COM29
0 1 0 0 COM36 COM27
D4 24H 24H COM36 COM28
D5 25H COM37 COM26 25H COM37 COM27
D6 26H COM38 COM25 26H COM38 COM26
D7 27H COM39 COM24 27H COM39 COM25
D0 28H COM40 COM23 28H COM40 COM24
D1 29H COM41 COM22 29H COM41 COM23
D2 2AH COM42 COM21 2AH COM42 COM22
D3 Page 5 2BH COM43 COM20 2BH COM43 COM21
0 1 0 1 COM44 COM19
D4 2CH 2CH COM44 COM20
D5 2DH COM45 COM18 2DH COM45 COM19
D6 2EH COM46 COM17 2EH COM46 COM18
D7 2FH COM47 COM16 2FH COM47 COM17
D0 30H COM48 COM15 30H COM48 COM16
D1 31H COM49 COM14 31H COM49 COM15
D2 32H COM50 COM13 32H COM50 COM14
D3 Page 6 33H COM51 COM12 33H COM51 COM13
0 1 1 0 COM52 COM11
D4 34H 34H COM52 COM12
D5 35H COM53 COM10 35H COM53 COM11
D6 36H COM54 COM9 36H COM54 COM10
D7 37H COM55 COM8 37H COM55 COM9
D0 38H COM56 COM7 38H COM56 COM8
D1 39H COM57 COM6 39H COM57 COM7
D2 3AH COM58 COM5 3AH COM58 COM6
D3 Page 7 3BH COM59 COM4 3BH COM59 COM5
0 1 1 1 COM60 COM3
D4 3CH 3CH COM60 COM4
D5 3DH COM61 COM2 3DH COM61 COM3
D6 3EH COM62 COM1 3EH COM62 COM2
D7 3FH COM63 COM0 3FH COM63 COM1
D0 40H COM64 COM64 40H COM64 COM0
D1 Page 8 41H 41H
1 0 0 0 D2 42H 42H
D3 43H 43H
Column address 00H 01H 02H 03H 04H 05H 06H 59H 5AH 5BH 5CH 5DH 5EH 5FH Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
37/62
Display Data RAM (DDRAM) STE2007
ICONMODE="1" ICONMODE="0"
Page address D COM Output COM Output
a Line Line
D3 D2 D1 D0 at Address Normal Reverse Address Normal Reverse
direction direction direction direction
D0 00H COM0 COM63 00H COM0 COM64
D1 01H COM1 COM62 01H COM1 COM63
D2 02H COM2 COM61 02H COM2 COM62
D3 Page 0 03H COM3 COM60 03H COM3 COM61
0 0 0 0
D4 04H COM4 COM59 04H COM4 COM60
D5 05H COM5 COM58 05H COM5 COM59
D6 06H COM6 COM57 06H COM6 COM58
D7
D0
07H
08H
IL[2:0] COM7
COM8
COM56
COM55
07H
08H
IL[2:0] COM7
COM8
COM57
COM56
D1 09H COM9 COM54 09H COM9 COM55
D2 0AH COM10 COM53 0AH COM10 COM54
D3 Page 1 0BH COM11 COM52 0BH COM11 COM53
0 0 0 1
D4 0CH COM12 COM51 0CH COM12 COM52
D5 0DH COM13 COM50 0DH COM13 COM51
D6 0EH COM14 COM49 0EH COM14 COM50
D7 0FH COM15 COM48 0FH COM15 COM49
D0 10H COM16 COM47 10H COM16 COM48
D1 11H COM17 COM46 11H COM17 COM47
D2 12H COM18 COM45 12H COM18 COM46
D3 Page 2 13H COM19 COM44 13H COM19 COM45
0 0 1 0
D4 14H COM20 COM43 14H COM20 COM44
D5 15H COM21 COM42 15H COM21 COM43
D6 16H COM22 COM41 16H COM22 COM42
D7 17H COM23 COM40 17H COM23 COM41
D0 18H COM24 COM39 18H COM24 COM40
D1 19H COM25 COM38 19H COM25 COM39
D2 1AH COM26 COM37 1AH COM26 COM38
D3 Page 3 1BH COM27 COM36 1BH COM27 COM37
0 0 1 1
D4 1CH COM28 COM35 1CH COM28 COM36
Partial Display
Partial Display
D6 1EH COM30 COM33 1EH COM30 COM34
COM31 COM32
Area (9)
D7 1FH 1FH COM31 COM33
D0 20H COM32 COM31 20H COM32 COM32
D1 21H COM33 COM30 21H COM33 COM31
22H Start COM34 COM29 Start COM34 COM30
D2 22H
D3 Page 4 23H COM35 COM28 23H COM35 COM29
0 1 0 0 COM36 COM27
D4 24H 24H COM36 COM28
D5 25H COM37 COM26 25H COM37 COM27
D6 26H COM38 COM25 26H COM38 COM26
D7 27H COM39 COM24 27H COM39 COM25
D0 28H COM40 COM23 28H COM40 COM24
D1 29H COM41 COM22 29H COM41 COM23
D2 2AH COM42 COM21 2AH COM42 COM22
D3 Page 5 2BH COM43 COM20 2BH COM43 COM21
0 1 0 1 COM44 COM19
D4 2CH 2CH COM44 COM20
D5 2DH COM45 COM18 2DH COM45 COM19
D6 2EH COM46 COM17 2EH COM46 COM18
D7 2FH COM47 COM16 2FH COM47 COM17
D0 30H COM48 COM15 30H COM48 COM16
D1 31H COM49 COM14 31H COM49 COM15
D2 32H COM50 COM13 32H COM50 COM14
D3 Page 6 33H COM51 COM12 33H COM51 COM13
0 1 1 0 COM52 COM11
D4 34H 34H COM52 COM12
D5 35H COM53 COM10 35H COM53 COM11
D6 36H COM54 COM9 36H COM54 COM10
D7 37H COM55 COM8 37H COM55 COM9
D0 38H COM56 COM7 38H COM56 COM8
D1 39H COM57 COM6 39H COM57 COM7
D2 3AH COM58 COM5 3AH COM58 COM6
D3 Page 7 3BH COM59 COM4 3BH COM59 COM5
0 1 1 1 COM60 COM3
D4 3CH 3CH COM60 COM4
D5 3DH COM61 COM2 3DH COM61 COM3
D6 3EH COM62 COM1 3EH COM62 COM2
D7 3FH COM63 COM0 3FH COM63 COM1
D0 40H COM64 COM64 40H COM64 COM0
D1 Page 8 41H 41H
1 0 0 0 D2 42H 42H
D3 43H 43H
Column address 00H 01H 02H 03H 04H 05H 06H 59H 5AH 5BH 5CH 5DH 5EH 5FH Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
S S S S S S S S S S S S S S
Normal E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
SEG 0 1 2 3 4 5 6 89 90 91 92 93 94 95
Output S S S S S S S S S S S S S S
Reverse E E E E E E E E E E E E E E
Direction G G G G G G G G G G G G G G
95 94 93 92 91 90 89 6 5 4 3 2 1 0
38/62
STE2007 Display Data RAM (DDRAM)
39/62
Instruction setups STE2007
6 Instruction setups
Reset status
40/62
STE2007 Power on/power off timing sequence
Figure 34 shows the timing diagram for power on/power down sequences.
Figure 34. Timing for phone’s power on sequence when VDD,VDDCP Up before VDDI
VDDI
VDD
tpi >0µs tpi >0µs
Inputs
High-Z High-Z
Outputs
tcs >0µs
tcs >0µs
!CS
tPWROFF1 >0 ms
tPWROFF2 >20ms
tp2 >0µs
!RES
trs = max. 5µs
INTERNAL
RESET Trs = max. 5µs
Reset State Reset State
Figure 35. Timing for phone’s power on sequence when VDDI Up before VDD
tp1 < 0 tp1 < 0
VDDI
VDD
tpi >0µs tpi >0µs
SDAIN
High-Z High-Z
SDAOUT
tcs >0µs
tcs >0µs
!CS
tPWROFF1 >0 ms
tPWROFF2 >20ms
tp2 >0µs
!RES
trs = max. 5µs
INTERNAL
RESET Trs = max. 5µs
Reset State Reset State
41/62
Power on/power off timing sequence STE2007
0 AE LCD display
Display ON/OFF 0 1 0 1 0 1 1 1
1 AF 0: OFF, 1: ON
42/62
STE2007 Power on/power off timing sequence
0 0 0 1 1 1 1 0 1 3D
Sets the Charge Pump Mux Factor
Charge Pump Charge
0 * * * * * *
Pump
0 1 1 1 0 1 1 1 1 EF Sets the Display Refresh
Refresh Rate Refersh Frequency
0 * * * * * *
Rate
Bias ratio 0 0 0 1 1 0 Bias Ratio Sets the VLCD
0 1 0 1 0 1 1 0 1 AD
N-line Inversion
0 * * F1 N-Line Inversion
Number of Lines 0 1 1 0 1 0 Mux Rate
0 1 0 1 0 1 1 0 0 AC SET Initial Row on Display
Image Location
0 * * * * * IL[2:0]
Ico
Icon Mode 0 1 1 1 1 1 0 0
n
0 1 0 1 0 1 0 0 1 A9 Reserved for STM (STM Test
STM TEST MODE1
0 * * * * * * * * Mode)
* = Disabled bits.
43/62
Commands STE2007
8 Commands
0 1 0 1 0 1 1 1 0 AE Display OFF
0 1 AF Display ON
When the Display OFF command is executed in the Display all points ON mode, Power
saver mode is entered. See the section on the Power saver for details.
When the Display all points ON command is executed when in the Display OFF mode,
Power saver mode is entered. See the section on the Power Saver for details.
44/62
STE2007 Commands
0 1 0 1 1 0 0 0 0 B0 0H
0 0 0 0 1 B1 1H
0 0 0 1 0 B2 2H
0 : : :
0 1 0 0 0 B8 8H
* Disabled bit
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 0 0 1 01H
0 0 0 0 0 0 1 0 02H
. .
. .
0 1 0 1 1 1 1 0 5EH
0 1 0 1 1 1 1 1 5FH
45/62
Commands STE2007
0 0 1 0 0 0 0 0 0 40 0H
0 0 1 0 0 0 0 0 1 41 1H
0 0 1 0 0 0 0 1 0 42 2H
: : :
0 0 1 1 1 1 1 1 0 7E 3EH
0 0 1 1 1 1 1 1 1 7F 3FH
Display start line assress con be used in partial dispaly mode to relocate the partial display
window on the screen.
Display start line + Partial Display area with must be smaller or equal to the number of line
selected.
0 1 0 1 0 0 0 0 0 A0 Normal
0 1 A1 Reverse
0 1 1 0 0 0 * * * Normal
1 * * * Reverse
* Disabled bit
46/62
STE2007 Commands
1 Write Data
0 1 1 0 1 1 0 1 1 DB Reads ID byte
0 0 0 IDB IDA 0 0 0 0 Pad Default
0 0 0 1 0 1 0 0 0 28
0 0 0 1 29
0 0 1 0 2A Booster : OFF
0 0 1 1 2B Voltage Regulator:OFF
0 1 0 0 2C Voltage Follower : OFF
0 1 0 1 2D
0 1 1 0 2E
Booster : ON
0 1 1 1 2F Voltage regulator : ON
Voltage follower : ON
47/62
Commands STE2007
Figure 36.
Vout
13.20V
EV[3:0] 1Fh
12h
11h
10h
00h
VOP[7:0]*B+V-OR
3V 00h
FFh
Figure 37.
V0R[2:0] EV[4:0]
Thermal
DAC VOUT
Compensation
Step: 40mV
Range 3V-13.20V
48/62
STE2007 Commands
0 0 0 1 0 0 0 0 0 20 0 3.00 V
0 0 0 1 21 1 4.28 V
0 0 1 0 22 2 5.56 V
0 0 1 1 23 3 6.84 V
0 1 0 0 24 4 8.12 V (Default)
0 1 0 1 25 5 9.40 V
0 1 1 0 26 6 10.68 V
0 1 1 1 27 7 11.96 V
0 1 1 1 0 0 0 0 1 E1 Command Identifier
0 VOP7 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 Data Field
0 0 0 0 0 0 0 0 00 0 Step (Default)
0 0 0 0 0 0 0 1 01 +1 Step
0 0 0 0 0 0 1 0 02 +2 Step
: : : : : : : : : :
0 1 1 1 1 1 1 1 7F +127 Step
1 0 0 0 0 0 0 0 80 0 Step
1 0 0 0 0 0 0 1 81 -1 Step
: : : : : : : : : :
1 1 1 1 1 1 0 1 FD -125 Step
1 1 1 1 1 1 1 0 FE -126 Step
1 1 1 1 1 1 1 1 FF -127 Step
49/62
Commands STE2007
Table 35. EV
(D/C) D7 D6 D5 D4 D3 D2 D1 D0 Hex EV Value VLCD voltage
0 1 0 0 0 0 0 0 0 80 0 Step low
0 0 0 0 0 1 81 1 Step
0 0 0 0 1 0 82 2 Step
: : : : :
0 1 0 0 0 0 90 16 Step (Default)
: : : : :
0 1 1 1 1 0 9E 30 Step
0 1 1 1 1 1 9F 31 Step high
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STE2007 Commands
8.14 Reset
When this command is issued, the driver is initialized.This command doesn’t change
DDRAM content.
0 1 1 1 0 0 0 1 0 E2 Command Identifier
8.15 NOP
Non–operation command.
0 1 1 1 0 0 0 1 1 E3 Command Identifier
0 1 0 1 0 1 1 0 0 AC Command Identifier
0 * * * * * IL2 IL1 IL0 Data Field
0 0 0 0 Lines
0 0 1 8 Lines
0 1 0 16 Lines
0 1 1 24 Lines
1 0 0 32 Lines
1 0 1 48 Lines
1 1 0 56 Lines
1 1 1 64 Lines
51/62
Commands STE2007
R R R R
9 8 7 6
·VLCD ·VLCD ·VLCD ·VLCD
10 9 8 7
R R R R
8 7 6 5
·VLCD ·VLCD ·VLCD ·VLCD
10 9 8 7
6R 5R 4R 3R
2 2 2 2
·VLCD ·VLCD ·VLCD ·VLCD
10 9 8 7
R R R R
1 1 1 1
·VLCD ·VLCD ·VLCD ·VLCD
10 9 8 7
R R R R
R R R
5 4 3
·VLCD ·VLCD ·VLCD
6 5 4
R R R
4 3 2
·VLCD ·VLCD ·VLCD
6 5 4
2R 1R 4R
2 2 2
·VLCD ·VLCD ·VLCD
6 5 4
R R R
1 1 1
·VLCD ·VLCD ·VLCD
6 5 4
R R R
52/62
STE2007 Commands
0 0 0 1 1 1 0 0 0 38 Command Identifier
Thermal
0 * * * * * Compensation Data Field
TC
Table 43. TC
TC2 TC1 TC0 TC Value
0 0 0 TC= 0 PPM
0 0 1 TC= -300 PPM
0 1 0 TC= -600 PPM
0 1 1 TC= -900 PPM
1 0 0 TC= -1070 PPM
1 0 1 TC= -1200 PPM
1 1 0 TC= -1500 PPM
1 1 1 TC= -1800 PPM
0 0 0 1 1 1 1 0 1 3D Command Identifier
0 * * * * * * CP1 CP0 Data Field
53/62
Commands STE2007
0 0 5x
0 1 4x
1 0 3x
1 1 Not Used
0 1 1 1 0 1 1 1 1 EF Command Identifier
0 * * * * * * RR1 RR0 Data Field
0 1 0 1 0 1 1 0 1 AD Command Identifier
0 * * F1 NL4 NL3 NL2 NL1 NL0 Data Field
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STE2007 Pad coordinates
The XOR function defines the polarity as the result of the logical XOR between the N-Line
and the frame polarity.
0 0 0 68 Lines (Default)
0 0 1 65 Lines
0 1 0 49 Lines
0 1 1 33 Lines
1 0 0 33 Lines Partial Display
1 0 1 25 Lines Partial Display
1 1 0 17 Lines Partial Display
1 1 1 9 Lines Partial Display
9 Pad coordinates
See Table 53: Pad coordinates and Table 55: Alignment marks coordinates.
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Pad coordinates STE2007
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STE2007 Pad coordinates
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Pad coordinates STE2007
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STE2007 Pad coordinates
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Chip mechanical drawing STE2007
35 µm
85 µm
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STE2007 Ordering information
11 Ordering information
12 Revision history
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STE2007
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