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Small Time-Step Simulation

An Introductory Tutorial
Rev 01

BRDG1

1 3 5

2 4 6
TABLE OF CONTENTS

1 INTRODUCTION ....................................................................................................................... 3
2 SMALL TIME-STEP SIMULATION BASICS .................................................................................. 4
3 SIMPLE VOLTAGE RECTIFIER .................................................................................................... 9
4 SIMPLE STATCOM EXAMPLE .................................................................................................. 17
5 INTERFACING LARGE AND SMALL TIME-STEP SIMULATIONS ............................................... 36
6 CONNECTING VSC BRIDGE BOXES USING SMALL TIME-STEP TRANSMISSION LINES............ 42
7 SMALL TIME-STEP IO ............................................................................................................. 48
8 SELECTING VALVE PARAMETERS ........................................................................................... 56
9 DISTRIBUTING PROCESSING LOAD OVER TWO PROCESSORS ............................................... 62
10 REFERENCES ....................................................................................................................... 64

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1 INTRODUCTION

Typical time-steps for EMTP type simulations are on the order of 50 microseconds. Such time-
steps, however, are not sufficiently small to allow for the accurate simulation of high frequency
switching circuits such as those used in PWM schemes. In order to model such schemes a feature
known as small time-step simulation was introduced into RSCAD. Small time-step simulation uses
several ‘shortcuts’ in order to reduce the time-step down to somewhere in the neighbourhood
of 1.5 to 2.5 microseconds. The actual time-step is not directly controlled by the user but is a
function of the complexity of the circuit being simulated. The aim of this tutorial is to familiarize
the user with the small time-step simulation feature of the RTDS Simulator.

This tutorial is broken up into several parts. In section 2 some of the basic theory behind small
time-step simulation is provided. Next, some of the details involved in building a small time-step
case are shown; this is done primarily by means of example. First a simple voltage rectifier is built
in section 3 and then a simplified STATCOM is assembled in section 4. The aim of sections 3 and
4 is to assist the reader in assembling a working simulation case. Sections 5 through 9 will
introduce some more advanced topics. Section 5 details how a small time-step simulation circuit
can be interfaced with a large time-step circuit. Section 6 will explain how to increase the size of
a circuit simulated using the small time-step simulation facility. Section 7 deals with importing
and exporting digital and analog signals into and out of the simulation. Section 8 discusses
strategies for how to go about selecting the valve parameters. Finally, in section 9, details are
given on how to spread the processing load of the small time-step simulation over multiple
processors.

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2 SMALL TIME-STEP SIMULATION BASICS

In order to understand small time-step simulation it is important to understand some


fundamentals about the core solution algorithm used by the RTDS Simulator. Consider the simple
circuit of Figure 2.1A for a moment. It consists of a source and three series connected
conductances (g1, g2 and g3). If the source and g1 are converted to their Norton equivalent the
circuit can be redrawn as shown in the adjacent figure of 2.1B. The labels V1 and V2 are added to
the circuit; our objective is to solve for these voltages.

g1 g2 V1 g2
V2

+ +
g3 g1 g3
V(t) g1V(t)
- -

(A) (B)

Figure 2.1: Simple circuit used to demonstrate RTDS solution algorithm

Kirchhoff’s Current Law (KCL) can be used to write the nodal equations at V1 and V2. This results
are in Eq. 2.1 and Eq. 2.2.

𝑉1 𝑔1 + (𝑉1 − 𝑉2 )𝑔2 = 𝑔1 𝑉(𝑡) [ Eq. 2.1 ]

𝑉2 𝑔3 + (𝑉2 − 𝑉1 )𝑔2 = 0 [ Eq. 2.2 ]

These equations can be re-written in matrix form as shown in Eq. 2.3.

𝑔 +𝑔 −𝑔2 𝑉1 𝑔1 𝑉(𝑡)
[ 1−𝑔 2 𝑔2 + 𝑔3 𝑉2 ] = [ 0 ]
] [ [ Eq. 2.3 ]
2

Solving for the node voltages V1 and V2 leads to Eq. 2.4 or equivalently Eq. 2.5.

𝑉 𝑔 +𝑔 −𝑔2 −1 𝑔1 𝑉(𝑡)
[ 1 ] = [ 1−𝑔 2 𝑔2 + 𝑔3 ] [ 0 ] [ Eq. 2.4 ]
𝑉2 2

[𝑉] = [𝐺]−1 [𝐼] [ Eq. 2.5 ]

The voltages at both nodes can be calculated if the voltage source signal, V(t), along with the
conductances g1, g2 and g3 are known. Eq. 2.5 is a very simplified summary of calculations carried

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out by the RTDS Simulator. In the equations above, G is known as the conductance matrix. In
general a circuit with N single phase nodes will lead to a conductance matrix of N x N dimension.

Without proof it is stated that passive elements such as inductors and capacitors can be modeled
as current sources connect in parallel with conductances. Figure 2.2 shows the equivalent circuits
for inductors and capacitors.

+ +
iL(t) iL(t) iC(t) iC(t)
+ +
vL(t) L vL(t) gL IHL vC (t) vC(t) gC IHC
- -
- -

(A) (B)

Figure 2.2 : Equivalent Circuits for (A) Inductor and (B) Capacitor

Furthermore, complicated elements such as Transformers, Transmission lines and Generators


can also generally be modeled as current sources connected in parallel with a conductance. Once
all the elements in a circuit are converted to a parallel conductance and current source, KCL can
again be written for each of the nodes in the circuit and an equation similar in form to that of Eq.
2.5 can be written. This is the general approach that the RTDS Simulator uses. The true
complication comes in trying to accurately model the behaviour of physical devices by modeling
them as a parallel connected current source and conductance.

One of the primary uses of the RTDS Simulator is its ability to study the transient behaviour of
powers systems. It is important to understand how a power system responds when a breaker
opens/closes, when a fault occurs or is cleared or when a power electronic device misfires.
Fortunately, the framework developed above can easily accommodate simulation of these
conditions/scenarios.

Consider the circuit of Figure 2.3A which contains two series connected resistances and a switch
which can open or close. A switch can be modeled fundamentally as a conductance which is small
when the switch is open and large when the switch is closed. Given this realization the circuit of
Figure 2.3A can be rewritten as shown in Figure 2.3B. This circuit is identical to the circuit
developed in Figure 2.1A thus the node voltages can be solved for using Eq. 2.5. The primary
difference will be that the conductance matrix, G, will evolve with time. When the switch is in an
open state the conductance g3 will be small, conversely when the switch is in a closed state g3
will be large. A time-varying conductance can just as easily be used to model a fault, or a power
electronic switch.

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R1 V1 R2 V2 g1 V1 g2 V2

+ +
S1 g3
V(t) V(t
- -

(A) (B)

Figure 2.3: Circuit demonstrating the modeling of switches in large time-step simulations

The Challenge...
Anytime the switching state of the circuit changes, the G-matrix changes. Whenever the G-matrix
changes, its inverse will also need to be recalculated. Unfortunately, the number of operations
needed to invert an N x N matrix increases exponentially with N. Currently the effective inversion
of a 66 node G matrix takes on the order of 50s. Given the real-time constraint applied to the
RTDS Simulator, it is not difficult to imagine that a 25 fold increase in processing power would be
needed in order to use the above described method to model switches with the 2s time-step
range necessary to accurately model some power electronic circuits. This is the challenge that
must be overcome in order to complete a real-time electromagnetic simulation using a time-step
on the order of 2s.

The Solution...
Given the challenges listed above, an alternate method for modeling a switch is needed. Instead
of modeling an open circuit as a small conductance, it will be modeled as a series connected
resistor and capacitor. Also, instead of modeling a short circuit as a large conductance, it will be
modeled as an inductor.

Short Circuit: Open Circuit:

+ +
iSC (t) + iOC(t) ioc(t)
isc(t)
+

vsc(t) vOC (t) voc(t) goc IHoc


vSC (t) L gsc IHsc

- -
- -

(A) (B)

Figure 2.4: Equivalent circuits used to represent (A) Short Circuit and
(B) Open Circuit in the small-time step simulation.
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It is possible, again without proof, to simplify the circuits chosen to represent a short circuit and
an open circuit into equivalent parallel connected current sources and conductances. Figure 2.4A
and Figure 2.4B show the small time-step representations for a short circuit and an open circuit
respectively. These representations can easily be incorporated into the above discussed
formulation used to solve for node voltages. Changing the state of a switch now involves two
possible changes. First gsc is changed to goc or vice versa; secondly, IHsc is changed to IHoc or vice
versa. Up to this point one approximation of an open circuit and another for a short circuit has
been proposed but neither the validity nor the advantages of such approximations have been
discussed.

The validity of the approximation is the most pressing concern; the values of R and C must be
selected so that together they represent a fairly large impedance across the system bandwidth.
Similarly, L must be selected so that it represents a fairly small impedance across the system. If
these criteria are not met then the chosen approximations for a short circuit and an open circuit
are invalid and there is no point in continuing with this approach. Fortunately, it is possible to
choose R, C and L to meet these constraints.

In addition to being selected so that the constraints above are met, the parameters R, L and C
can also be chosen in such a way that gsc and goc are equal. If gsc equals goc then the conductance
matrix of the system being simulated will not change when the state of a switch changes. This in
turn implies that the conductance matrix remains constant throughout the entire simulation and
that it does not need to be re-inverted when a switching event occurs. Only the values of IHsc and
IHoc need to be recalculated. This approach results in huge computational savings and is the
primary reason the time-step can be reduced to within the 1.5 – 2.5s range.

There are, however, disadvantages to this approach. The problem lies in the fact that open and
short circuits are being represented using capacitors and inductors, both energy storage devices.
In either of the two states a small amount of energy from the system will be stored, something
which does not occur when using a pure conductance to represent the open and short circuited
conditions. Upon the occurrence of a switching event one circuit representation is abruptly
changed to the other and in doing this, the small amount of energy that was stored in the
previous switching state is effectively discarded. This is an artificial energy loss that is introduced
by the modeling method and the total energy loss increases as the number of switching events
increases. Switches modeled in the above described manner can be operated up to about 3 kHz
without problem but beyond this frequency the artificial losses become unrealistic. Some of the
small time-step models can be switched at increased rates of up to 12 kHz but these switches
have been modeled using the traditional method and are mathematically decoupled from the
small time-step G-matrix. This will be discussed later in this tutorial.

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What has been presented so far was intended to give the user a basic understanding of the
fundamentals of small time-step simulation; further details about the above described
approaches can be found in [1]. In the next section, a simple voltage rectifier circuit will be
assembled using the RTDS Simulator’s small time-step simulation facilities.

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3 SIMPLE VOLTAGE RECTIFIER

In this section a simple voltage rectifier will be assembled and simulated using the small time-
step functionality of the RTDS Simulator. The topology of the circuit will be similar to that shown
in Figure 3.1. Since switching will only occur at power system frequency this is not an example of
the type of circuit that would typically need to be studied using small time-step simulations, but
construction of this circuit is instructive nevertheless and serves as a good starting point.

Figure 3.1: Simple voltage rectifier circuit to be assembled.

VSC Bridge Box


In order to build a small time-step simulation case the first thing that must be done is to add a
special hierarchy box into the DRAFT case. This special hierarchy box is known as a VSC Bridge
Box and appears as shown in Figure 3.2. Any circuit which is to be simulated using a small time-
step must be assembled inside a VSC Bridge Box. In general, only small time-step components
can be placed inside the VSC bridge box; large time-step component will not work using a small
time-step. The Master library contains a tab labelled Small_dt which contains a collection of small
time-step models. Although control compiler components can be placed within a VSC bridge box
without generating a compile error, they are nonetheless simulated using the large time-step.

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Figure 3.2: Icon for the small time-step bridge box.

Double-clicking on a VSC bridge box allows its contents to be edited in the same manner that the
contents of a hierarchy box can be modified. Right-clicking on the VSC bridge box and selecting
Edit->Parameters opens the parameter menu; Figure 3.3 shows the parameter menu for the
small time-step bridge box. Some of these parameters will be described later in this tutorial but
additional details can be found in the ‘VSC Small Time-Step Modelling’ Chapter of the manual.

Figure 3.3: Parameter menu for the rtds_vsc_BRIDGE_BOX

Voltage Rectifier Circuit


Inside the VSC bridge box the circuit of Figure 3.4 should be constructed. It is a simple voltage
rectifier where the diode bridge has been replaced by a GTO bridge with anti-parallel diodes. If
firing pulses for the GTOs are not provided then the GTO bridge effectively becomes a diode
bridge. The load on the DC bus will be a 100Ω resistance and the source impedance will be a 1Ω
resistance. The six GTOs with anti-parallel diodes are a single component named
rtds_vsc_PH3LEV2 which can be found in the small time-step library in the ‘2 & 3 LEVEL VSC’ box.

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Figure
When building small time-step circuits 3.4: DRAFT
one component thatmodel
is very of rectifier
useful circuit
is the rtds_vsc_BRC3 branch component.

This component is highly customizable and can be used to model R, L, C, RL, RC, RRL and high
pass filter branches. The number of branches per component can be varied between one and
three and they can be positioned either inline or in parallel. It is also possible to include a
controlled voltage source in the branch by setting the vsrc parameter to Yes as shown in Figure
3.5. The shape and magnitude of the voltages follow that of the controls compiler signals
referenced under the NAMES FOR REAL/INT VOLTAGE SOURCE INPUTS tab.

Figure 3.5: Adding voltage sources to a branch component

The AC side of the bridge has a three phase controlled voltage source so some external signals
from the controls compiler must be referenced. The control logic shown in Figure 3.6 will
generate a set of three phase signals which are assigned to SRCa, SRCb, SRCc. The source
magnitude is 11.5 kV LL rms.

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Figure 3.6: Control signals which generate the AC voltage signal

Five nodes are included in the circuit; three on the AC side and one at each rail of the DC side. It
should be noted that small time-step nodes differ from large time-step nodes in that their values
are only monitored if explicitly requested. Only the node voltages of interest should be
monitored; for this example the voltages at all the nodes should be monitored.

In order to achieve rectifier operation, no firing pulses are provided to the GTOs/IGBTs connected
in anti-parallel with the diodes. This can be done by changing the source of the firing pulses of
the bridge to CC_WORD, naming the control signal which serves as the control word for the
bridge (FPWORD1 in this case as seen in Figure 3.7) and assigning zero to that control word by
using a wire label and an integer constant. The least significant bit of the control word (bit 0)
controls switch 1, the second least significant bit (bit 1) controls switch 2 and so on. Figure 3.7
shows the menu items of the bridge which must be modified.

Figure 3.7: Change the source of the firing pulse so that it originates from the control compiler

When the case is compiled the warning listed below might appear. This warning is to inform the
user that there might be a problem with their control circuitry because they are trying to control

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the switching of the bridge elements use a gating signal that originates from the large time-step.
This fundamentally undermines the advantages of small time step simulation. For the moment
this warning can be safely ignored because the GTOs/IGBTs are not being switched during the
simulation and there is no need for precise timing of the gating signals. This issue will be revisited
later in the tutorial when a PWM scheme will be implemented.

WARNING: This message is from a small time-step


VSC component of type: ph3lev2
and of component name: BRDG1
located on the first processor
of a VSC bridge named: VB1
in subsystem number: 1.
The firing pulse word input "FPWORD1" for the VSC
component is not locally produced on the processor but
comes from the large time-step backplane.
Consequently, firing pulse word input
changes only once in a large time-step.
The firing could have better resolution if
it was created on the local processor.
Noted in fcn: rnet_ph3lev2_code

Warning issued from <rnet_ph3lev2_code>

Once the case has been successfully compiled, RUNTIME can be launched and the DC and AC side
voltage signals can be plotted. Figure 3.8 shows plots of the results that should be obtained. The
signal VP, as expected, is the maximum value of the signals VA, VB and VC; conversely the signal
VN is the minimum amongst them.

Figure 3.8: RUNTIME plot of the AC and DC side signals from the voltage rectifier circuit

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ALTENATIVE APPROACHES:
There are a number of alternative approaches to building the diode rectifier in this section; some
of these are briefly described below. Each method has its own distinct advantages and
disadvantages.

Discrete Switching Elements:

The small time-step component rtds_vsc_VALVE1 can be used to build the diode bridge. The
vtype parameter can be modified so that several types of switching elements can be represented.
Among them are a GTO, a GTO with an anti-parallel diode, a diode, a thyristor and a thyristor
with an anti-parallel diode. To build the diode rectifier of this section, each switching element
would be a separate component. Using this approach, any arbitrary circuit topology can be
implemented and is particularly useful when circuits having non-standard topology must be
simulated. Figure 3.9A shows the implementation of a diode rectifier using this approach.

Two Level VSC Bridge:

Certain common circuit topologies have been implemented as single components. The
rtds_vsc_PH3LEV2 component, for instance, consists of six GTOs/IGBTs with anti-parallel diodes
and is useful for modeling two-level converters. In this section this component was used to build
a diode rectifier by simply not providing any gating signals to the GTOs/IGBTs. Figure 3.9B shows
the implementation of diode rectifier using this approach. There is essentially no difference in
how this circuit functions when compared to the first implementation using discrete switching
elements. There are two advantages of using this model, however, (1) the circuit is more easily
assembled and (2) foreknowledge of the topology allowed the component to be coded in a more
efficient manner. The benefit of these added efficiencies is that the simulation time-step might
be reduced or the number of components that can be simulated might be increased. Another
useful topology in the library is a single leg of a three-level converter, rtds_vsc_PH1LEV3.

Interfaced Six Pulse Bridge:

A third option in assembling the simple diode rectifier is to use the rtds_vsc_LEV2 component.
Figure 3.9C shows the implementation of diode rectifier using this component. This third
implementation of the diode rectifier is fundamentally different from the two previous
implementations. The bridge in the rtds_vsc_LEV2 component is actually interfaced with the
small time-step network solution using a transmission line having a wave propagation delay of
one small time-step. The presence of this short t-line implies that what occurs at one end of the
transmission line does not affect what occurs at the other end for at least one small time-step.
The valve group is thus effectively decoupled from the small time-step network solution during
any single small time-step. This is the same principle used to divide a large simulation across

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multiple racks. Instead of modeling the VSC switches in a network solution using the methods
introduced in section 2, an open switch is a small conductance and closed switch is a large
conductance. All possible conductance matrices for the circuit are pre-calculated and stored in
memory; they are then referenced as needed. The anomalous power loses previously described
do not occur and higher switching frequencies can be supported. The disadvantage, of course, is
that transmission lines which do not exist in the real system have to been introduced into the
circuit. These transmission lines can lead to reflections and other effects, and thus this
component must be applied with care.

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(A)

(B)

(C)

Figure 3.9: Alternative constructions for the diode rectifier circuit using
(A) discrete valves, (B) valve bridge and (C) interfaced valve bridge

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4 SIMPLE STATCOM EXAMPLE

The small time-step capabilities of the RTDS Simulator are often used to model high frequency
switching circuits such as those used in PWM schemes. In this next section the foundations
established in the previous section are built upon and a simple STATCOM will be assembled. A
STATCOM controls the flow of reactive power into a bus and can thus be used to regulate the
voltage at that bus. Figure 4.1 gives details about the topology of the circuit that will be
constructed; it consists of an infinite bus feeding a load that can be switched in or out of service
by controlling a breaker. The system side is 93kV while the voltage on the converter side of the
transformer is 11.5kV. The base power for the system is 100 MVA. A significant drop in the
voltage at the load bus will occur when the load is connected; the purpose of the STATCOM is to
correct this voltage drop.

Pinj, Qinj

Infinite Bus STATCOM


vs rs xs xtransformer xreactor

VDC

filter VDC
rl
Load
xl

Figure 4.1: Overview of the Simplified STATCOM case being assembled.

The circuit of Figure 4.1 differs from a practical STATCOM in that ideal voltage sources are used
for the DC bus. Normally large capacitors are used on the DC side of the STATCOM, but the use
of ideal sources will significantly ease the construction of a control system since the capacitor
voltage will not need to be actively regulated. In a practical STATCOM the concepts of
instantaneous reactive power are deployed in order to achieve fast, sub-cycle control of the bus
voltage. Here, a simplified approach will be adopted where conventionally defined reactive
power will be regulated.

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STATCOM CIRCUIT:
The small time-step circuit to be constructed is given below in Figure 4.2. The system in 93kV on
the high voltage side and 11.5kV on the low voltage side; the base MVA is 100. All components
must be placed inside a small time-step bridge box. Brief descriptions of each of the important
parts of this circuit are provided below.

Figure 4.2: DRAFT model of Simplified STATCOM

Source:

A controllable source is used to model an infinite bus having a rated voltage of 93 kV LL RMS. The
source impedance is 0.019 + j0.064 pu (Rs = 1.64Ω and Xs = 5.54 Ω at a nominal frequency of
60Hz). The control signals for the source originate from the large time-step and the following
circuit can be used to provide these signals.

Figure 4.3: Signal source for infinite bus

Load

The load is 120 MVA with a power factor of 0.9322 (Rl = 67.25 Ω and Xl = 26.11 Ω at a nominal
frequency of 60Hz). The load can be switched in and out of the circuit using the three phase
circuit breaker component rtds_vsc_BKRN3 which is modeled using the same method as other
switches in the small time-step. When the load is switched in, the voltage at Bus 2 is expected to
dip and it is this dip that the simplified STATCOM should regulate.

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Filter:

The elements found between Buses 3 and 4 together make up a filter; it consist of reactors and
shunt high-pass filter branches. The high-pass filter can be created by using the rtds_vsc_BRC3
component and selecting HIPASS as the Branch Type. In this tutorial a PWM scheme is used where
switching occurs at a frequency of 21 times the fundamental or 1260 Hz. Current and voltage
harmonics will be generated in the vicinity of this switching frequency and the shunt filter branch
will behave as an effective short circuit at these harmonic frequencies and effectively ground Bus
3 to minimize their impact on the network.

The value for the parameters of the filter are Lreactor =0.006686H, Rshunt = 0.6295Ω, Cshunt = 200F
and Lshunt = 0.000079517H. These parameter choices lead to the bode plot of Figure 4.4 for the
impedance of the shunt branch. The input impedance of the shunt branch is ~0.4466Ω at 1260
Hz which is small relative to the impedance offered by the transformer and reactor at that
frequency. At the nominal frequency of 60Hz the input impedance provided by the shunt filter
branch is fairly large and has a value of 13.23 Ω, approximately 10x the base impedance. This
implies that the filter will have a minimal impact on the circuit at the nominal frequency.

Figure 4.4: Bode plot of the magnitude of the shunt branch impedance
The size of the reactor was selected almost arbitrarily and the design rules listed below were
used to select the parameters of the shunt high-pass filter branches. Justification for the design
approach is beyond the scope of this tutorial.

A) Select the capacitor so that at the nominal frequency of 60Hz, the shunt filter branch
behaves like an open circuit. The impedance of the capacitor can be arbitrarily chosen
as 10 pu at 60Hz.

11.52
𝑍𝑏𝑎𝑠𝑒𝐿𝑉 = = 1.322Ω [ Eq. 4.1 ]
100

At the nominal frequency of 60Hz, 𝑙𝑒𝑡 𝑍𝐶𝐴𝑃 = 10 𝑝𝑢 = 1.322Ω × 10 = 13.22𝛺

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1 1
𝐶= = ~200𝜇𝐹 [ Eq. 4.2 ]
𝜔𝑍𝐶𝐴𝑃 376.991×13.22

B) Neglect the parallel resistor and assume a series LC circuit. Using the capacitance
calculated in step (A) select the inductance such that a resonance occurs at the
modulation frequency and the impedance of the capacitor and inductor cancel each
other to provide a path to ground. The resonant frequency of a series LC circuit is 𝜔 =
1
and the resonance should occur at 1260 Hz.
√𝐿𝐶
1 1
𝐿 = 𝜔2 𝐶 = (2𝜋×1260)2 × 200.65𝑒 −6 = 7.9517e−5 𝐻 [ Eq. 4.3 ]

C) Select R such that its impedance is equal to that of the parallel connected inductance at
the modulating frequency.

𝑅 = 𝜔𝐿 = (2𝜋 × 1260) × 7.9517e−5 = 0.62952Ω [ Eq. 4.4 ]

Transformer:

A transformer is typically used to connect the STATCOM and the filters to the bus where voltage
regulation is needed. The impedance is selected as purely reactive and is Xleak = 0.18 pu (15.568
Ω at 60Hz on the primary side). The small time-step transformer rtds_vsc_TRFS1PH should be
used; it is an ideal transformer. The three-phase transformer should be implemented using three
single phase units, each rated at 33.3 MVA. This component will initially be one single phase unit,
but within the configuration menu this can be changed to three single phase units.

Six-Pulse Bridge:

The six pulse bridge shown uses the rtds_ vsc_PH3LEV2 component. The bridge could alternately
be constructed using the rtds_vsc_LEV2 component or several rtds_vsc_VALVE1 components as
was described earlier in this tutorial. The firing pulses for these components will be provided by
the rtds_vsc_3LGFIR component which will need to be supported by a rtds_vsc_TRIWAV3
component and a large time-step control system which will be described shortly.

DC Bus:

The DC bus for the STATCOM will simply be implemented as an ideal source. As discussed above,
this will lead to simplification of the control system. The source impedance will be selected as
purely resistive and as small as possible. The DC bus should be set to 60kV across the positive and
negative poles. (+30kV for the positive pole and -30kV for the negative pole).

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STATCOM CONTROLS:
Two regulators are used in this tutorial; the first will control the voltage magnitude at bus 2, the
second will regulate the real power flow. The theoretical basis for our control is derived from Eq.
4.5 and Eq. 4.6. These two equations describe the physical system that is to be controlled;
specifically they describe the real and reactive power injected into bus 2. The impedance found
between bus 2 and bus 3 is assumed to be purely reactive and δ is the angle of the voltage at Bus
3 relative to that at Bus 2.
𝑉3 𝑉2
𝑃𝑖𝑛𝑗 = 𝑋
sin δ [ Eq. 4.5]

𝑉3 𝑉2 cos δ−𝑉2 2
𝑄𝑖𝑛𝑗 = [ Eq. 4.6]
𝑋

Given that there are no capacitor voltages which need to be actively maintained, the power
flowing out of the STATCOM will simply be regulated to zero. This closely approximates a real
STATCOM where the real power consumption is generally quite small. The voltage at bus 2 will
be regulated to the nominal value of 1.0 per unit.

It is well documented that the power flowing between buses 2 and 3 is strongly correlated to δ.
Similarly, the reactive power flow is a strong function of the voltage magnitudes of the buses.
Given such strong correlations, δ will be used to control P32, and V3 will be used to control Q32.
The mutual effects of δ on Q32 and of V3 on P32 are effectively ignored but good control should
be achievable.

Active Power Regulator:

If δ is limited to +/- 90 degrees then a simple relationship exist between the electric power
transfer, Pinj, and δ. If δ increases then so will P. Such a relationship is ideally suited for control
using the PI controller of Figure 4.5.

Pref + +90
δ
PI
- -90

Pmeas

Figure 4.5: Block diagram of active power regulator

Failure to limit the output of the PI controller is a failure to take into account the non-linear
nature of the underlying process and could cause the controller to fail. Consider the case where
𝑉3 𝑉2
Pref is set to a value above the theoretical limit of the process, . The simple PI controller, in
𝑋

-21-
an attempt to regulate the power flow, would cause δ to increase continually which in turn would
cause Pmeas to oscillate.

Figure 4.6 shows the implementation of the Active Power Regulator for this example. As
mentioned above, Pref will be fixed to zero. The proportional gain is selected as G = 0.01 and the
integrator time constant is set to T = 0.1s. These values are selected experimentally and have not
been optimized in any way. In order to prevent windup problems the integrator is reset when
the controller is operating in the open loop. For this tutorial, the controller will only be open
looped if firing of the bridge’s valves is blocked. The integrators are also reset for the first second
after the simulation is started. This is necessary to make certain that the controllers respond
quickly after the simulation’s start-up electrical transients end. Figure 4.7 shows the integrator
reset logic. The reset logic is not a robust or comprehensive solution but it will work for this
example. The same reset logic is used to reset all the integrators in the STATCOM’s controller.

Figure 4.6: Implementation of active power regulator

Figure 4.7: Implementation of integrator reset logic

Bus Voltage Regulator:

The objective of the voltage regulator is to regulate the voltage at bus 2 to some pre-defined
value. Fortunately the voltage at bus 2 can be fairly easily regulated by controlling the amount of
reactive power injected. If the reactive power injected into bus 2 increases then so will the
voltage at the bus. The PI controller below can be used to control such a system.

-22-
V2ref + Q
PI
-
V2meas

Figure 4.8: Block diagram of bus 2 voltage regulator

The next step involves determining how to go about controlling the reactive power injecting into
bus 2; this will have to be done indirectly. By inspection of Eq. 4.6, a simple relationship between
Qinj and V3 can be found. Assuming that δ has been limited to +/- 90 degrees then as V3 increases,
so will Qinj. Like before, this simple relationship is ideally suited to be controlled by a PI controller.

Qref + V3
PI
-
Qmeas

Figure 4.9: Block diagram of reactive power regulator

The PI regulator above has been designed as though the voltage at bus 3 can be directly
controlled. This is in fact approximately true; the voltage at bus 3 can be controlled by modulation
of the fixed DC bus voltage. With the sinusoidal PWM scheme that will be deployed, it can be
shown that the magnitude of the filtered signal that would ideally appear at bus 3 will be
𝑚𝑎 𝑉𝑆𝑅𝐶 [2]. Here VSRC is the one half of the fixed DC bus voltage and ma is the PWM’s amplitude
modulation ratio. Thus the amplitude of the filtered voltage found at bus 3 can be controlled
directly through manipulation of the amplitude modulation ratio.

Cascading the two PI controllers above allows the control of the voltage at bus 2 indirectly by
changing the amplitude modulation ratio. The complete controller is given below in Figure 4.10.

V2ref + Qref +
PI PI m
- -
V2meas Qmeas

Figure 4.10: Complete block diagram of voltage regulator

Figure 4.11 shows the implementation of the voltage regulator for this example. Like with the
Real Power Regulator, provisions for resetting the integrators during simulation start-up and
when operating in the open loop are included. The first PI controller has a proportional gain of G
= 1000 and an integrator time constant of T = 0.0005s. The second PI controller has a proportional
gain of G = 0.005 and an integrator time constant of T = 40. These parameters were also chosen

-23-
through trial and error. Furthermore, a limiter is added so that the amplitude modulation ratio is
kept in the range of zero and one in order to avoid over-modulation.

Figure 4.11: Implementation of the bus voltage regulator

Signal Filtering:

In order to provide stable results, the measured signals used by the voltage regulator and the
active power regulator are first passed through filters; simple real-pole filters are used. The gains
for all the filters are set to one. The time constants for P and Q filters are set to T = 0.2s. The time
constant for voltage filter is also set to T = 0.2s. Again, these parameters are selected heuristically.
The filters can be seen below in Figure 4.12. The current values, CRT1, CRT2, and CRT3, are the
input currents into winding 1 of the transformer.

Figure 4.12: Regulator input signal measurement and filtering

Sinusoidal Pulse Width Modulation (SPWM):

Two separate regulators have been designed whose outputs define the amplitude and phase of
the voltage that should appear at bus 3 in order to achieve the dual design objectives of
regulating the bus 2 voltage and regulating the active power drawn by the STATCOM. The next
step is to generate this desired voltage. Sinusoidal PWM (SPWM) is used to achieve this objective.

-24-
Consider the circuit of Figure 4.13A which shows one leg of the bridge that has been created in
this tutorial example. In a standard SPWM scheme a sinusoidal modulation signal is compared
with a high frequency triangle wave as demonstrated in Figure 4.13B. When the value of the
triangle wave exceeds that of the modulation signal then switch S1 will be turned off. Conversely,
when the amplitude of the triangle wave is less than that of the modulation waveform then
switch S1 will be turned on. The switch S2 will be controlled in a complimentary fashion.

VDC
S1 -A
(B)
+
Vout S2 VDC
VDC
-

(A)

-VDC (C)

Figure 4.13: Sinusoidal pulse width modulation basics

The signal Vout from the circuit will be a switched waveform similar to that shown in Figure 4.13C.
It can be shown that if the amplitudes of the triangle wave and sinusoidal modulation signal are
the same, then the amplitude of the fundamental component of Vout will be equal to the DC rail
voltage, VDC. Similar principles of operation apply to all three legs of the bridge.

Modulation Waveforms

The outputs of the active power and bus voltage regulators designed above are δ and m
respectively. Both of the signals are used in the generation of the modulation waveforms of
the PWM scheme that will be deployed. The control circuit used to generate the modulation
signals is shown in Figure 4.14; the frequency is fixed at 60Hz.

-25-
Figure 4.14: Control circuit to generate modulation waveforms for sinusoidal PWM

Triangle Waveform

In order to implement SPWM, a high frequency triangle wave needs to be compared to the
modulation signals. The small time-step Triangle Wave Generator Component
(rtds_vsc_TRIWAV3) will be used to generate this triangle wave. The triangle wave is generated
within the small time-step simulation because a high resolution signal is needed in order for the
switching instants to be calculated with precision.

In practice, the frequency of the triangle wave is commonly an integer multiple of the
fundamental frequency. Since the fundamental frequency can drift in a real system, the small
time-step triangle wave generator was designed to accept inputs from a large time-step controls
circuit which can track such drift. The circuit of Figure 4.15 is one such circuit that can be quite
useful for SPWM applications. A three phase signal can be input into a PLL whose output is the
phase and frequency of that three phase signal. Multiplying the output frequency by the SPWM’s
frequency modulation factor, mf, yields a frequency signal for a triangle wave. Multiplying the
phase signal by mf and fixing it so that is lies between 0 and 2π yields the associated phase signal
for the triangle wave.

Figure 4.15: Generation of support signals for small time-step triangle wave generator

-26-
Figure 4.16 further illustrates the generation of the triangle wave’s phase signal assuming mf = 4.
The output of the PLL is multiplied by mf = 4 and the result is then fixed so that it lies between
the range of 0 and 2π. Notice that result is a phase signal appropriate for a triangle wave having
frequency mf times that of the original signal.


ANGLE


TANGLE
t

Figure 4.16: Generation of the triangle wave’s phase signal


Figure XX: Generation of the triangle wave’s phase signal

It was stated earlier that a high resolution triangle wave is needed in order to precisely determine
switching instants. The small time-step component rtds_vsc_TRIWAV3 uses the phase and
frequency information generated by the large time-step control circuit of Figure 4.15 to generate
that high resolution triangle wave in the small time-step. This is done primarily through
extrapolation as well as some boundary wrapping. Every small time-step the incremental phase,
θ’, can generally be calculated according to the equation θ’ = θ0 + ωt and based on the calculated
value, the proper point on a triangle wave can be fairly easily found using a lookup table and/or
by simple range checking. Figure 4.17 illustrates this concept.

θ' 2π

-A

Figure 4.17: Extrapolated θ' used to get a value for the triangle wave

-27-
Some of the default parameters in the rtds_vsc_TRIWAV3 component will need to be changed.
The signal label names assigned to the triangle wave phase and frequency outputs must be
specified inside the rtds_vsc_TRIWAV3 component. Only a single triangle wave is needed in this
example and its peak-to-peak magnitude will be set to 2.0 with an offset of 0.0; this will produce
a triangle wave that oscillates between 1.0. A name must be assigned to the triangle wave signal
that will be output from the component so that it can be referenced by the small time-step
comparator that will be described next. Finally, the triangle wave should explicitly be targeted
for monitoring during RUNTIME so that the performance of the PWM scheme can be evaluated.
The user is encouraged to consult documentation regarding the additional capabilities of the
triangle wave generator.

PWM Comparator

At this stage both a triangle wave and the desired modulation signals have been generated. What
remains to be done is a comparison of these signals in order to generate the required firing
pulses. This comparison must be done in the small time-step simulation in order to accurately
determine the switching instances. The rtds_vsc_3LGFIR component is used in order to do the
comparison. A single component is capable of doing the three comparisons needed for the three
phase system.

Several inputs must be provided to this component. These include the names of the triangle wave
and modulation signals as well as a de-block signal. The rtds_vsc_3LGFIR component gives the
user complete freedom to specify how the firing pulse word used to control valve firing is
generated. Each of the component’s three comparators makes one of two possible contributions
to the final firing pulse word; one for when its modulation signal is greater than or equal to the
triangle wave and another for when its modulation signal is less than the triangle wave. The
outputs from each of the comparators are then bitwise ORed together. The result is then ANDed
with a de-block signal. The equation for the output of the firing pulse generator is given in Eq.
4.7. In this equation cmp1t, cmp2b, cmp1t, cmp2b, cmp3t, cmp3b and dblknm are all parameters
of the rtds_vsc_3LGFIR component.

fpout = [(cmp1t || cmp1b) || (cmp2t || cmp2b) || (cmp3t || cmp3b)] && dblknm [ Eq. 4.7 ]

For this tutorial the end objective is to control the valve bridge of the rtds_vsc_PH3LEV2
component. This valve bridge component is designed in such a fashion that each valve is
controlled by a different bit of a firing word which is referenced as a parameter. Valve 1 is
controlled by bit 1, valve 2 by bit 2, valve 3 by bit 3 and so forth. If the bit associated with any of
the valves is one then the valve is conducting, if it is zero then the valve is blocking.

-28-
Assume that the bridge receives its firing pulse input word from the rtds_vsc_3LGFIR component
and that the contributions from each of its three comparators are left with their default values
which are listed in Table 1. Each comparator can make one of two possible contributions to the
firing pulse word depending on how the triangle wave and its modulation signal compare. Notice
that with the default contributions valves 1 and 2, valves 3 and 4 and valves 5 and 6 will always
be fired in a complementary fashion as needed. The contributions are also such that comparator
1 affects only bits 1 and 2, comparator 2 affects only bits 3 and 4 and comparator 3 affects only
bits 5 and 6. The implication of this is that the contributions from all three comparators can be
ORed together to form a single firing pulse input word without affecting each other. This firing
pulse input word is then ANDed with a de-block signal before being passed to the valve bridge.

Comparator Condition Contribution Contribution


(Decimal) (Binary)

1 Modulation Wave #1 >= Triangle Wave 1 00 00 01


Modulation Wave #1 < Triangle Wave 2 00 00 10
2 Modulation Wave #2 >= Triangle Wave 4 00 01 00
Modulation Wave #2 < Triangle Wave 8 00 10 00
3 Modulation Wave #3 >= Triangle Wave 16 01 00 00
Modulation Wave #3 < Triangle Wave 32 10 00 00

Table 1: Comparator contributions to firing pulse word

Although the component is flexible enough to block only selected valves, for this example all
valves are either blocked or de-blocked. Adding a simple switch that outputs an integer value of
63 when de-blocked (ON state) and 0 when blocked (OFF state) will achieve the desired objective.

RUNTIME INTERFACE
Create a RUNTIME interface similar to that shown in Figure 4.18. If the STATCOM is blocked then
the voltage at bus 2 should drop significantly when the load is connected. If the STATCOM is de-
blocked the voltage at bus 2 should be regulated to around 1pu regardless of whether the load
is connected or not.

-29-
Figure 4.18: RUNTIME interface for simple STATCOM example

-30-
Additional Exercise: Monitoring Small Time-Step Signals in High
Definition
When viewing a small time-step signal in RUNTIME the signal is only plotted each large time-step
by default and can thus appear distorted. In some cases the full signal resolution may be desired
in RUNTIME.

In the previous case, TWAVEA was plotted over top MOD1WAV1. Zooming in on TWAVEA shows
that the peaks of the signal appear distorted, as in Figure 4.19. However, TWAVEA is a very
accurate triangle wave and simply has higher resolution than the plot displays.

Figure 4.19: Small time-step TWAVEA signal plotted against large-time step time signal.

SCOPE:

We cannot continuously plot small time-step signals in RUNTIME because of the large number of
data points required. We therefore use a SCOPE component (rtds_vsc_SCOPE1) to allow portions
of a small time-step signal to be plotted in RUNTIME.

In DRAFT, place this component into the small time-step bridge box and edit the parameters as
follows. Enable monitoring of channel 1 and scope time signal output (mon1 and mon7). Set the
number of words to capture per channel to 11000 (limit of 20000 for each channel). Change the
input signal name for channel 1 to TWAVEA and output name to TWAVEhd.

Scope data capture is not done continuously, it is a triggered update using the trigger control
integer input name. If a rising edge of the trigger control signal is detected, new data is collected.
When you perform a steady state plot update, the same previously captured words are displayed.
The only time new data is collected is when a rising edge of the trigger signal is detected.

-31-
If you want new small time-step data collected based on a trigger pattern, you could do this as
well using a pattern-trigger control signal. The pattern trigger is armed using a bit of the trigger
control input word (trignm). Upon arming the pattern trigger, the update is triggered based on
the pattern trigger input word (pattnm).

In this case the default trigger parameters can be used. To control triggering of the update, add
the control components shown in Figure 4.20.

Figure 4.20: SCOPE component and triggering controls.

RUNTIME INTERFACE
To highlight the advantages of the SCOPE, add the plots seen in Figure 4.21 to your RUNTIME
interface. TWAVEhd vs TIMESIG is an X-Y plot with the small time-step time signal on the X-axis
and the small time-step scope signal on the Y-axis. In this example, when the UpdatePlots
pushbutton is pressed in RUNTIME new small time-step data is collected. This example disables
the pattern trigger control by setting the pattern trigger signal to 0.

Observe the functionality of the SCOPE by first comparing the distortion of TWAVEA to the
TWAVEhd signal. Also note that plotting TWAVEhd against time does not yield the true
representation of the signal. The X-Y plot is therefore required and will correctly match with time.
On this plot you should be able to see that a data point is plotted every small time-step.

If you continue to trigger the scope to collect data, the X-Y plot may look strange. This is because
the update is not synchronized to the last 11000 words. The data could now be starting at any
location on the waveform. When looking at the X-Y plot you must also keep in mind at which

-32-
point you have selected to update data. If it happens to be at a point where the small time-step
time signal is being reset to 0, the results will look strange.

Figure 4.21: RUNTIME interface for observing SCOPE functionality.

-33-
Additional Exercise: Change in the DC Bus
In the previous case, the DC bus for the STATCOM was implemented as an ideal source. An
additional exercise would be to replace the source with a large capacitor, as this more closely
resembles a practical STATCOM. Figure 4.19 shows the change that needs to be made to the
power system. The change can be made by keeping the same component (rtds_vsc_BRC3) for
the DC bus, changing the branch type to RC and excluding the branch’s optional voltage source
in the branch. Choose the capacitor value to be 2000F and make the series resistance 0.0001Ω.

Figure 4.22: Bus with capacitors instead of sources

The function of the STATCOM will remain the same, but the addition of the capacitor adds
another layer of complexity to the system. No longer can the power regulator be referenced to
zero as real power needs to be exchanged between the STATCOM and the power system in order
to maintain the charge on the capacitors. The Active Power Regulator developed above will need
to be augmented to achieve this objective.

DC Bus Regulator (formerly Active Power Regulator):

The voltage of a capacitor is governed by Eq. 4.8. The voltage seen at the DC bus is determined
by the amount of current that can be directed to the bus. This provides a simple relationship
between DC Capacitor voltage, VDC, and Pinj. To increase VDC, inject more active power, and hence
current, to the STATCOM. Therefore the DC bus can be regulated by controlling the real power
exchange. The PI controller seen in Figure 4.20 will perform the required control.
1
𝑉𝑐 = 𝐶 ∫ 𝐼𝑐 𝑑𝑡 [ Eq. 4.8]

-34-
VDCref + P
PI
-
VDC

Figure 4.20: Block diagram of DC bus regulator

By cascading the two PI controllers of Figure 4.5 and 4.20, the DC bus voltage can be regulated indirectly
by changing the load angle,δ. Figure 4.21 shows the complete block diagram. The reason why the polarity
is reversed for Pref and Pmeas, is because injecting P or Q into the power system from the STATCOM is
considered the ‘positive’ direction while increasing the DC bus voltages, requires power flowing in the
‘negative’ direction.

VDCref
+ Pref - +90
δ
PI PI
- + -90

VDC Pmeas

Figure 4.21: Complete block diagram of DC Bus Regulator

Figure 4.22 shows the implementation of the DC Bus Regulator. An integrator time constant of
0.25s and a proportional gain of 5 for the first PI controller seemed to provide reasonable results.
The parameters for the second PI controller are unchanged from earlier in the tutorial.

Figure 4.22: Complete block diagram of DC Bus Regulator

Voltage Regulator:

The voltage regulator will be the same as in the previous cases where the DC bus contained
sources.

RUNTIME INTERFACE
Create the same runtime file from the previous case as seen in Figure 4.18. Once again, the
voltage at bus 2 should be around 1pu when the STATCOM is de-blocked. However, with the
addition of the capacitor, the active and reactive power flowing through network and the
STATCOM will deviate from zero since real power will be drawn to maintain the capacitor voltage.

-35-
5 INTERFACING LARGE AND SMALL TIME-STEP SIMULATIONS

Up until this point, all the simulations in this tutorial have consisted entirely of small time-step
components. When possible this is a good option, but it is not always practical. The large time-
step library is much more extensive than the small time-step library and sometimes the need for
these models drives the need to interface the small and large time-step simulations. Also, small
time-step simulation is relatively computationally intense when compared to the large time-step
simulation so it does not always make sense to model everything with the level of detail provided
by the small time-step simulation.

In order to interface the large and small time-step simulations a component called an interface
transformer must be used. One side of the interface transformer will have only large time-step
components connected to it; the other side will only be connected to small time-step
components.

There are several interface transformers available but the most recent and most stable model is
the rtds_vsc_IFCTRF1 component. Currently this interface transformer is only available in single
phase form; a three phase transformer can be created using three of these single phase
transformers. Two older interface transformers include the rtds_vsc_TF3 and the rtds_vsc_STFR4
components. Use of these models, however, is not recommended since the newer model is more
stable.

Whenever possible the circuit should be divided at a point where an actual transformer exists.
This is due to the fact that the interface transformer has a leakage reactance and a resistance. To
minimize the impact of inserting the interface transformer into the circuit it is best to insert it a
point where a leakage reactance and a resistance already exist. The presence of the leakage
reactance and resistance is a consequence of how the transformer is modeled. Details on the
implementation of the rtds_vsc_IFCTRF1 component are given at the end of this section.

As an exercise, the simple STATCOM from section 4 can be modified. The transformer will be
replaced by an interface transformer and the source and load will be modeled using large time-
step components since there is no need to model these devices with a small time-step. Figure 5.1
illustrates how the original circuit is to be divided.

-36-
Move to Large ∆t Replace w/ Interface TR Leave in Small ∆t

Figure 5.1: Simulating a simple STATCOM using two different time-steps.

The first step would be to remove the source, load and breaker from the small time-step
simulation and replace them with equivalent large time step components. The transformers in
the small time-step bridge box will need to be replaced with interface transformers with
equivalent ratings, leakage reactance and resistance.

The next step is to connect the large time step components to the interface transformer.
Fortunately the VSC bridge box behaves similar to a conventional hierarchy box. If a large time-
step power system node is connected to the VSC bridge box using a wire then that node can be
duplicated inside the VSC bridge-box and the compiler will recognize that the nodes are in fact
the same node and that they are electrically connected. With the node duplicated inside the VSC
bridge box, it can then easily be connected to the primary side of the interface transformer.
Figure 5.2 illustrates what the circuit should look like with the source and load modeled in the
large time-step. Some signals will need to be monitored and some very minor changes will need
to be made to the control system to get things working like in section 4.

-37-
BUS 2 93 kV

BUS1
1.0 /_ 1.0
N3 N2 N1

BUS 1
AC Type VB1

A
RRL

B
RRL
Infinite Bus
C
src RRL

Ell= 93 kV

BRK1B

BRK1A
BRK1C
Breaker
BRK1
7
0

R L

R L

R L
Switchable
Load

Figure 5.2: Simple STATCOM case divided between large and small time-step simulation facilities

Interface Transformer
The rtds_vsc_IFCTRF1 interface transformer model is implemented as a travelling wave
transmission line. This approach to modeling the transformer was chosen because of the stability
that it provides. The transmission line is kept quite short; its traveling time is fixed at 1.39 large
time-steps. The inductance, L, of the transmission line is chosen so that it is equal to the leakage
of the interface transformer. The capacitance, C, of the transmission line is then calculated using
the travel time and the inductance of the line. For the purpose of this calculation the line is
assumed to be lossless. The actual model can accommodate the presence of losses.

Assuming a lossless line, the travel time of wave propagating on a transmission line is given by
Eq. 5.1.

-38-
𝑡𝑟𝑎𝑣𝑒𝑙 𝑡𝑖𝑚𝑒 = √𝐿 ∙ 𝐶 [ Eq. 5.1 ]

where L is the line inductance in H


C is the line capacitance in F

With the travel time set to 1.39 times the large time-step, Eq. 5.1 can be used to determine the
line capacitance. The result is given in Eq. 5.2.
2
(1.39∙∆𝑇𝑙𝑎𝑟𝑔𝑒 )
𝐶= [ Eq. 5.2 ]
𝐿

This capacitance is a direct consequence of modeling the transformer as a transmission line and
would not normally exist in the circuit. Care should be taken to make certain that this capacitance
is not too large. If it is, then it will start to impact the simulation, something which should be
avoided. In general, the value of XC should be significantly larger than the surrounding
impedances.

By inspection of Eq. 5.2, it is evident that if the leakage of the interface transformer is chosen
very small then the capacitance, C, will be large. In order the avoid this situation the interface
transformer leakage must be greater than 0.05 pu.

The capacitance and inductance described above represent distributed parameters. In order to
be able to assess whether the capacitance of the line has become too large, it is helpful to find
the effective capacitance seen at terminals of the interface transformer. In order to do this the
π-circuit equivalent for the transmission line/interface transformer must be found. Figure 5.3
shows this equivalent; an ideal transformer has been added to the transmission line π-circuit
equivalent to model the voltage transformation capabilities of the interface transformer.
𝑍𝑒 ′
1∶ 𝑁

Large Time- Small Time-


𝑌𝑒 𝑌𝑒 ′
Step Step
2 2
Simulation Simulation

Figure 5.3: π -circuit equivalent for the interface transformer with ideal transformer

The effective capacitive reactance of the interface transformer seen from the large time-step side
of the interface transformer is labelled as XC and can be calculated using Eq. 5.3[3]. In this

-39-
equation ZC is the characteristic impedance of the line, γ is the propagation constant of the line
and l is the length of the line.

𝑌 −1 1 𝛾𝑙 −1
𝑋𝐶 = ( 2𝑒 ) = (𝑍 tanh ( 2 )) [ Eq.5.3 ]
𝐶

With the assumption of a lossless line Eq. 5.3 can be simplified to Eq. 5.4.

𝑌 −1 1 𝑗𝜔∙1.8∙∆𝑡𝑙𝑎𝑟𝑔𝑒 −1
𝑋𝐶 = ( 2𝑒 ) = (𝑍 tanh ( )) [ Eq.
𝐶 2
5.4 ]

𝐿
where 𝑍𝐶 = √
𝐶

When a case containing an interface transformer is compiled the effective capacitive reactance
is calculated for the rated frequency of the interface transformer and is listed in the MAP file. For
convenience, the effective capacitance of the line is also referred to the small time-step side of
the ideal transformer and listed in the MAP file. An excerpt of the listing is provided below:
VSC component model of type "ifctrf1"
named: T1
within the BRIDGE named: VB1
in subsystem: #1
is assigned to GPC Card #2 Processor A

At a tap factor of 1.0, there is an effective


capacitive reactance connected between the
primary terminals of 2.704987e+004 Ohms.

Regardless of the tap factor, there is an effective


capacitive reactance connected between the
secondary terminals of 3.784344e+002 Ohms.

The MAP file can be viewed by pressing the view button in DRAFT’s toolbar and selecting MAP
File in the dialog that appears. Figure 5.4 shows the button that should be pressed.

-40-
Figure 5.4: Opening a MAP File

-41-
6 CONNECTING VSC BRIDGE BOXES USING SMALL TIME-STEP
TRANSMISSION LINES

Currently, each VSC bridge box can contain a maximum of 30 nodes and about 32 switching
devices. It is recognized that there is sometimes a need to model larger switching networks. In
response to this need, the VSC Cross−Card Bergeron Transmission Line model has been
developed. The transmission line model can be used either to model a transmission line in a single
VSC Bridge Box or they can be used to connect two VSC Bridge Boxes together. It is this latter
ability to link bridge boxes that will be the focus of this section.

The process of linking small time-step bridge boxes is analogous to connecting different racks for
the large time-step simulation. The network solutions for each bridge box are effectively
decoupled if the travelling time of the transmission line connected between them is greater than
a small time-step. This decoupling allows the network solutions to be solved independently and
results in significant computational savings. Given that a small time-step is typically 1.5~2.5s
and assuming a wave propagation velocity of 3x108 m/s the minimum length of the small time-
step transmission line ends up being on the order to 430 to 740m long, significantly shorter than
the large time-step transmission lines which are typically on the order of 15km long.

Hardware Connections:
Large time-step transmission lines are used to communicate from one rack to another. Signal
communication is managed by the GTWIF and in order to communicate from one rack to another
there has to be a fibre optic cable linking the GTWIF cards of the respective racks.

Analogously, small time-step transmission lines are used to communicate from one small time-
step bridge box to another. In order to communicate between the two bridge boxes there must
be a fibre optic link between them. Unlike with large time-step t-lines where racks are linked
through the GTWIF cards, small time-step t-lines are linked through the GPC’s card GTCOM ports.

Each GPC card has four fibre optic ports, two are GTCOM ports and two are GTIO ports which are
used to connect IO cards. The topmost port is GTCOM port 3 while the second from the top is
GTCOM port 4. Please refer to Figure 6.1 below for a diagram on how to locate these ports.

-42-
Figure 6.1: Location of GTCOM ports on GPC processor card

As already stated, in order to connect a transmission line between one bridge box and another,
there must be a physical fibre optic cable connecting the cards on which the bridges are running.
The signals for up to 8 transmission lines can communicate over the same fibre cable and both
processors on a GPC card can simultaneously access the same GTCOM port. Figure 6.2 below
shows three different examples of how small time-step bridge boxes can be linked. The
processors on which the bridge boxes are running have been selected arbitrarily. A line
connecting any two bridge boxes in the diagram indicates that one or more t-lines span them;
lines of the same color represent the same physical fibre optic cable. The GTCOM ports to which
each end of a fibre is connected are also indicated in the diagram.

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Figure 6.2: Sample bridge box interconnections

Small Time-Step Transmission Lines:


Similar to large time-step transmission lines, three things are needed to make a small time-step
transmission line (1) a sending end terminal, (2) a receiving end terminal and (3) a calculation
block. Figure 6.3 below shows the DRAFT icons for these components. They are linked by the
compiler if they share the same ‘T-LINE NAME’.

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(A) (B)

(C)

Figure 6.3: (A) Sending End, (B) Receiving End and


(C) Calculation Block for a Small Time-Step T-line

In order to link two bridge boxes, one end of the small time-step transmission line would be
placed in one of the bridge boxes and the other end would be placed in the second bridge box;
the calculation block can be placed in either. Figure 6.4 illustrates how a simple circuit might be
divided between two bridge boxes. Generally the process of creating the data for a small time-
step t-line is identical to that needed for a large time-step transmission line. Please review
Tutorial Chapter 2: Simple AC System for details on this process.

Figure 6.4: Using a transmission line to connect two VSC bridge boxes

One important difference from large time-step transmission lines is that the GTCOM port used
must explicitly be specified inside each terminal of the transmission line. Figure 6.5 shows the
parameter which must be changed in each of the transmission line terminals.

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Figure 6.5: Specification of the GTCOM port inside a transmission line's terminals

When a case which includes small time-step transmission lines is compiled successfully then a
.txt file is generated that is named DRAFTFILENAME_comm_fiber_patching.txt. This file is located
in the project directory and lists where all the necessary fibre connections should be made. This
file is especially useful if you have many connections. The content of such a file is listed below:

Optical fibers must be connected between


communication ports on the backs of
processor cards as follows:

END No. 1 END No. 2


rack card port <----> rack card port

7 1AB 3 7 1AB 4

Because of the transmission line’s dependence on a physical fibre connection it becomes useful
to be able to fix the processor on which the small time-step bridge will run. If this is not done
then the processor to which a given VSC bridge box is assigned can change from one DRAFT
compilation to the next. This would require that frequent changes to the GTCOM fibre
connections be made. Not only would this be tedious, it is also error-prone. The processor to
which a specific VSC Bridge is assigned can be manually set by the right-clicking on a given bridge
box and selecting Edit -> Parameters. Figure 6.6 show the parameters that need to be modified
in order to manually assign a bridge box to a specific physical processor.

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Figure 6.6: Parameters associated with manual processor allocation of VSC bridge boxes

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7 SMALL TIME-STEP IO

Importing and exporting signals into and out of the small time-step simulation is fairly straight
forward. This section provides a brief rundown of how to do this for both digital and analog
signals.

Analog Outputs
All small time-step analog signals are output from the RTDS simulator on an individual basis. The
user must specifically indicate which signals they want output and where they would like those
signals output. This is typically done directly within individual small time-step components. The
signals available to be output will vary from one component to another. In general a signal can
either be output to one of the processing card’s faceplate outputs or to a GTAO card connected
to the processor. The process of sending a signal to both of these targets is described below.

Faceplate AO:

Generally small time-step components will have a tab named either ‘ENABLE FACEPLATE D/A
OUTPUT’ or other similar name. This tab allows the user to select the signals intended for output
through the faceplate analog outputs. As mentioned, the signals available to be output will vary
from one component to another. After a signal has been selected for output through the
faceplate then another tab will be become available. The name of the tab will vary but it will be
something along the lines of ‘FACEPLATE D/A CHANNEL ASSIGNMENT’ and it will allow the signal
to be assigned to a specific channel. The channel can be any value between 1 and 12. The signal
will be written to the channel of the processor on which the model is running (either processor
A or B). A scaling constant can be used to modify the signal of interest so that it lies within the
faceplate analog outputs dynamic range of +/- 10V. A unique offset can also be added to each of
the faceplate outputs. Figure 7.2 highlights the parameters that would have to be changed if a
branch current were to be monitored though the faceplate.

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Figure 7.1: Menu items related to front panel analog outputs

GTAO:

The process of sending a signal to the GTAO is similar to that needed to output a signal through
the faceplate but a few additional steps are needed. Every small time-step component must be
assigned to a processor and each processor can access up to two GTAO cards. Each GTAO is
referred to as either ‘GTAO1’ or ‘GTAO2’. The first step is to enable components within the small
time-step bridge box to access the GTAO cards. This is done inside the properties of the VSC
bridge box as shown in Figure 7.2.

Figure 7.2: Enable access to GTAO card inside the VSC bridge box

If analog output through at least one of the GTAOs has been enabled then the menu of Figure
7.3 will appear and details about the physical connections of the GTAO can be entered.
Specifically, the GTAO card number and the GTIO fiber port number to which it is connected must
be entered. It should be noted that only the first two GTAO cards in any chain can be accessed.

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Figure 7.3: Specify GTAO card number and GTIO Fiber port to which it connects

NOTE: Once access to the GTAO cards has been enabled within the small time-step bridge box
then signals can be freely assigned to the GTAO channels within individual components. Failure
to complete the above steps will trigger errors when the case is compiled.

Generally small time-step components will have a tab called ‘ENABLE GTAO D/A OUTPUT’ or
something similar. This tab allows the user to select the signals intended for output through a
GTAO analog output card. Like with the faceplate analog outputs, the signals which are available
to be output will vary from one component to another. When at least one signal is chosen for
output through the GTAO, another tab will appear (if not already visible); in it the user must
specify the GTAO card to which the each signal is to be sent. This is done by referring to the
‘GTAO1’ or ‘GTAO2’ aliases that are assigned to physical GTAO cards in the small time-step bridge
box. The specific GTAO channel must also be specified; any value between 1 and 12 is valid but if
multiple signals are assigned to the same channel of the same GTAO card then an error will result
upon compiling the case. A scaling constant must be specified for each channel. The scaling
constant is usually chosen so that a scaled signal falls within the +/- 10V dynamic range GTAO
card. Like the faceplate analog outputs, an offset can be added to the scaled output and the
output can be inverted if desired. Figure 7.4 highlights the parameters that would have to be
changed if a branch current were to be monitored through a GTAO.

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Figure 7.4: Menu items related to GTAO analog outputs

It is desirable to have the ability to control the processor to which a small time-step bridge box is
allocated. This is especially true when external equipment needs to be interfaced through the
small time-step component. In general the compiler can automatically allocate the bridge box to
an available processor but the allocation can potentially change as a case is developed. This opens
up the possibility that a small change in a case could cause the small time-step bridge box to get
bumped to another processor and thus would require all the external connections to be
physically moved. This potential problem can be avoided by manually assigning components to a
processor; the small time-step bridge box will thus always get allocated to the specified processor
each time the case is compiled. Figure 7.5 shows the parameters in the bridge box which allow
the user to manually assign it to a specific processor.

Figure 7.5: Manual processor assignment of small time-step bridge box

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Digital Input
GTDI:

Digital input signals are used extensively in small time-step simulation for things like providing
firing pulses to power electronic switches. The GTDI IO card is required in order to bring digital
signals into the small time-step simulation. A small time-step bridge box can access up to two
different GTDI cards but they must be the first two GTDI cards in the chain.

As with the GTAO, the first step to using the GTDI is to enable components within the small time-
step bridge box to access them. This is done inside the properties of the VSC bridge box as is
shown in Figure 7.6.

Figure 7.6: Enable access to GTDI card inside the VSC bridge box

After the digital input from the GTDI card has been enabled then the menu of Figure 7.7 will
appear where details about the physical connections of the GTDI can be entered; the GTDI card
number and the GTIO Fiber Port number to which it is connected must be specified. Also, two
signal names to which the inputs read from the GTDI card can be assigned should be specified.
The GTDI has 64 channels; channels 1-32 get assigned to GTDI word 1 and the channels 33-64 get
assigned to GTDI word 2. These words can then be referenced by various small time-step
components.

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Figure 7.7: Specify GTDI card number, the GTIO Fiber port, and the signal names
for the read signals

Once access to the GTDI cards has been enabled within the small time-step bridge box and their
inputs have been assigned to signals, then these signals can be freely referenced by individual
components. Most components that can accept digital inputs will have a tab called ‘FIRING PULSE
INPUT’. If the option exists then the source of the firing pulse input word should be specified as
‘CC_WORD’. One of the signal names assigned inside the small time-step bridge box can then be
referenced inside the component. Figure 7.8 illustrates how this can be done for the three-phase,
two-level bridge component (rtds_vsc_PH3LEV2); one of the GTDI’s input is presumed to have
been assigned to the control word ‘GTDI1W1’ inside the small time-step bridge box.

Figure 7.8: Referencing inputs from a GTDI inside a small time-step component

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Analog Input
GTAI:

In order to bring analog signals into the small time-step simulation the rtds_VSC_GTAI
component can be used. The icon for the component is shown in Figure 7.9.

Figure 7.9: Icon for small time-step GTAI component

This component works in much the same way that the large time step GTAI component works.
Details about the physical connections of the GTAI must be specified; this includes the GTAI card
number and the GTIO fiber port number to which it connects. Each of the GTAI’s channels can be
enabled individually. A separate scaling constant and offset can be specified for each channel.
The read GTAI signals can also be made available in the large time-step or through the front panel
analog outputs if desired.

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Digital Output
GTDO:

In order to output digital signals from the small time-step simulation the rtds_VSC_GTDO
component can be used. The icon for the component is shown in Figure 7.10.

Figure 7.10: Icon for small time-step GTDO component

This component works in much the same way that the large time step GTDO component works.
Details about the physical connections of the GTDO must be specified; this includes the GTDO
card number and the GTIO fiber port number to which it connects. The 64 channels of the GTDO
card are divided into four 16 channel banks. Each bank is controlled by a different control signal
and can be enabled or disabled independently. The 16 least significant bits of the first control
signal are assigned to output channels 1-16; the 16 least significant bits of the second control
signal are assigned to output channels 17-32, etc.

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8 SELECTING VALVE PARAMETERS

As discussed in section 2 of this tutorial, several shortcuts are used mimic the behaviour of a
switch; an open circuit is modeled as an RC branch and a short circuit is modeled as an L branch.
This approach is selected primarily because it allows the freedom to select R, L and C in such a
fashion that the conductance value for when the switch is opened, goc, and when it is closed, gsc,
are the same. The change in switching state can then be completely represented by changes in
current injections. This significantly simplifies the required calculations because the matrix
inversion of Eq. 2.5 is not required by the network solution.

The validity of the modeling approach used for small time-step simulation is based upon the
accuracy with which a large resistance can be represented by an RC circuit and the accuracy with
which a small resistance can be represented by an inductance. The parameters R, L and C must
be selected with care in order to make certain that the chosen approximations are accurate. In
this section, the different constraints which are placed on the selection of these parameters is
discussed.

1. The main objective of modeling an open circuit as an RC circuit, and a short circuit as an
inductor is to avoid the need for a matrix inversion whenever a switch changes states. In
order to achieve this objective, the conductance values for both states must be the same.
This leads directly to Eq. 8.1, the first constraint imposed on the selection or R, L and C.
2𝐿 ∆𝑡
= 𝑅 + 2𝐶 [ Eq. 8.1 ]
∆𝑡

2. With the chosen modeling approach there is the potential for undesired interactions
between the switches. Consider two series connected switches, one in the ON state and
the other in the OFF state. Using the conventional modeling approach this would be a
large resistance in series with small resistance but using the proposed approach it is
actually represented by a series RLC circuit. It is possible that the response of such a circuit
could be poorly damped when subjected to a disturbance. If possible it is desirable to
select R, L and C parameters for the switches such that the response of the circuit to a
disturbance is well damped. The challenge is that switches can be connected in any
arbitrary topology and that the equations relating damping to the parameter choices will
change accordingly. A heuristic approach must therefore be adopted; the values of R, L
and C are selected so that good damping is achieved for series connected switches, one
ON and the other OFF. This topology is illustrated in Figure 8.1 and is one that is commonly
found in VSC converters.

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i(t) i(t)
L

v(t) v(t)
R

Figure 8.1: Series connected switches, one ON and the other OFF

𝐼(𝑠)
Writing the transfer function relating for results in a second order function for which
𝑉(𝑠)
it is easy to define the damping factor, δ, and natural frequency, wn. The transfer function,
δ and ωn are given in equations 8.2 through 8.4.

𝐼 (𝑠 ) 𝑠
𝑉 (𝑠 )
= 𝑅 1 [ Eq. 8.2 ]
𝐿(𝑠 2 +𝑠 + )
𝐿 𝐿𝐶

𝑅
where 2𝛿𝜔𝑛 = [ Eq.
𝐿
8.3 ]

1
𝜔𝑛 = [ Eq. 8.4 ]
√𝐿𝐶

The desired damping of the circuit is something that will be specified as a valve parameter;
the natural frequency is not so much a concern. Substituting out ωn from Eq. 8.3 and Eq.
8.4 leads to Eq. 8.5, the second constraint imposed on the selection or R, L and C.

1 𝑅
2𝛿 = [ Eq. 8.5 ]
√𝐿𝐶 𝐿

3. As a result of the modeling method there are artificial losses which occur every time a
switch changes states. For slowly switched circuits these loses are not a concern but as
the switching frequency increases these losses start to accumulate. The aim of the final
constraint applied to the selection of R, L and C is to minimize these losses.

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Consider the diagram of Figure 8.3 which shows a comparison of the current established
in an ideal switch at turn-on versus the current established in an inductor, the chosen
representation for a switch in the ON state. Assuming that L will be quite small, when the
switch starts to the conduct the current should be established relatively quickly. This is
required if good simulation results are to be achieved. If the valve will stay in its switching
state long enough so that the inductor representing it charges to its full capacity then the
1
energy stored equals 𝐸𝑠𝑐 = 2 𝐿𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡 . When the switch turns off then the energy
stored is lost, because the L branch is abruptly changed to an RC branch.

valve OFF
Iconduct

valve ON Valve Current Response (Ideal)

Valve Current Response ( L branch)

Figure 8.2: Comparison of current establishment in ideal switch and small time-step switch

Consider the diagram of Figure 8.3 which shows a comparison of the voltage established
across an ideal switch versus the voltage established across the capacitor in an RC circuit.
Assuming that the capacitance will be quite small, when the switch is opened the voltage
across the capacitor should be established fairly quickly. This is required if good simulation
results are to be achieved. If the valve stays in its switching state long enough so that the
capacitor representing it charges to its full capacity the energy stored will be 𝐸𝑜𝑐 =
𝐶𝑣𝑏𝑙𝑜𝑐𝑘 . When the switch turns on again the energy stored is lost, because the RC branch
will abruptly be changed to an L branch.

valve ON
Vblock

valve OFF Valve Voltage Response (Ideal)

Valve Voltage Response (RC branch)

Figure 8.3: Comparison of voltage established across an ideal switch and the capacitance in
an RC circuit

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The goal is to minimize the total energy lost during a switching cycle. This quantity is given
by Eq. 8.6.

𝐸𝑡𝑜𝑡𝑎𝑙 = 𝐸𝑠𝑐 + 𝐸𝑜𝑐


1
2 2
𝐸𝑡𝑜𝑡𝑎𝑙 = 2 𝐿𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡 + 𝐶𝑣𝑏𝑙𝑜𝑐𝑘 [ Eq. 8.6 ]

It can be shown that this is achieved when the Eq. 8.7 is satisfied. This is the last of the 3
equations that are used to constrain the selection of R, L and C in the chosen valve
representation.

2 2 1
𝐶𝑣𝑏𝑙𝑜𝑐𝑘 = 2 𝐿𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡 [ Eq. 8.7 ]

Equations 8.1, 8.5 and 8.7 can be solved for the parameters R, L and C. The results are given in
Equations 8.8 through 8.10.
∆t 𝑣𝑏𝑙𝑜𝑐𝑘
𝐿 = √2(𝛿 + √𝛿 2 + 1) [ Eq. 8.8 ]
2 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡

2
∆t 1
𝐶 = ((𝛿 + √𝛿 2 + 1) 2 ) 𝐿
[ Eq. 8.9 ]

2𝐿 ∆𝑡
𝑅= − [ Eq. 8.10 ]
∆𝑡 2𝐶

The parameters ∆t, δ, vblock and iconduct are all assumed to be known. The small time-step size is
calculated during the compile. The damping, blocked voltage during switching and conduction
current during switching are all user specifiable parameters. Components that model switches
using the method described above will generally have a properties tab labelled VALVE
PARAMETERS. Figure 8.4 shows such a tab for the rtds_vsc_PH3LEV2 component.

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Figure 8.4: Properties tab where valve parameters are specified

After solving for R, L and C it is possible to write equations for XC and XL as a function of frequency.
These equations are given in Eq. 8.11 and Eq. 8.12.
∆t 𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝐿 = √2 ∙ 2𝜋𝑓(𝛿 + √𝛿 2 + 1) [ Eq. 8.11 ]
2 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡

√2 𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝐶 = ∆t [ Eq. 8.12 ]
2𝜋𝑓(𝛿+√𝛿 2 +1) 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡
2

Given that the damping factor, δ, is limited to lie between 0.7 and 1.33 and that the time-step,
∆t, will generally be on the order of 2s. Assuming that δ ~ 1 and ∆t ~ 2s, Eq. 8.11 and Eq.
8.12 above are approximately equal to Eq. 8.13 and Eq. 8.14 below.
𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝐿 ≈ 1 × 10−5 𝑓 𝑖 [ Eq. 8.13 ]
𝑐𝑜𝑛𝑑𝑢𝑐𝑡

1×105 𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝐶 ≈ [ Eq. 8.14 ]
𝑓 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡

𝑣𝑏𝑙𝑜𝑐𝑘 𝑣𝑏𝑙𝑜𝑐𝑘
By inspection up to about 10kHz, XL is at most about 0.1 𝑖 and XC is at least 10 𝑖 . If
𝑐𝑜𝑛𝑑𝑢𝑐𝑡 𝑐𝑜𝑛𝑑𝑢𝑐𝑡
𝑣𝑏𝑙𝑜𝑐𝑘
the ratio is selected as the base impedance then a short will be a relatively small
𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡
impedance and an open circuit will be a relatively large impedance.

Strategy for Selecting V block and I conduct


Quite often the default values for vblock and iconduct are reasonable and do not need to be changed.
If there is, however, some concern about whether the switch is approximating an open circuit
when OFF and a closed circuit when ON then the ratio of vblock and iconduct can be changed so that
it is approximately equal to the base impedance of the system. In cases where abnormally high

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losses are observed, the values of vblock and iconduct can be adjusted so that they more accurately
represent the average blocked voltage and the average conducted current seen by the switch. A
balance must be struck between (1) having the switch represent a large impedance when off/
small impedance when on and (2) avoiding excessive losses which are anomalies of the modeling
approach.

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9 DISTRIBUTING PROCESSING LOAD OVER TWO PROCESSORS

The method used for modeling a switch in small time-step simulations begins to lose its accuracy
as the time-step increases. It is therefore desirable to keep the time-step small, preferably below
2.5s. The time-step used is a function of the complexity of the small time-step circuit; as the
number of components inside a VSC bridge box grows the time-step will increase. An estimate of
the small time-step is calculated when the case is compiled and the calculated value is written to
the MAP file. Inside the MAP file a section similar to the one listed below shows the small time-
step that is used.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
RISC-based VSC_NET1 Bridge model named: VB1
in subsystem: #1
is assigned to GPC Card #1 Processor B

The Bridge model has 28 small


time-steps in each large time-step.

The small time-step size is 1.785714 microseconds.

The calculation time permitted for each


small time-step is 1724 nanoseconds.

There is no T0 output. If there had been


it would have gone out in small step number: 2.
Any T2 output is scheduled for small step number: 14.

The small-step clock count on processor A


is expected to be 1309 clocks without the margin.
The User specified margin is 360 nanoseconds ( 360 clocks ).

The VSC network solution method on 1st processor


is W-matrix.
Estimated W-matrix = 246 clocks.
Estimated Gi-matrix = 434 clocks.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

If the time-step becomes large then it is advisable to distribute the calculation load over two
processors in order to reduce it. As a general guideline, if a small time-step circuit has more than
18 single-phase switches or if several computation-heavy components (ie: small time-step
machine model) are used then it is a good idea to use two processors. If the small time-step is
larger than 3s then a warning will be issued, this signals to the user that the processing load
should be re-distributed.

-62-
By default the small time-step bridge box taken from the library will run on a single processor. In
order to use two processors for the calculation of the small time-step simulation the parameter
rqnmp inside the VSC bridge box must be changed to Two. This is shown in Figure 9.1.

Figure 9.1: Running small time-step simulation on two processors

After two processors have been requested in the bridge box’s properties menu then individual
components must be allocated to either processor one or processor two. Most of the small time-
step components will have a parameter called prc12; this parameter can be assigned a value of
either one or two and allows for the allocation of a component to a particular processor when
two processors have been requested by a bridge box. If only one processor has been requested
then all components will be placed on that processor. Figure 9.2 highlights the prc12 parameter.

Figure 9.2: The prc12 parameter used to assign small time-step components to a particular
processor

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10 REFERENCES

[1] T. Maguire and J. Giesbrecht. Small Time-step (<2 Sec) VSC Model for Real Time Digital
Simulator. International Conference on Power System Transients (IPST’05). Montreal, Canada.
June 19-23, 2005.

[2] Mohan, Undeland, and Robbins. Power Electronics: Converters, Applications, and Design. 2nd
Ed. Toronto: John Wiley & Sons, Inc , 1995

[3] Prabha Kundur. Power System Stability and Control. Toronto. McGraw-Hill, Inc. 1994

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