L.C.D L.E.D T.

V Panels Connection and Voltages Understanding

Here we talking about the main voltages and pin connection of L.C.D and L.E.D T.Vs

Panels, every technician should know where to test and how to check voltages of each connection as
they mention in Service Manual or schematic diagram or at least you should know the basic working
voltages.

Connection Name Connection Working Voltages

1. VGL in Driver negative P.supply1 Around -10.5v

2. VCL in Driver negative p.supply2 Around -10v to -12v

3. VSS Digital ground GND

4. VDD VDD is the logic supply input for the scan driver.

5. VGH Supply LCM driver output Around 12v+ to 19.5v+

6. STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is
used to generate the high-voltage STVP output. PulseL.C.D L.E.D T.V Panels Connection and Voltages
Understanding

Here we talking about the main voltages and pin connection of L.C.D and L.E.D T.Vs

Panels, every technician should know where to test and how to check voltages of each connection as
they mention in Service Manual or schematic diagram or at least you should know the basic working
voltages.

Connection Name Connection Working Voltages

1. VGL in Driver negative P.supply1 Around -10.5v

2. VCL in Driver negative p.supply2 Around -10v to -12v

3. VSS Digital ground GND

4. VDD VDD is the logic supply input for the scan driver.

5. VGH Supply LCM driver output Around 12v+ to 19.5v+

6. STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is
used to generate the high-voltage STVP output. Pulse

7. CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing of the CKV1 and CKVB1 outputs,
which change state (by first sharing charge) on its falling edge.

Pulse

8. CPV2
9. V.COM out Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2
outputs, which change state (by first sharing charge) on its falling edge.

Common signal output TFT Clock pulse

Signal pulse

10. POL in Supply input common signal Signal

11. VDC in Supply +5.0v min

12. VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP
high-voltage driver outputs. Around 20v+

13. V-OFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP
high-voltage driver outputs. Around 8V-

Brief Details of Panels Connection Points

VDD VDD is the logic supply input for the scan driver.

VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP high-
voltage driver outputs.

VOFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP high-
voltage driver outputs.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.

CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing of the CKV1 and CKVB1 outputs, which
change state (by first sharing charge) on its falling edge.

CPV2 Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2 outputs, which
change state (by first sharing charge) on its falling edge.
EN Enables the MAX17121. Drive EN high to start up the MAX17121 after a delay time, which is
set by a capacitor at DLY.

CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high
impedance whenever CKV1 is high impedance.

CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high
impedance whenever CKV2 is high impedance.

CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2

and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2,
sharing charge between the capacitive loads on these two outputs.

CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are
both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing
charge between the capacitive loads on these two outputs.

STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is
connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high
impedance.

DLY Startup Delay Setting. Connect a capacitor to adjust the delay

DISH VOFF Discharge Connection. Pulling DISH below ground activates an internal connection
between VOFF and GND, rapidly discharging the VOFF supply. Typically, DISH is capacitive connected
to VDD, so that when VDD falls, VOFF is discharged.

VCOM Operational Amplifier Output

CKV High-Voltage, Gate-Pulse Output. When enabled, CKV toggles between its high state
(connected to GON) and its low state (connected to GOFF) on each falling edge of the CPV input.
Further, CKV is high impedance whenever CPV and OE are both low and whenever CPV is low and
OECON is high.

CKVCS CKV Charge-Sharing Connection. CKVCS connects to CKV whenever CKV is high impedance to
allow connection to CKVB, sharing charge between the capacitive loads on these two outputs.

CKVBCS CKVB Charge-Sharing Connection. CKVBCS connects to CKVB whenever CKVB is high
impedance to allow connection to CKV, sharing charge between the capacitive loads on these two
outputs.

CKVB High-Voltage, Gate-Pulse Output. CKVB is the inverse of CKV during active states and is high
impedance whenever CKV is high impedance.

STVP High-Voltage, Start-Pulse Output. STVP is low (connected to GOFF) whenever STV is low and
is high (connected to GON) only when STV is high and CPV and OE are both low. When STV is high
and either CPV or OE is high, STVP is high impedance.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.
OECON Active-Low, Output-Enable Timing Input. OECON is driven by an RC-filtered version of the OE
input signal. If OE remains high long enough for the resistor to charge the capacitor up to the OECON
threshold, the OE signal is masked until OE goes low and the capacitor is discharged below the
threshold through the resistor.

OE Active-High, Gate-Pulse Output Enable. CKV and CKVB leave the high-impedance charge-
sharing state on the rising edge of OE.

CPV Vertical Clock-Pulse Input. CPV controls the timing of the CKV and CKVB outputs that change
state (by first sharing charge) on its falling edge.

GND Logic Ground

DISH GOFF Discharge Input. Pulling DISH below ground activates an internal connection between
GOFF and GND, rapidly discharging the GOFF supply. Typically, DISH is capacitively connected to IN,
so that when VIN falls GOFF is discharged.

VDD Supply Input. Logic supply input for the VCOM calibrator. Bypass to GND through a minimum
0.1μF capacitor.

WPN Active-Low, Write-Protect Input. When WPN is low, I2C commands are ignored and the
VCOM calibrator settings cannot be modified.

SCLS Alternate I2C-Compatible Clock Input. When WPN is high, SCLS connects to SCL to drive SCL
from an alternate clock source.

SCL I2C-Compatible Clock Input and Output

SDA I2C-Compatible Serial Bidirectional Data Line

WPP Write-Protect Output. WPP is the inverse of WPN. It can be used to control active-high,
write-protect inputs on other devices.

SET Full-Scale, Sink-Current Adjustment Input. Connect a resistor, RSET, from SET to GND to set
the full-scale adjustable sink current that is VBOOST / (20 x RSET). IOUT is equal to the current
through RSET.

VL 3.3V On-Chip Regulator Output. This regulator powers internal analog circuitry for the step-
up regulator, op amp, and VCOM calibrator. External loads up to 10mA can be powered. Bypass VL to
GND with a 0.22μF or greater ceramic capacitor.

BGND Amplifier Ground

BOOST Operational Amplifier Supply Input. Connect to VMAIN (Figure 2) and bypass to BGND with a
1μF or greater ceramic capacitor.

OUT Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp
input POS (between BOOST and GND) that determines the VCOM output voltage. IOUT lowers the
divider voltage by a programmable amount.

POS Operational Amplifier No inverting Input

NEG Operational Amplifier Inverting Input

VCOM Operational Amplifier Output

SHDN Shutdown Control Input. Pull SHDN low to disable the step-up regulator. The VCOM
calibrator, op amp, and scan driver functions remain enabled.

IN Step-Up Regulator Supply Input. Bypass IN to AGND (pin 34) with a 1μF or greater ceramic
capacitor.

LX Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.

PGND Power Ground. Source connection of the internal step-up regulator power switch.

FB Feedback Input. Reference voltage is 1.24V nominal. Connect external resistor-divider

midpoint here and minimize trace area. Set VOUT according to: VOUT = 1.24V (1 + R1/R2).

COMP Compensation Input for Error Amplifier. Connect a series RC from COMP to AGND. Typical
values are 180k and 470pF.

AGND Ground

GOFF Gate-Off Supply. GOFF is the negative supply voltage for the CKV, CKVB, and STVP high-
voltage driver outputs. Bypass to PGND with a minimum of 0.1μF ceramic capacitor.

GON Gate-On Supply. GON is the positive supply voltage for the CKV, CKVB, and STVP high-voltage
driver outputs. Bypass to VMAIN or PGND with a minimum of 0.1μF ceramic capacitor.

EP Exposed Backside Pad. Connect to the analog ground plane through multiple vias to enhance
thermal performance.

CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high
impedance whenever CKV1 is high impedance.

STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is
connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high
impedance.

CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high
impedance whenever CKV2 is high impedance.

CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2

and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2,
sharing charge between the capacitive loads on these two outputs.

CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are
both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing
charge between the capacitive loads on these two outputs.

CKV2 High-Voltage Scan-Drive Output. When enabled, CKV2 toggles between its high state
(connected to VON) and its low state (connected to VOFF) on each falling edge of the CPV2 input.
Further, CKV2 is high impedance whenever CPV2 and STV are both low.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.

CPV1 Vertical Clock-Pulse Input.7. CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing
of the CKV1 and CKVB1 outputs, which change state (by first sharing charge) on its falling edge.
 Pulse

8. CPV2

9. V.COM out Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2
outputs, which change state (by first sharing charge) on its falling edge.

Common signal output TFT Clock pulse

Signal pulse

10. POL in Supply input common signal Signal

11. VDC in Supply +5.0v min

12. VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP
high-voltage driver outputs. Around 20v+

13. V-OFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP
high-voltage driver outputs. Around 8V-

Brief Details of Panels Connection Points

VDD VDD is the logic supply input for the scan driver.

VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP high-
voltage driver outputs.

VOFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP high-
voltage driver outputs.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.

CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing of the CKV1 and CKVB1 outputs, which
change state (by first sharing charge) on its falling edge.
CPV2 Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2 outputs, which
change state (by first sharing charge) on its falling edge.

EN Enables the MAX17121. Drive EN high to start up the MAX17121 after a delay time, which is
set by a capacitor at DLY.

CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high
impedance whenever CKV1 is high impedance.

CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high
impedance whenever CKV2 is high impedance.

CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2

and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2,
sharing charge between the capacitive loads on these two outputs.

CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are
both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing
charge between the capacitive loads on these two outputs.

STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is
connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high
impedance.

DLY Startup Delay Setting. Connect a capacitor to adjust the delay

DISH VOFF Discharge Connection. Pulling DISH below ground activates an internal connection
between VOFF and GND, rapidly discharging the VOFF supply. Typically, DISH is capacitive connected
to VDD, so that when VDD falls, VOFF is discharged.

VCOM Operational Amplifier Output

CKV High-Voltage, Gate-Pulse Output. When enabled, CKV toggles between its high state
(connected to GON) and its low state (connected to GOFF) on each falling edge of the CPV input.
Further, CKV is high impedance whenever CPV and OE are both low and whenever CPV is low and
OECON is high.

CKVCS CKV Charge-Sharing Connection. CKVCS connects to CKV whenever CKV is high impedance to
allow connection to CKVB, sharing charge between the capacitive loads on these two outputs.

CKVBCS CKVB Charge-Sharing Connection. CKVBCS connects to CKVB whenever CKVB is high
impedance to allow connection to CKV, sharing charge between the capacitive loads on these two
outputs.

CKVB High-Voltage, Gate-Pulse Output. CKVB is the inverse of CKV during active states and is high
impedance whenever CKV is high impedance.

STVP High-Voltage, Start-Pulse Output. STVP is low (connected to GOFF) whenever STV is low and
is high (connected to GON) only when STV is high and CPV and OE are both low. When STV is high
and either CPV or OE is high, STVP is high impedance.
STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.

OECON Active-Low, Output-Enable Timing Input. OECON is driven by an RC-filtered version of the OE
input signal. If OE remains high long enough for the resistor to charge the capacitor up to the OECON
threshold, the OE signal is masked until OE goes low and the capacitor is discharged below the
threshold through the resistor.

OE Active-High, Gate-Pulse Output Enable. CKV and CKVB leave the high-impedance charge-
sharing state on the rising edge of OE.

CPV Vertical Clock-Pulse Input. CPV controls the timing of the CKV and CKVB outputs that change
state (by first sharing charge) on its falling edge.

GND Logic Ground

DISH GOFF Discharge Input. Pulling DISH below ground activates an internal connection between
GOFF and GND, rapidly discharging the GOFF supply. Typically, DISH is capacitively connected to IN,
so that when VIN falls GOFF is discharged.

VDD Supply Input. Logic supply input for the VCOM calibrator. Bypass to GND through a minimum
0.1μF capacitor.

WPN Active-Low, Write-Protect Input. When WPN is low, I2C commands are ignored and the
VCOM calibrator settings cannot be modified.

SCLS Alternate I2C-Compatible Clock Input. When WPN is high, SCLS connects to SCL to drive SCL
from an alternate clock source.

SCL I2C-Compatible Clock Input and Output

SDA I2C-Compatible Serial Bidirectional Data Line

WPP Write-Protect Output. WPP is the inverse of WPN. It can be used to control active-high,
write-protect inputs on other devices.

SET Full-Scale, Sink-Current Adjustment Input. Connect a resistor, RSET, from SET to GND to set
the full-scale adjustable sink current that is VBOOST / (20 x RSET). IOUT is equal to the current
through RSET.

VL 3.3V On-Chip Regulator Output. This regulator powers internal analog circuitry for the step-
up regulator, op amp, and VCOM calibrator. External loads up to 10mA can be powered. Bypass VL to
GND with a 0.22μF or greater ceramic capacitor.

BGND Amplifier Ground

BOOST Operational Amplifier Supply Input. Connect to VMAIN (Figure 2) and bypass to BGND with a
1μF or greater ceramic capacitor.

OUT Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp
input POS (between BOOST and GND) that determines the VCOM output voltage. IOUT lowers the
divider voltage by a programmable amount.

POS Operational Amplifier No inverting Input

NEG Operational Amplifier Inverting Input

VCOM Operational Amplifier Output

SHDN Shutdown Control Input. Pull SHDN low to disable the step-up regulator. The VCOM
calibrator, op amp, and scan driver functions remain enabled.

IN Step-Up Regulator Supply Input. Bypass IN to AGND (pin 34) with a 1μF or greater ceramic
capacitor.

LX Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.

PGND Power Ground. Source connection of the internal step-up regulator power switch.

FB Feedback Input. Reference voltage is 1.24V nominal. Connect external resistor-divider

midpoint here and minimize trace area. Set VOUT according to: VOUT = 1.24V (1 + R1/R2).

COMP Compensation Input for Error Amplifier. Connect a series RC from COMP to AGND. Typical
values are 180k and 470pF.

AGND Ground

GOFF Gate-Off Supply. GOFF is the negative supply voltage for the CKV, CKVB, and STVP high-
voltage driver outputs. Bypass to PGND with a minimum of 0.1μF ceramic capacitor.

GON Gate-On Supply. GON is the positive supply voltage for the CKV, CKVB, and STVP high-voltage
driver outputs. Bypass to VMAIN or PGND with a minimum of 0.1μF ceramic capacitor.

EP Exposed Backside Pad. Connect to the analog ground plane through multiple vias to enhance
thermal performance.

CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high
impedance whenever CKV1 is high impedance.

STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is
connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high
impedance.

CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high
impedance whenever CKV2 is high impedance.

CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2

and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2,
sharing charge between the capacitive loads on these two outputs.

CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are
both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing
charge between the capacitive loads on these two outputs.

CKV2 High-Voltage Scan-Drive Output. When enabled, CKV2 toggles between its high state
(connected to VON) and its low state (connected to VOFF) on each falling edge of the CPV2 input.
Further, CKV2 is high impedance whenever CPV2 and STV are both low.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.
CPV1 Vertical Clock-Pulse Input. L.C.D L.E.D T.V Panels Connection and Voltages Understanding

Here we talking about the main voltages and pin connection of L.C.D and L.E.D T.Vs

Panels, every technician should know where to test and how to check voltages of each connection as
they mention in Service Manual or schematic diagram or at least you should know the basic working
voltages.

Connection Name Connection Working Voltages

1. VGL in Driver negative P.supply1 Around -10.5v

2. VCL in Driver negative p.supply2 Around -10v to -12v

3. VSS Digital ground GND

4. VDD VDD is the logic supply input for the scan driver.

5. VGH Supply LCM driver output Around 12v+ to 19.5v+

6. STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is
used to generate the high-voltage STVP output. Pulse

7. CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing of the CKV1 and CKVB1 outputs,
which change state (by first sharing charge) on its falling edge.

Pulse

8. CPV2

9. V.COM out Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2
outputs, which change state (by first sharing charge) on its falling edge.

Common signal output TFT Clock pulse

Signal pulse

10. POL in Supply input common signal Signal

11. VDC in Supply +5.0v min

12. VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP
high-voltage driver outputs. Around 20v+

13. V-OFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP
high-voltage driver outputs. Around 8V-

Brief Details of Panels Connection Points

VDD VDD is the logic supply input for the scan driver.

VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP high-
voltage driver outputs.

VOFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP high-
voltage driver outputs.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.

CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing of the CKV1 and CKVB1 outputs, which
change state (by first sharing charge) on its falling edge.

CPV2 Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2 outputs, which
change state (by first sharing charge) on its falling edge.

EN Enables the MAX17121. Drive EN high to start up the MAX17121 after a delay time, which is
set by a capacitor at DLY.

CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high
impedance whenever CKV1 is high impedance.

CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high
impedance whenever CKV2 is high impedance.

CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2

and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2,
sharing charge between the capacitive loads on these two outputs.

CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are
both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing
charge between the capacitive loads on these two outputs.

STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is
connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high
impedance.

DLY Startup Delay Setting. Connect a capacitor to adjust the delay

DISH VOFF Discharge Connection. Pulling DISH below ground activates an internal connection
between VOFF and GND, rapidly discharging the VOFF supply. Typically, DISH is capacitive connected
to VDD, so that when VDD falls, VOFF is discharged.

VCOM Operational Amplifier Output

CKV High-Voltage, Gate-Pulse Output. When enabled, CKV toggles between its high state
(connected to GON) and its low state (connected to GOFF) on each falling edge of the CPV input.
Further, CKV is high impedance whenever CPV and OE are both low and whenever CPV is low and
OECON is high.

CKVCS CKV Charge-Sharing Connection. CKVCS connects to CKV whenever CKV is high impedance to
allow connection to CKVB, sharing charge between the capacitive loads on these two outputs.

CKVBCS CKVB Charge-Sharing Connection. CKVBCS connects to CKVB whenever CKVB is high
impedance to allow connection to CKV, sharing charge between the capacitive loads on these two
outputs.

CKVB High-Voltage, Gate-Pulse Output. CKVB is the inverse of CKV during active states and is high
impedance whenever CKV is high impedance.

STVP High-Voltage, Start-Pulse Output. STVP is low (connected to GOFF) whenever STV is low and
is high (connected to GON) only when STV is high and CPV and OE are both low. When STV is high
and either CPV or OE is high, STVP is high impedance.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.

OECON Active-Low, Output-Enable Timing Input. OECON is driven by an RC-filtered version of the OE
input signal. If OE remains high long enough for the resistor to charge the capacitor up to the OECON
threshold, the OE signal is masked until OE goes low and the capacitor is discharged below the
threshold through the resistor.

OE Active-High, Gate-Pulse Output Enable. CKV and CKVB leave the high-impedance charge-
sharing state on the rising edge of OE.

CPV Vertical Clock-Pulse Input. CPV controls the timing of the CKV and CKVB outputs that change
state (by first sharing charge) on its falling edge.

GND Logic Ground

DISH GOFF Discharge Input. Pulling DISH below ground activates an internal connection between
GOFF and GND, rapidly discharging the GOFF supply. Typically, DISH is capacitively connected to IN,
so that when VIN falls GOFF is discharged.

VDD Supply Input. Logic supply input for the VCOM calibrator. Bypass to GND through a minimum
0.1μF capacitor.

WPN Active-Low, Write-Protect Input. When WPN is low, I2C commands are ignored and the
VCOM calibrator settings cannot be modified.
SCLS Alternate I2C-Compatible Clock Input. When WPN is high, SCLS connects to SCL to drive SCL
from an alternate clock source.

SCL I2C-Compatible Clock Input and Output

SDA I2C-Compatible Serial Bidirectional Data Line

WPP Write-Protect Output. WPP is the inverse of WPN. It can be used to control active-high,
write-protect inputs on other devices.

SET Full-Scale, Sink-Current Adjustment Input. Connect a resistor, RSET, from SET to GND to set
the full-scale adjustable sink current that is VBOOST / (20 x RSET). IOUT is equal to the current
through RSET.

VL 3.3V On-Chip Regulator Output. This regulator powers internal analog circuitry for the step-
up regulator, op amp, and VCOM calibrator. External loads up to 10mA can be powered. Bypass VL to
GND with a 0.22μF or greater ceramic capacitor.

BGND Amplifier Ground

BOOST Operational Amplifier Supply Input. Connect to VMAIN (Figure 2) and bypass to BGND with a
1μF or greater ceramic capacitor.

OUT Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp
input POS (between BOOST and GND) that determines the VCOM output voltage. IOUT lowers the
divider voltage by a programmable amount.

POS Operational Amplifier No inverting Input

NEG Operational Amplifier Inverting Input

VCOM Operational Amplifier Output

SHDN Shutdown Control Input. Pull SHDN low to disable the step-up regulator. The VCOM
calibrator, op amp, and scan driver functions remain enabled.

IN Step-Up Regulator Supply Input. Bypass IN to AGND (pin 34) with a 1μF or greater ceramic
capacitor.

LX Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.

PGND Power Ground. Source connection of the internal step-up regulator power switch.

FB Feedback Input. Reference voltage is 1.24V nominal. Connect external resistor-divider

midpoint here and minimize trace area. Set VOUT according to: VOUT = 1.24V (1 + R1/R2).

COMP Compensation Input for Error Amplifier. Connect a series RC from COMP to AGND. Typical
values are 180k and 470pF.

AGND Ground

GOFF Gate-Off Supply. GOFF is the negative supply voltage for the CKV, CKVB, and STVP high-
voltage driver outputs. Bypass to PGND with a minimum of 0.1μF ceramic capacitor.

GON Gate-On Supply. GON is the positive supply voltage for the CKV, CKVB, and STVP high-voltage
driver outputs. Bypass to VMAIN or PGND with a minimum of 0.1μF ceramic capacitor.
EP Exposed Backside Pad. Connect to the analog ground plane through multiple vias to enhance
thermal performance.

CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high
impedance whenever CKV1 is high impedance.

STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is
connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high
impedance.

CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high
impedance whenever CKV2 is high impedance.

CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2

and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2,
sharing charge between the capacitive loads on these two outputs.

CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are
both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing
charge between the capacitive loads on these two outputs.

CKV2 High-Voltage Scan-Drive Output. When enabled, CKV2 toggles between its high state
(connected to VON) and its low state (connected to VOFF) on each falling edge of the CPV2 input.
Further, CKV2 is high impedance whenever CPV2 and STV are both low.

STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to
generate the high-voltage STVP output.

• CPV1 Vertical Clock-Pulse Input.

• Now I am going to tell about the flash ic The flash ic is used in the lcd led tv to store the
firmware That firmware will be used by the Micro Controller Unit There are different types of name
to the flash ic SPI flash memory Serial Peripheral Interface Serial Flash Memory

• Serial Nor Flash Memory Serial SPI Flash Memory IC How to identify that is the flash ic There
are different manufacturers are there

• the first name be will the company code after that it start with the number 25

• after that the memory size will be mentioned on that Winbond flash ic start with the
W25pXX w25qxx W25Xxx NAND flash memory is a type of non-volatile storage technology that does
not require power to retain data. An important goal of NAND flash development has been to reduce
the cost per bit and increase maximum chip capacity so that flash memory can compete with
magnetic storage devices like hard disks

• Flash is a electronics non volatile storage medium which can be erased electronically and
reprogramed

• Flash will be corrupted so often

• it will store the digital data Flash memory is computer storage memory that can be
electrically erased and re-written. Flash is used as storage in a number of devices, including cellular
phones, digital cameras and MP3 players, in addition to USB flash drives. In nand flash there is no
need to acdet signal

• Atmel flash comes with the number AT 25xxx

• Amic company with A25xxx

• Eon company start with EN 25Qxx

• Microchip start with SST25Lxx Armel 25256

• spikes in the power These flash ic comes with 8pin

• pin number 1 is chip select pin number 2 serial data input

• 3 is serial data output that will we be write protect pin number 4 is ground pin no 5 is serial
data input pin number 6 is clock input pin number 7 is hold

• this is used to pause the device pin number 8 is supply

• when ever you are replacing the fash ic you have to replace with the same memory or a
little bit more but should not be more

• you can use any company

• for that you have to see the data sheet

• For the 24C series EEPROM IC, it can be divided into two:

• 24C16 is downward compatibility for replace 24C02, 24C04, 24C08. The

• 24C08 can replace 24C04 and 24C02, 24C04 can replace 24C02. But the 24C32

• cannot replace 24C02, 24C04, 24C08 and 24C16. The 24C64 can replace

• 24C32. The 24C128 can replace 24C64 and 24C32. Please make sure that it is

• using the same IC packages. Because some different packages, their Vcc input

• voltages will different. For more details, please refer to their own datasheet and

• it is save before replace it.

• * EEPROM= Electrically Erasable and Programmable Read-Only Memory

• 24C01= 1K bits (128 x 8= 1024 bits)

• 24C02= 2K bits (256 x 8= 2048 bits)

• 24C04= 4K bits (512 x 8= 4096 bits)

• 24C08= 8K bits (1024 x 8= 8192 bits)

• 24C16= 16K bits (2048 x 8= 16384 bits)

• And so on….....

• 16 bit can be replaced with 32 bit

• you should not replace with 64 or 128 bit For example, in the Samsung 943 series LCD
monitor

• main board, commonly using this EEPROM IC S24CS08A (Seiko Instrument)

• and causing lots of the problem. So you can use the AT24C08A (Atmel) as an

• equivalent. And it can work very well.

• The 24Cxx series EEPROM IC pin7 (WP- Write Protect) have two kinds of

• method to connect it. The EEPROM IC manufacturer like AT (Atmel), ST

• (STMicroelectronic) and BR (ROHM), their EEPROM IC pin7 need to connect

• to the ground to allow data write into the EEPROM memory. 27U1G8 in AOC 32" LED TV
when try to copy one error coming "162 area blocked" what is this error PCF Series EEPROM IC

• For Philips EEPROM IC, most of their PCF series IC are compatible with

• 24Cxx series. For example, they can replace with:

• 24C01 ? PCF8522

• 24C02 ? PCF8582

• 24C04 ? PCF8592

• The PCF8522 and PCF8581/PCF8582 their connection for pin7 (WP) are

• different. PCF8522 pin7 need to connect to ground. The PCF8581 and PCF8582

• their pin7 need to connect it as “Active High”. The substitute for this PCF series

• IC also same, choose the bigger size to replace a bit small size memory. For

• example, PCF8582 can replace PCF8581; PCF8598 can replace PCF8594

• EEPROM IC.

• Be careful of different EEPROM IC packages will have different Vcc input

• voltage range. For example Vcc input voltage range for Atmel series EEPROM

• IC: 4.5~5.5V, 2.5V~5.5V, 1.8V~5.5V and 1.7V~5.5V. 1, 6, 2 would be pin showing not
connected If the EEPROM IC damage, the best choice is use an original part number. If

• can’t get it, highly recommend to use same specification part number but

• different brands IC. For example, the original part number is ST24C16, so you

• can use AT24C16 EEPROM IC to replace it.

• Example of that induct coil in power supply so that flash failure can be avoided. When find
the equivalent EEPROM IC, need to find a memory size bigger

• than the original one. For example, 24C02 can be replaced by 24C04 or 24C08.
• Please make sure not to use too bigger memory size EEPROM IC, sometime it

• could be malfunction or other strange problem will occur. Some model TV can’t use the
bigger memory size or different brands of

• EEPROM IC to replace their original EEPROM IC. Because of this TV Main

• board CPU will detect the memory IC their ID number. If the number is

• different, the CPU will not accept it and the Main board will not operate or

• strange problem will occur. Some 24W series EEPROM IC their pin7 (WP) connect to MCU, so
this type

• of EEPROM IC is highly recommend to use their original part number memory

• IC.

• Flash problem may be due to so many reason 1 virus from pendrive 2 lightning strike 3
3.3v regulators problem etc Lastly, if using different packaging EEPROM IC, make sure that their Vcc

• pin input voltage suitable the original memory IC or cover in the voltage range.

• lcd led tv fault finding methods

• Common faults in lcd led tv ‘s are

• power supply

• mother board

• t-con board

• back light

• inverter board (some time combine with motherboard or power supply board)

• lcd display matrix problem .

• power supply

• This is the most important part in lcd led tv that most often gets fault . it contains

• A.C line filter

• bridge rectifier

• mosfet for switching

• PWM chip for switching mosfet

• opto coupler for feedback supply regulator by ka431

• ripple filter

• mother board

• this second important component that often gets complained

• voltage regulators used for proper voltages like 3.3v ,2.5v,1.8v,1.2v, some cpu consume 0.9v
in lg tvs

• after gets proper voltage cpu reset , XTL1,XTL2, SIGNALS MAKE CPU WORK

• CPU loads boot programme from flash chip via ram chip .

• if boot loader works properly cpu work on further action

• t-con board

• This is also a important component need to look

• panel circuit impotant signals CKV1,CKV2,CKVB1,CKVB2 , VSS, STVP

• CKV1

• HIGH VOLTAGE SCAN DRIVE OUTPUT.WHEN ENABLED,CKV1 toggles between its high state
(connected to von) and its low state (connected to VOFF) on each fall ing edge of the CPV1 input.
further CKV1 is high impedence whenever CPV1 AND STV are low

• CKV2

• HIGH VOLTAGE SCAN DRIVE OUTPUT.WHEN ENABLED,CKV2 toggles between its high state
(connected to von) and its low state (connected to VOFF) on each fall ing edge of the CPV2 input.
further CKV2 is high impedence whenever CPV2 AND STV are low

• CKVB1

• HIGH VOLTAGE Scan drive output .CKVB1 IS THE INVERSE OF CKV1 during active states and is
high impedence whenever CKV1 IS HIGH IMPEDENCE

• CKVB2

• HIGH VOLTGE SCAN DRIVE OUTPUT. CKVB2 is the inverse of CKV2 DURING Active states and
is high impedence whenever CKV2 IS HIGH IMPEDENCE.

• VSS/VOFF

•
• GATE OFF SUPPLY VOFF IS THE NEGATIVE SUPPLYVOLTAGE FOR THE CKV_CKVB_ AND STVP
HIGH VOLTAGE DRIVER OUTPUTS