VLSI LAB

SYED HABEEB-1PE16EC161
SUNIL.M-1PE16EC160
ALL GATES

module gates(a,b,f1,f2,f3,f4,f5,f6);

input a,b;

output f1,f2,f3,f4,f5,f6;

assign f1=a&b;

assign f2=a|b;

assign f3=~a;

assign f4=~(a&b);

assign f5=~(a|b);

assign f6=a^b;

endmodule

TESTBENCH

module tb;

reg a,b;

wire f1,f2,f3,f4,f5,f6;

gates x1(a,b,f1,f2,f3,f4,f5,f6);

initial begin

#0 a=1'b0;b=1'b0;

#10 a=1'b0;b=1'b1;

#10 a=1'b1;b=1'b0;

#10 a=1'b1;b=1'b1;

end

initial
#110 $finish;

Endmodule

WAVEFORM

COUNTERS

ASYNCHROUNS COUNTER

module asyn_ctr(input clk,clear,output [3:0]count);

reg [3:0]count;

always@(negedge clk)

begin

if(clear)

count=4'b0000;

else

count[0]=~count[0];

end
always@(negedge count[0])

begin

count[1]=~count[1];

end

always@(negedge count[1])

begin

count[2]=~count[2];

end

always@(negedge count[2])

begin

count[3]=~count[3];

end

endmodule

TESTBENCH

module asyn_tb();

reg clk,clear;

wire [3:0]count;

asyn_ctr n1(clk,clear,count);

initial begin

clk=1'b0;

forever #5 clk=~clk;

end

initial begin

#0 clear=1'b1;

#10 clear=1'b0;

#150 $finish;

end

endmodule
WAVEFORM

SYNCHROUNS

module syn_ctr(input up,clk,clr,output [3:0]count);

reg [3:0]count;

always@(negedge clk,posedge clr)

begin

if(clr)

count=4'b0000;

else

begin

if(up)
count=count+1;

else

count=count-1;

end

end

endmodule

TESTBENCH

module syn_tb();

reg up,clk,clr;

wire [3:0]count;

syn_ctr n1(up,clk,clr,count);

initial begin

clk=1'b0;

forever #5 clk=~clk;

end

initial begin

#0 clr=1'b1;up=1'b1;

#10 clr=1'b0;up=1'b1;

#50 clr=1'b0;up=1'b0;

#30 $finish;

end

endmodule

WAVEFORM
BUFFER

module buff(y,a);

input a;

output y;

wire w;

supply1 vdd;

supply0 gnd;

pmos p1(w,vdd,a);

nmos n1(w,gnd,a);

pmos p2(y,vdd,w);

nmos n2(y,gnd,w);

endmodule

TESTBENCH

module tb_buf();

reg a;

wire y;
buff b1(y,a);

initial begin

#0 a=1'b0;

#10 a=1'b1;

#10 a=1'b0;

#10 a=1'bx;

#10 a=1'bz;

#10 $finish;

end

endmodule

WAVEFORM

INVERTER

module inv(vout,vin);

input vin;

output vout;

supply1 vdd;

supply0 gnd;
pmos p1(vout,vdd,vin);

nmos n1(vout,gnd,vin);

endmodule

TESTBENCH

module tb_inv;

reg vin;

wire vout;

inv v1(vout,vin);

initial begin

vin=1'b0;

#10 vin=1'b1;

#10 vin=1'b0;

#10 vin=1'bx;

#10 vin=1'bz;

#10 $finish;

end

endmodule

WAVEFORM
PARALLEL

module full_adder(input a,b,cin,output sum,carry);

wire w1,w2,w3;

xor x1(w1,a,b);

xor x2(sum,w1,cin);

and x3(w2,a,b);

and x4(w3,w1,cin);

or x5(carry,w3,w2);

endmodule

module bit_4adder(a,b,cin,sum,carry);

input [3:0]a,b;

input cin;

output [3:0]sum;

output carry;

wire c1,c2,c3;

full_adder f1(a[0],b[0],cin,sum[0],c1);

full_adder f2(a[1],b[1],c1,sum[1],c2);
full_adder f3(a[2],b[2],c2,sum[2],c3);

full_adder f4(a[3],b[3],c3,sum[3],carry);

endmodule

TESTBENCH

module bit_4tb();

reg [3:0]a,b;

reg cin;

wire [3:0]sum;

wire carry;

bit_4adder b1(a,b,cin,sum,carry);

initial begin

#0 a=4'b1010;b=4'b1110;cin=0;

#10 a=4'b1010;b=4'b1101;cin=1;

#10 a=4'b1010;b=4'b1011;cin=0;

#10 a=4'b1010;b=4'b0111;cin=1;

#10 $finish;

end

endmodule

WAVEFORM
FF

SRFF

module srff(q,sr,clk,p,r);

input clk,p,r;

input [1:0]sr;

output reg [1:0]q;

initial

begin

q=2'b10;

end

always@(posedge clk,negedge p,negedge r)

begin

if(!r)

q=2'b01;

else if(!p)

q=2'b10;

else
case(sr)

2'b00:q=q;

2'b01:q=2'b01;

2'b10:q=2'b10;

2'b11:q=2'b11;

endcase

end

endmodule

TEST BENCH

module sr_tb();

reg clk,p,r;

reg [1:0]sr;

wire [1:0]q;

srff s1(q,sr,clk,p,r);

initial begin

clk=1'b0;

forever #5 clk=~clk;

end

initial begin

#0 p=1'b0;r=1'b1;sr[0]=1'bx;sr[1]=1'bx;

#10 p=1'b01;r=1'b0;sr[0]=1'bx;sr[1]=1'bx;

#10 p=1'b1;r=1'b1;sr[0]=1'b0;sr[1]=1'b1;

#10 p=1'b1;r=1'b1;sr[0]=1'b1;sr[1]=1'b0;

#10 p=1'b1;r=1'b1;sr[0]=1'b1;sr[1]=1'b1;

#10 p=1'b1;r=1'b1;sr[0]=1'b0;sr[1]=1'b0;

#10 $finish;

end

endmodule

WAVEFORM
JKFF

module jk_ff(q,j,k,clk,p,r);

input clk,p,r;

input j,k;

output reg [1:0]q;

initial

begin

q=2'b10;

end

always@(posedge clk,negedge p,negedge r)

begin

if(!r)

q=2'b01;

else if(!p)

q=2'b10;

else
case({j,k})

2'b00:begin q[0]=q[0];q[1]=q[1];end

2'b01:begin q[0]=1'b0;q[1]=1'b1;end

2'b10:begin q[0]=1'b1;q[1]=1'b0;end

2'b11:begin q[0]=(~q[0]);q[1]=(~q[1]);end

default:begin q[0]=q[0];q[1]=q[1];end

endcase

end

endmodule

TESTBENCH

module jk_tb();

reg clk,p,r;

reg j,k;

wire [1:0]q;

jk_ff s1(q,j,k,clk,p,r);

initial begin

clk=1'b0;

forever #5 clk=~clk;

end

initial begin

#0 p=1'b0;r=1'b1;j=1'bx;k=1'bx;

#10 p=1'b01;r=1'b0;j=1'bx;k=1'bx;

#10 p=1'b1;r=1'b1;j=1'b0;k=1'b0;

#10 p=1'b1;r=1'b1;j=1'b0;k=1'b1;

#10 p=1'b1;r=1'b1;j=1'b1;k=1'b0;

#10 p=1'b1;r=1'b1;j=1'b1;k=1'b1;

#10 p=1'b1;r=1'b1;j=1'b0;k=1'b0;

#10 p=1'b1;r=1'b1;j=1'b1;k=1'b1;

#10 p=1'b1;r=1'b1;j=1'b1;k=1'b1;
#10 p=1'b1;r=1'b1;j=1'b0;k=1'b0;

#10 $finish;

end

endmodule

WAVEFORM

DFF

module d_ff(q,d,clk,p,r);

input clk,p,r;

input d;

output reg [1:0]q;

initial

begin

q=2'b10;

end

always@(posedge clk,negedge p,negedge r)

begin

if(!r)
q=2'b01;

else if(!p)

q=2'b10;

else

case(d)

1'b0:q=2'b01;

1'b1:q=2'b10;

default:q=2'b01;

endcase

end

endmodule

TESTBENCH

module d_tb();

reg clk,p,r;

reg d;

wire [1:0]q;

d_ff s1(q,d,clk,p,r);

initial begin

clk=1'b0;

forever #5 clk=~clk;

end

initial begin

#0 p=1'b0;r=1'b1;d=1'bx;

#10 p=1'b01;r=1'b0;d=1'bx;

#10 p=1'b1;r=1'b1;d=1'b1;

#10 p=1'b1;r=1'b1;d=1'b0;

#10 p=1'b1;r=1'b1;d=1'b0;

#10 p=1'b1;r=1'b1;d=1'b1;

#10 $finish;
end

endmodule

WAVEFORM

TFF

module t_ff(q,t,clk,p,r);

input clk,p,r;

input t;

output reg [1:0]q;

initial

begin

q=2'b10;

end

always@(posedge clk,negedge p,negedge r)

begin

if(!r)

q=2'b01;

else if(!p)
q=2'b10;

else

case(t)

1'b0:begin q[0]=q[0];q[1]=q[1];end

1'b1:begin q[0]=(~q[0]);q[1]=(~q[1]);end

default:begin q[0]=q[0];q[1]=q[1];end

endcase

end

endmodule

TESTBENCH

module t_tb();

reg clk,p,r;

reg t;

wire [1:0]q;

t_ff s1(q,t,clk,p,r);

initial begin

clk=1'b0;

forever #5 clk=~clk;

end

initial begin

#0 p=1'b0;r=1'b1;t=1'bx;

#10 p=1'b01;r=1'b0;t=1'bx;

#10 p=1'b1;r=1'b1;t=1'b1;

#10 p=1'b1;r=1'b1;t=1'b0;

#10 p=1'b1;r=1'b1;t=1'b1;

#10 p=1'b1;r=1'b1;t=1'b0;

#10 $finish;

end

endmodule
WAVEFORM

TXN GATE

module tg(in,out,s,sbar);

input in,s,sbar;

output out;

pmos p1(out,in,sbar);

nmos n1(out,in,s);

endmodule

TESTBENCH

module tb_tg();

reg in,s,sbar;

wire out;

tg t1(in,out,s,sbar);

initial begin

#0 s=1'b1;sbar=1'b0;in=1'b0;

#10 in=1'b1;
#10 in=1'b0;

#10 s=1'b0;sbar=1'b1;

#10 in=1'b1;

#10 in=1'b0;

#10 $finish;

end

endmodule

WAVEFORM

SERIAL

module fa (a,b,cin,s,cout);

input a,b,cin;

output s,cout;

assign s=(a^b)^cin;

assign cout=((a&b)|(cin&a)|(b&cin));

endmodule

module sa2(en,clk,in1,in2,sum,carry);
input en,clk;

input [7:0]in1,in2;

output reg [7:0] sum;

output reg carry;

reg lsbin1,lsbin2,car2,sum2,car1=1'b0;

reg [3:0] count=3'b0;

reg [7:0] summer=8'b0;

always @(posedge clk)

begin

if((en)&&(count!=3'b111))

begin

lsbin1=in1[0];

lsbin2=in2[0];

in1=in1>>1;

in2=in2>>1;

fa fx(lsbin1,lsbin2,car1,sum2,car2);

summer[7]=sum2;

car1=car2;

summer=summer>>1;

count=count+1;

end

end

assign carry=car2;

assign sum=summer;

endmodule

TESTBENCH

module tb_sa();

reg clk,reset,paload,pbload,en;

reg [7:0]adata,bdata;
wire [7:0]pout;

wire scout;

sa ad1(clk,reset,paload,pbload,pout,scout,adata,bdata,en);

initial begin

clk=1'b0;

end

always

#5 clk=~clk;

initial begin

reset=1'b1;

#5 reset=1'b0;paload=1'b1;pbload=1'b1;

#5 adata=8'b10001001;bdata=8'b10001001;

#10 paload=1'b0;pbload=1'b0;en=1'b1;

#80 en=1'b0;

#10 reset=1'b1;

#10 reset=1'b0;paload=1'b1;pbload=1'b1;

#10 adata=8'b00011001;bdata=8'b10001001;

#10 paload=1'b0;pbload=1'b0;en=1'b1;

#80 en=1'b0;

#20 $finish;

end

endmodule
WAVEFORM

MASTER SLAVE JKFF

module ms_jkff (qs,qsb,qm,qmb,j,k,clk,rst);
output qs, qsb;
inout qm,qmb;
input j,k,clk,rst;
wire clkbar;
assign clkbar = ~ clk;
jkff jk1 (qm,qmb ,j,k,clk,rst);
jkff jk2 (qs,qsb,qm,qmb,clkbar,rst);
endmodule