Addressing modes:

a) Indirect addressing, unlike the direct one, makes an address with the help of IRP bit of STATUS
and FSR registers, not from an instruction. INDF holds the address indicated by a FSR and the
addressed location is accused through this register.
b) Direct addressing, represents the most simple addressing mode of the operands stored in the
memory. Every instruction which is based on direct addressing, contains as operands, the
address of the internal memory location in which the data required for executing the instruction
is memorized.
CPU

Central processing unit is the brain of a uP. That part is responsible for finding and fetching the right
instruction which needs to be executed, for decoding that instruction and for executing it.

Wregister consists of a memory space that stores the operands for each instruction. It also stores
the results of each instruction.

FSR ( File rel reg. ) acts as a pointer to any other general-purpose register. It consists of a register file
address and it is used in indirect addressing.

The instruction register is an eight bit reg. and it’s used to contain the instruction just fetched from
the memory.

ADDR MUX will either take the address of the IR or the address of a result from the FSR.

The instruction register will have direct addressing so the value will be found in the memory.

Data bus ( 8 bits ) bidirectional, on this bus flows all data from the uP and is connecting all
functioning elements.

Address bus is used for accussing the internal memory, only the PC can access it.
INTERRUPTS ( RUPT )

Interrupts are a mechanism of a uP which enables it to respond to some events at the moment
when they occur, regardless of what the uP is doing at the time. This is a very important part,
because it provides conn. Between uP and environment which surrounds it. Generally, each intr.
Changes the program flow, interrupts it and after executing an interrupt routine, it continues from
that point.
ADDRESS BUS ORIGINATES FROM ADR REGISTERS

Address registers are 16 bit registers intended for storing addrs. They may be called data counters or
pointers. They are double registers, 2x8 bit reg. Their essential characteristic is to be conn. to the
address bus, which is created by the addrs. registers. The addr. BUS appears on the left and bottom
of the illustration. In order to load the contents of these 16-bit registers, we use a data bus.

PC-> Prog. Counter

It must be present in any uP, its presence is fundamental to progr. execution. It contains the address
of the next instruction to be executed. It’s contents will be deposited on the ADR bus and
transmitted to the memory, the memory will read the contents specified by this address and send it
back to the MPU.

SP->Stack Pointer-> a dedicated register that contains the address of the top of the stack within the
memory.

Index register (IX) is a special register used to provide addressing capability called indexing. Indexing
is a facility for accessing blocks of data in the memory with a simple instruction.

ALU-> arithmetic logic unit-> a combinational digital electronic circuit that performs arithmetic and
bitwise operations on integer binary numbers. The result of the ALU will be sent to the DATA BUS.

ACCUM is a register used to store 8 bits of info, it can be read and written from it.
ONE MACHINE CYCLE

We have 2 ports: Port 2 and Port 0. Port2 will carry only addresses, namely the high part of the
address of the PC ( bits 8-15 ). Port 0 is multiplexed so it can send addresses ( when ALE is on the
falling edge -> the low port of the PC address ). It can also send instructions when PSEN is on the
rising edge.
INSTRUCTION FETCH

MPU will fetch instr. from an external memory and exec them.

MPU->uP, RAM, ROM -> MEMORY CHIP

PC holds the address of the next instr. to be exec. ( points to the next instruction in the memory that
needs to be exec ) PC => into ADDRESS BUS, one of the lines will be used to select the RAM memory,
the address will be presented to the memory through the address bus and it will select an internal
location in the memory, at this address will find a word. After it was selected the MPU will promt
the memory to read it. Data will appear on the DATA pins of the memory, which are conn to the
data bus. This bus is con to the 8 pins of the MPU bus, data coming back from the memory and the
instruction will now be gated back to the MPU. These contents will be given by the control unit to
the instruction register ( special register of the control unit ). After doing the instruction, it will fetch
another instr.

CONTROL UNIT-> INSIDE THE MPU CHIP

SERIAL TO PARALLEL CONVERS

Signal coming from left to UART (serial signal).

Clock will allow us to distinguish the entering signal.

The receiver section of the UART will rec the CLK then the signal and will give us an 8 bit parallel
output.
STANDARD SYSTEM ARHIT

Power from top, clock provides timing signals, XTAL provides precise timing ref to clock.

Right of MPU-> 3 BUSES of any micro computer system. 8 BIT DATA BUS connects to the 8 pins of
the 8 bit uP.

16 bit ADR BUS-> carries adr from uP to the devices and will help select which one to choose.

CONTROL LINES-> carries orders as: read, write,…

3 MAIN Types of components intercom.

  ON-CHIP MEMORY INTERNAL RAM

UPPER 128 RAM SPECIAL FUNC

(IND ADR) REG(DIR ADR)

(DIR AND INDIR

ADR)
Lower 128 RAM ( DIR AND INDIR ADR)
BIT
3 internal memory zones
ADDRESSABLE
32 bytes
GENERAL PURP.
REIGSTERS

The break selected with the PSW bits RS1, RS0 and then the address is specified. It permits fast
interrupts switching in the service routines.

The direct addressable bits are placed between 20H and 2FH

They are general purpose registers that can be directly accused by the uP via an instruction and
are used for fast access. These registers have a common data bus and individual “enable” pins.

SFR ( Spec func reg) are memories that belong to the peripherial modules ( timers, UART, SPi,
etc) They contain data that has to be sent, received data or binary numbers used by timers for
comparison.

R0->R7 are registers that can be direct accessed ,at a higher speed, using an instruction.
Detailed block diagram – PIC

a) ROM Prog. Memory -> Read-Only memory -> a type of non-volatile memory used in computers
and other electronic devices. Data stored in ROM can be modified with difficulty so it’s mainly
used for storing firmware.
b) Instruction register ( IR ) is the part of a CPU’s control unit that hold the instruction currently
being executed or decoded.
c) Program bus is a set of wires that transfer data between components
d) Instruction decode and control
Instruction decoder translates an instruction code into address in the micro-memory where the
micro code for the instruction starts
Instruction control tells the comp’s memory arithmetic/logic unit and input and output devices
how to respond to a programs instructions.
e) Timing generator, a circuit that produces a timing signal (clock signal) for synchronizing a
circuit’s operations
f) Program counter, contains the address pointer value of the current instruction. Each cycle the
value at the pointer is read into the instruction decoder and the PC updates to the next
instruction.
g) RAM, random access memory, stores data and machine code currently used. It’s volatile, when
the power goes off, the data stored in RAM will be lost.
h) Direct addressing mode, the value for a given instruction in assembly programmed is pointed to
by a given value.
i) Address MUX, allows us to use fewer pins on the processor and thus fewer bus lines.
j) FSR reg, File select register, used for indirect or indexed addressing of the other file registers,
particulary the general purpose register.
k) Indirect addressing, a scheme where the address specifies which memory word or register
contains the address of the operand
l) Status register, a hardware register that contains inform about the state of the uP.
m) MUX, multiplexer, selects one or several analog or digital input signals and forwards the
selected input into a single line.
n) ALU, arithm logic unit, a combinational digital electronic circuit that performs arithm and bitwise
operations on integer binary numbers.
o) W register, special register in PIC architecture used as one of the 2 operands for ALU operations,
and can also be the destination for any ALU operation.
p) Power up timer, ensures that the supply voltage is stable before the clock starts up.
q) Oscillator start-up timer, keeps the device reset until the crystal oscil. is stable.
r) Power on reset, generates a reset signal when power is applied to the device, so taht the device
starts operating in a known state.
s) Watchdog timer, a piece of hardware that can be used to automatically detect software
anomalies and resets the uP, if any occur.
8051 CPU Registers

 A – Accumulator, 8 bit register it holds the result of most arithmetic and logic
operations.
 B – B register is executing multiplication and division.
 PSW – Program Status Word, 8 bit register contains status bits that reflect the current
CPU state
 SP – Stack Pointer, 8 bit register, only bit addressable, the content of the SP points to
the last stored location of system stack.
 PC – Program counter, 2 byte address which tells the uP where the next instruction to
execute is found in memory.
 DPTR – Data pointer Register, 16 bit register, user accessible, used to points data, allows
the uP to access external memory.
 PORTS

a) Role and relation between TRISA and PORTA of a PIC.

TRISA – role: pin configuration (digital I/O port module) of the port A.

TRISX.i = 1 => pin i is input

TRISX.i = 0 => output

PORTA -> data register, if this register is used as source -> it returns the data value of the pin;
destination -> the data value will be held in the port latch. (PORTX, sets the pin’s output bit level)

Relation: both are control registers of PIC uP. Setting a TRISA bit to 1 will make the corresponding
PORTA pin an input, setting to 0, the PORTA pin will be output.
BROWN-OUT Condition

A B-OUT is a short dip in the power supply, many uP have B-OUT detection on-chip, with programmable
threshold levels. When a B-OUT occurs, the uP will reset. The uP has a minimum operating voltage,
when a glitch occurs on the power rails (Voltage drops below minimum op. V) the uP will reset to
prevent any functionality issues or major failures (wrong instr, data results)
SIMPLIFIED MPU ARHITECTURE (SINGLE BUS)

BUS -> Set of lines grouped by functions

FUNCT OF BUS -> Data transmission, address transmission, address transmission, control inform (sync
purpose)

EXTERNAL BUS -> 8 bit Bidirectional BUS interconnects all elements of the uP. (8 lines)

ALU -> airthm logic unit (V shape), a combinational digital electronic circuit that performs arithmetic and
bitwise operations on integer binary numbers. BUS connects both inputs. ALU accept 2 source operands,
resulting data goes through a shifter back on the internal bus, through a BUS. From there it can get to
any of the elements of the system.

SHIFTER -> circuit allowing to displace info either left or right by one position. It can be located at the
output of ALU or input, where are the Accumulator.

ACCUMULATOR -> register used to store 8 bits of info, can write or read from it.

ON LEFT -> registers, contain info on which the uP will operate. From 0 to N labeled.
Internal memory of the uP, used to manipulate data, more registers -> faster uP. More registers ->
longer the instructions. Registers should be abundant but limited, to have a better addressing speed.

Special registers: IX, SP, PC

PC -> contains the address of the next instruction to be executed, it has 2 parts, Low (0-7) and High
(8-15)

SP -> Stack pointer, used to provide a stack capability, will keep a pointer on top of the stack.

IX -> index, special register used to provide addressing capability called indexing.

ADDRESS BUS -> BUS coming out of these 3, special registers 16 bit, it will carry out in the external world
the address of the devices which are being selected for data transmission.

FLAGS, are special indicators => Z- zero/not zero | C – carry (if 8 bits are exceeded from summing) | N –
negative (if 1 – negative if 0 – positive) | O – overflow ( if magnitude changes sign) | H – half carry (in
BCD) | P – Parity |

CONTROL UNIT – synchronizes everything, decoding instructions, finding out what to do and doing it, it
will open gates, it will send orders to the elements of the system.