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DESCRIPTION FEATURES
The MP2305 is a monolithic synchronous buck • 2A Output Current
regulator. The device integrates 130mΩ • Wide 4.75V to 23V Operating Input Range
MOSFETS that provide 2A continuous load • Integrated 130mΩ Power MOSFET Switches
current over a wide operating input voltage of • Output Adjustable from 0.923V to 20V
4.75V to 23V. Current mode control provides • Up to 93% Efficiency
fast transient response and cycle-by-cycle • Programmable Soft-Start
current limit. • Stable with Low ESR Ceramic Output Capacitors
An adjustable soft-start prevents inrush current • Fixed 340kHz Frequency
at turn-on. Shutdown mode drops the supply • Cycle-by-Cycle Over Current Protection
current to 1μA. • Input Under Voltage Lockout
This device, available in an 8-pin SOIC APPLICATIONS
package, provides a very compact system
solution with minimal reliance on external • Distributed Power Systems
components. • Networking Systems
• FPGA, DSP, ASIC Power Supplies
EVALUATION BOARD REFERENCE • Green Electronics/ Appliances
Board Number Dimensions • Notebook Computers
EV2305DS-00A 2.0”X x 1.5”Y x 0.5”Z All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
C5 Efficiency vs
10nF
Load Current
100
95 VOUT = 3.3V
2 1 90
EFFICIENCY (%)
7
IN BS
3
85 VOUT = 2.5V
EN SW
80
MP2305
8 5 75
SS FB
GND COMP 70
4 6 65
60
55
50
0 0.5 1.0 1.5 2.0 2.5
LOAD CURRENT (A)
MP2305-EC01
ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature (TA)
MP2305DS SOIC8 MP2305DS -40°C to +85°C
PACKAGE REFERENCE
TOP VIEW
BS 1 8 SS
IN 2 7 EN
SW 3 6 COMP
GND 4 5 FB
MP2305_PD01
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Shutdown Supply Current VEN = 0V 1 3.0 μA
Supply Current VEN = 2.0V; VFB = 1.0V 1.3 1.5 mA
Feedback Voltage VFB 4.75V ≤ VIN ≤ 23V 0.900 0.923 0.946 V
Feedback Overvoltage Threshold 1.1 V
Error Amplifier Voltage Gain (5) AEA 400 V/V
Error Amplifier Transconductance GEA ΔIC = ±10μA 800 μA/V
(5)
High-Side Switch On Resistance RDS(ON)1 130 mΩ
Low-Side Switch On Resistance (5) RDS(ON)2 130 mΩ
High-Side Switch Leakage Current VEN = 0V, VSW = 0V 10 μA
Upper Switch Current Limit Minimum Duty Cycle 2.4 3.4 5.3 A
Lower Switch Current Limit From Drain to Source 1.1 A
COMP to Current Sense
GCS 3.5 A/V
Transconductance
Oscillation Frequency Fosc1 340 kHz
Short Circuit Oscillation Frequency Fosc2 VFB = 0V 100 kHz
Maximum Duty Cycle DMAX VFB = 1.0V 90 %
Minimum On Time (5) 220 ns
EN Shutdown Threshold Voltage VEN Rising 1.1 1.5 2.0 V
EN Shutdown Threshold Voltage
210 mV
Hysteresis
EN Lockout Threshold Voltage 2.2 2.5 2.7 V
EN Lockout Hysterisis 210 mV
Input Under Voltage Lockout
VIN Rising 3.80 4.10 4.40 V
Threshold
Input Under Voltage Lockout
210 mV
Threshold Hysteresis
Soft-Start Current VSS = 0V 6 μA
Soft-Start Period CSS = 0.1μF 15 ms
Thermal Shutdown (5) 160 °C
Note:
5) Guaranteed by design, not tested.
PIN FUNCTIONS
Pin # Name Description
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET
1 BS
switch. Connect a 0.01μF or greater capacitor from SW to BS to power the high side switch.
Power Input. IN supplies the power to the IC, as well as the step-down converter switches.
2 IN Drive IN with a 4.75V to 23V power source. Bypass IN to GND with a suitably large capacitor
to eliminate noise on the input to the IC. See Input Capacitor.
Power Switching Output. SW is the switching node that supplies power to the output. Connect
3 SW the output LC filter from SW to the output load. Note that a capacitor is required from SW to
BS to power the high-side switch.
4 GND Ground.
Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a
5 FB resistive voltage divider from the output voltage. The feedback threshold is 0.923V. See
Setting the Output Voltage.
Compensation Node. COMP is used to compensate the regulation control loop. Connect a
series RC network from COMP to GND to compensate the regulation control loop. In some
6 COMP
cases, an additional capacitor from COMP to GND is required. See Compensation
Components.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on
7 EN
the regulator, drive it low to turn it off. Pull up with 100kΩ resistor for automatic startup.
Soft-Start Control Input. SS controls the soft start period. Connect a capacitor from SS to GND
8 SS to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 15ms. To disable the
soft-start feature, leave SS unconnected.
VIN
20mV/div. VEN VEN
5V/div. 5V/div.
VOUT
20mV/div. VOUT VOUT
1V/div. 2V/div.
IL
1A/div. IL IL
1A/div. 1A/div.
VSW
VSW
10V/div. VSW
10V/div.
10V/div.
VO, AC VO, AC
VO, AC
20mV/div. 20mV/div.
20mV/div.
IL IL
IL
1A/div. 1A/div.
1A/div.
VOUT
VOUT VOUT
2V/div.
2V/div. 200mV/div.
IL
IL 1A/div.
2A/div. IL
2A/div. ILOAD
1A/div.
OPERATION
FUNCTIONAL DESCRIPTION The converter uses internal N-Channel
The MP2305 is a synchronous rectified, MOSFET switches to step-down the input
current-mode, step-down regulator. It regulates voltage to the regulated output voltage. Since
input voltages from 4.75V to 23V down to an the high side MOSFET requires a gate voltage
output voltage as low as 0.923V, and supplies greater than the input voltage, a boost capacitor
up to 2A of load current. connected between SW and BS is needed to
drive the high side gate. The boost capacitor is
The MP2305 uses current-mode control to charged from the internal 5V rail when SW is
regulate the output voltage. The output voltage low.
is measured at FB through a resistive voltage
divider and amplified through the internal When the MP2305 FB pin exceeds 20% of the
transconductance error amplifier. The voltage at nominal regulation voltage of 0.923V, the over
the COMP pin is compared to the switch current voltage comparator is tripped and the COMP
measured internally to control the output pin and the SS pin are discharged to GND,
voltage. forcing the high-side switch off.
+
CURRENT IN
OVP SENSE
-- AMPLIFIER +
1.1V
RAMP 5V
OSCILLATOR
FB + --
CLK
340KHz
BS
0.3V --
+ S Q
-- R Q SW
SS + -- CURRENT
ERROR COMPARATOR
0.923V + AMPLIFIER
COMP
-- GND
EN
EN OK 1.2V OVP
IN < 4.1V
LOCKOUT
2.5V + COMPARATOR
7V
Zener IN
+
INTERNAL
REGULATORS
1.5V -- SHUTDOWN
COMPARATOR
APPLICATIONS INFORMATION
COMPONENT SELECTION Choose an inductor that will not saturate under
Setting the Output Voltage the maximum inductor peak current. The peak
The output voltage is set using a resistive inductor current can be calculated by:
voltage divider from the output voltage to FB pin. VOUT ⎛ V ⎞
The voltage divider divides the output voltage ILP = ILOAD + × ⎜⎜1 − OUT ⎟⎟
2 × fS × L ⎝ VIN ⎠
down to the feedback voltage by the ratio:
R2 Where ILOAD is the load current.
VFB = VOUT
R1 + R2 The choice of which style inductor to use mainly
Where VFB is the feedback voltage and VOUT is depends on the price vs. size requirements and
the output voltage. any EMI requirements.
The worst-case condition occurs at VIN = 2VOUT, MP2305 can be optimized for a wide range of
where IC1 = ILOAD/2. For simplification, choose capacitance and ESR values.
the input capacitor whose RMS current rating
Compensation Components
greater than half of the maximum load current.
MP2305 employs current mode control for easy
The input capacitor can be electrolytic, tantalum compensation and fast transient response. The
or ceramic. When using electrolytic or tantalum system stability and transient response are
capacitors, a small, high quality ceramic controlled through the COMP pin. COMP pin is
capacitor, i.e. 0.1μF, should be placed as close the output of the internal transconductance
to the IC as possible. When using ceramic error amplifier. A series capacitor-resistor
capacitors, make sure that they have enough combination sets a pole-zero combination to
capacitance to provide sufficient charge to control the characteristics of the control system.
prevent excessive voltage ripple at input. The
The DC gain of the voltage feedback loop is
input voltage ripple for low ESR capacitors can
given by:
be estimated by:
VFB
I V ⎛ V ⎞ A VDC = R LOAD × G CS × A EA ×
ΔVIN = LOAD × OUT × ⎜⎜1 − OUT ⎟⎟ VOUT
C1 × fS VIN ⎝ VIN ⎠
Where AVEA is the error amplifier voltage gain;
Where C1 is the input capacitance value. GCS is the current sense transconductance and
Output Capacitor RLOAD is the load resistor value.
The output capacitor is required to maintain the The system has two poles of importance. One
DC output voltage. Ceramic, tantalum, or low is due to the compensation capacitor (C3) and
ESR electrolytic capacitors are recommended. the output resistor of the error amplifier, and the
Low ESR capacitors are preferred to keep the other is due to the output capacitor and the load
output voltage ripple low. The output voltage resistor. These poles are located at:
ripple can be estimated by:
GEA
V ⎛ V ⎞ ⎛ 1 ⎞ fP1 =
ΔVOUT = OUT × ⎜⎜1 − OUT ⎟⎟ × ⎜ R ESR + ⎟ 2π × C3 × A VEA
fS × L ⎝ VIN ⎜ 8 × f S × C2 ⎟⎠
⎠ ⎝
1
Where C2 is the output capacitance value and fP2 =
2π × C2 × R LOAD
RESR is the equivalent series resistance (ESR)
value of the output capacitor. Where GEA is the error amplifier transconductance.
In the case of ceramic capacitors, the The system has one zero of importance, due to the
impedance at the switching frequency is compensation capacitor (C3) and the compensation
dominated by the capacitance. The output resistor (R3). This zero is located at:
voltage ripple is mainly caused by the
1
capacitance. For simplification, the output f Z1 =
2π × C3 × R3
voltage ripple can be estimated by:
The system may have another zero of
VOUT ⎛ V ⎞
ΔVOUT = × ⎜⎜1 − OUT ⎟⎟ importance, if the output capacitor has a large
2 VIN
8 × fS × L × C2 ⎝ ⎠ capacitance and/or a high ESR value. The zero,
due to the ESR and capacitance of the output
In the case of tantalum or electrolytic capacitors, capacitor, is located at:
the ESR dominates the impedance at the
switching frequency. For simplification, the 1
fESR =
output ripple can be approximated to: 2π × C2 × R ESR
VOUT ⎛ V ⎞
ΔVOUT = × ⎜1 − OUT ⎟⎟ × R ESR
f S × L ⎜⎝ VIN ⎠
In this case (as shown in Figure 2), a third pole 3. Determine if the second compensation
set by the compensation capacitor (C6) and the capacitor (C6) is required. It is required if the
compensation resistor (R3) is used to ESR zero of the output capacitor is located at
compensate the effect of the ESR zero on the less than half of the switching frequency, or the
loop gain. This pole is located at: following relationship is valid:
1 1 f
fP 3 = < S
2π × C6 × R3 2π × C2 × R ESR 2
The goal of compensation design is to shape If this is the case, then add the second
the converter transfer function to get a desired compensation capacitor (C6) to set the pole fP3
loop gain. The system crossover frequency at the location of the ESR zero. Determine the
where the feedback loop has the unity gain is C6 value by the equation:
important. Lower crossover frequencies result
in slower line and load transient responses, C2 × R ESR
C6 =
while higher crossover frequencies could cause R3
system instability. A good rule of thumb is to set External Bootstrap Diode
the crossover frequency below one-tenth of the An external bootstrap diode may enhance the
switching frequency. efficiency of the regulator, and it will be a must
To optimize the compensation components, the if the applicable condition is:
following procedure can be used. z VOUT=5V or 3.3V; and duty cycle is high:
1. Choose the compensation resistor (R3) to set VOUT
D= >65%
the desired crossover frequency. VIN
Determine the R3 value by the following In these cases, an external BST diode is
equation: recommended from the output of the voltage
regulator to BST pin, as shown in Figure 2
2π × C2 × fC VOUT 2π × C2 × 0.1 × fS VOUT
R3 = × < ×
GEA × GCS VFB GEA × GCS VFB External BST Diode
IN4148
Where fC is the desired crossover frequency BST
which is typically below one tenth of the CBST
MP2305
switching frequency.
SW 5V or 3.3V
L +
2. Choose the compensation capacitor (C3) to COUT
achieve the desired phase margin. For
applications with typical inductor values, setting Figure 2—Add Optional External Bootstrap
the compensation zero, fZ1, below one-forth of Diode to Enhance Efficiency
the crossover frequency provides sufficient
phase margin. The recommended external BST diode is
Determine the C3 value by the following equation: IN4148, and the BST cap is 0.1~1µF.
4
C3 >
2π × R3 × f C
INPUT
4.75V to 23V
2 1
IN BS
7 3
EN SW
MP2305
8 5
SS FB
GND COMP
4 6
PACKAGE INFORMATION
SOIC8
0.189(4.80)
0.024(0.61) 0.050(1.27)
0.197(5.00)
8 5
0.063(1.60)
0.150(3.80) 0.228(5.80)
0.213(5.40)
PIN 1 ID 0.157(4.00) 0.244(6.20)
1 4
0.053(1.35)
0.069(1.75)
0.0075(0.19)
SEATING PLANE
0.0098(0.25)
0.004(0.10)
0.013(0.33) 0.010(0.25)
0.020(0.51) SEE DETAIL "A"
0.050(1.27)
BSC
0.010(0.25)
x 45o NOTE:
0.020(0.50)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.