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`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:13 09/05/2018
// Design Name:
// Module Name: modulate
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module modulate(
input clk,
input ce,
input rst,
input [7:0] data,
input sample,
output reg [7:0] d_out_re,
output reg [7:0] d_out_im,
output reg [4:0] address,
output start
);

wire [5:0] cnt;


reg [6:0] counter;
wire [6:0] address_5;
wire [6:0] counter_t;
reg counter_rst;
reg cnt_nw;
reg cnt_pre;

assign counter_t=counter-1'b1;
assign cnt= (counter>7'b0)?counter_t[5:0]:6'b0;
assign start=(counter==7'd4);
assign address_5=7'd63-cnt;

// always @(posedge sample or posedge rst)


// begin
// if(rst)
// counter_rst=1'b0;
// else
// counter_rst=1'b1;
// end

always @ (posedge clk or posedge rst)


if (rst)
begin
counter=7'b0;
d_out_re=8'b0;
d_out_im=8'b0;
counter_rst=1'b0;
cnt_nw=1'b0;
cnt_pre=1'b0;
end
else if(ce)
begin
cnt_nw=(sample)?1'b1:1'b0;
counter_rst=(cnt_nw>cnt_pre); //edit
cnt_pre=cnt_nw;

if(counter<7'd67)//7'd64
begin
counter=counter+1'b1;
if (cnt<7'd32)
address=cnt[4:0];
else if (cnt<7'd64)
address=address_5[4:0];

// case (data)
// 8'd0 :
// begin
// d_out_re=-8'd1;
// d_out_im=(cnt<7'd32)?8'd1:-8'd1;
// end
// 8'd1 :
// begin
// d_out_re=-8'd1;
// d_out_im=(cnt<7'd32)?-8'd1:8'd1;
// end
// 8'd2 :
// begin
// d_out_re=8'd1;
// d_out_im=(cnt<7'd32)?8'd1:-8'd1;
// end
// 8'd3 :
// begin
// d_out_re=8'd1;
// d_out_im=(cnt<7'd32)?-8'd1:8'd1;
// end
// default :
// begin
// d_out_re=8'd0;
// d_out_im=(cnt<7'd32)?8'd0:8'd0;
// end
// endcase
d_out_re=data; //temp
d_out_im=data; //temp

end
else if(counter_rst)
begin
counter=1'b0;
end
end

endmodule

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