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VLSI Lab
06ECL77
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LABORATORY CERTIFICATE
Date …………..
Signature of the Teacher In charge of the batch
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INDEX
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for GUI the first two commands remain the same but from third
#ncelab inv_test –access +rwc
#ncsim inv_test -gui
6. The 5th step can also be done using the single step with GUI
#irun inverter.v inverter_test.v –access +rwc -gui
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Synthesize procedure
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Block Diagram
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Output Waveform
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2. BASIC GATES
RTL Code
AND Gate
module and_gate(a,b,c);
input a,b;
output c;
assign c = a & b;
endmodule
Block Diagram
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Output Waveform
RTL Code
OR Gate
module or_gate(a,b,c);
input a,b;
output c;
assign c = a | b;
endmodule
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Block Diagram
Output Waveform
RTL Code
XOR Gate
module xor_gate(a,b,c);
input a,b;
output c;
assign c = a ^ b;
endmodule
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a = 0; b = 0; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
a = 1; b = 1; #100;
$display(“a=%d |”,a,”b=%d |”,b,”c=%d”,c);
end
endmodule
Block Diagram
Output Waveform
RTL Code
XNOR Gate
module xnor_gate(a,b,c);
input a,b;
output c;
assign c = ~ (a ^ b;)
endmodule
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Block Diagram
Output Waveform
RTL Code
NOR Gate
module nor_gate(a,b,c);
input a,b;
output c;
assign c = ~ (a | b;)
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endmodule
Block Diagram
Output Waveform
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RTL Code
NAND Gate
module nand_gate(a,b,c);
input a,b;
output c;
assign c = ~ (a & b;)
endmodule
Block Diagram
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Output Waveform
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3. BUFFER
RTL Code
module buffer_1(a, b);
input a;
output b;
not(ta,a);
not(b,ta);
endmodule
Block Diagram
Output Waveform
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4. JK Flip Flop
RTL Code
module jk_ff(j, k, clk, q, qb);
input j,k,clk;
output reg q,qb;
reg kk = 1’b0;
reg [1:0] t;
always@(posedge(clk))
begin
t={j,k};
case(t)
2'b00 : kk = kk;
2'b01 :kk = 1’b0;
2'b10 : kk = 1’b1;
2'b11 :kk = ~kk;
default: ;
endcase
q = kk; qb = ~q;
end
endmodule
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Block Diagram
Output Waveform
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5. SR Flip flop
RTL Code
module sr_ff(s,r, q,qb);
input s,r;
output reg q,qb;
reg st = 1'b0;
reg [1:0] k;
always@(s,r)
begin
k = {s,r};
case(k)
2'b00 : st = st;
2'b01 : st = 1'b0;
2'b10 : st = 1'b1;
2'b11 : st = 1'bz;
default: ;
endcase
q = st;
qb = ~q;
end
endmodule
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Block Diagram
Output Waveform
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6. D Flip flop
RTL Code
module d_ff(d,clk, q,qb);
input d,clk;
output reg q,qb;
always@(posedge(clk))
begin
q = d;
qb = ~d;
end
Block Diagram
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Output Waveform
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7. T Flip flop
RTL Code
module t_ff(t,clk, q,qb);
input t,clk;
output q,qb;
jk_ff u1(t,t,clk,q,qb);
endmodule
(note: write the jk_ff code JK Flip flop in a separate file and save it )
JK Flip flop Code
module jk_ff(j, k, clk, q, qb);
input j,k,clk;
output reg q,qb;
reg kk = 1’b0;
reg [1:0] t;
always@(posedge(clk))
begin
t={j,k};
case(t)
2'b00 : kk = kk;
2'b01 :kk = 1’b0;
2'b10 : kk = 1’b1;
2'b11 :kk = ~kk;
default: ;
endcase
q = kk;
qb = ~q;
end
endmodule
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begin
t = 0; #10;
t = 1; #10;
t = 0; #10;
t = 1; #10;
end
endmodule
Block Diagram
Output Waveform
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8. MS Flip flop
RTL Code
module ms_ff(j,k,clk, q,qb);
input j,k,clk;
output q,qb;
jk_ff u1(j,k,clk,qm,qmb);
jk_ff u2(qm,qmb,~clk,q,qb);
endmodule
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begin
j = 1; k = 0; #10;
j = 0; k = 1; #10;
j = 1; k = 0; #10;
j = 0; k = 1; #10;
j = 1; k = 1; #10;
end
endmodule
Block Diagram
Output Waveform
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end
endmodule
Block Diagram
Output Waveform
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#33;
rst = 1;
end
endmodule
Block Diagram
Output Waveform
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reg load;
wire [8:0] sum;
serial_adder my_adder(a,b,clk,load,sum);
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
load = 0;
a = 8’d100;
b = 8’d25;
#10;
load = 1;
#10;
load = 0;
#80 ;
$display("a=%d",a," b=%d", b, " sum = %d",sum);
end
endmodule
Block Diagram
Output Waveform
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Block Diagram
Output Waveform
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0 1
1 0
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Test Circuit
Layout
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Transient analysis
DC Analysis
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Schematic
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Test Circuit
Layout
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Transient analysis
DC Analysis
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AC Analysis- Frequency
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Schematic
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Test Circuit
Layout
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Transient analysis
DC Analysis
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AC Analysis
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VLSI Questions
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Because we can't get full voltage swing with only NMOS or PMOS .We have to use both of them
together for that purpose.
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for pass transistor,
both voltage levels need to be passed and hence both nmos and pmos need to be used.
What are set up time & hold time constraints? What do they signify?
Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the
signal changes state during this interval, the output of that flip-flop cannot be predictable (called
metastable).
Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If the
signal changes during this interval, the output of that flip-flop cannot be predictable (called
metastable).
clock skew is the time difference between the arrival of active clock edge to different flip-flops’
of the same chip.
Why is not NAND gate preferred over NOR gate for fabrication?
NAND is a better gate for design than NOR because at the transistor level the mobility of
electrons is normally three times that of holes compared to NOR and thus the NAND is a
faster gate. Additionally, the gate-leakage in NAND structures is much lower.
In CMOS technology, in digital design, why do we design the size of pmos to be higher than
the nmos. What determines the size of pmos wrt nmos. Though this is a simple question try
to list all the reasons possible?
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In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the
carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos
helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd. If
the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the
output node. If we have a larger PMOS than there will be more carriers to charge the node
quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise
and fall times for the output node.
What happens when the PMOS and NMOS are interchanged with one
another in an inverter?
If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1
O/P will be degraded 1 Similarly degraded 0
Why are pMOS transistor networks generally used to produce high signals, while nMOS
networks are used to product low signals?
This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS
can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in
pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing.
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid
Latch Up?
A latch up is the inadvertent creation of a low-impedance path between the power supply rails of
an electronic component, triggering a parasitic structure(The parasitic structure is usually
equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning
of the part. Depending on the circuits involved, the amount of current flow produced by this
mechanism can be large enough to result in permanent destruction of the device due to electrical
over stress - EOS
What is slack?
The slack is the time delay difference from the expected delay(1/clock) to the actual
delay in a particular path. Slack may be +ve or -ve.
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Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study of ckt's
operation independent of timing parameters and gate delays. b) Timing Simulation :study including
estimated delays, verify setup, hold and other timing requirements of devices like flip flops are met.
Synthesis: One of the foremost in back end steps where by synthesizing is nothing but converting VHDL
or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit
into the target technology. Basically the synthesis tools convert the design description into equations or
components.
FPGA vs ASIC
Definitions
Speed
ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific application they can
be optimized to maximum, hence we can have high speed in ASIC designs. ASIC can have high
speed clocks.
Cost
FPGAs are cost effective for small applications. But when it comes to complex and large volume
designs (like 32-bit processors) ASIC products are cheaper.
Size/Area
FPGA are contains lots of LUTs, and routing channels which are connected via bit
streams(program). As they are made for general purpose and because of re-usability. They are in-
general larger designs than corresponding ASIC design. For example, LUT gives you both
registered and non-register output, but if we require only non-registered output, then it’s a waste
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Power
FPGA designs consume more power than ASIC designs. As explained above the unwanted
circuitry results wastage of power. FPGA won’t allow us to have better power optimization.
When it comes to ASIC designs we can optimize them to the fullest.
Time to Market
FPGA designs will still take less time, as the design cycle is small when compared to that of
ASIC designs. No need of layouts, masks or other back-end processes. It’s very simple:
Specifications -- HDL + simulations -- Synthesis -- Place and Route (along with static-analysis) --
Dump code onto FPGA and Verify. When it comes to ASIC we have to do floor planning and
also advanced verification. The FPGA design flow eliminates the complex and time-consuming
floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the
design logic is already synthesized to be placed onto an already verified, characterized FPGA
device.
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Type of Design
ASIC can have mixed-signal designs, or only analog designs. But it is not possible to design
those using FPGA chips.
Customization
ASIC has the upper hand when comes to the customization. The device can be fully customized
as ASICs will be designed according to a given specification. Just imagine implementing a 32-bit
processor on a FPGA!
Prototyping
Because of re-usability of FPGAs, they are used as ASIC prototypes. ASIC design HDL code is
first dumped onto a FPGA and tested for accurate results. Once the design is error free then it is
taken for further steps. It’s clear that FPGA may be needed for designing an ASIC.
NRE refers to the one-time cost of researching, designing, and testing a new product, which is
generally associated with ASICs. No such thing is associated with FPGA. Hence FPGA designs
are cost effective.
Due to software that handles much of the routing, placement, and timing, FPGA designs have
smaller designed cycle than ASICs.
Due to elimination of potential re-spins, wafer capacities, etc. FPGA designs have better project
cycle.
Tools
Tools which are used for FPGA designs are relatively cheaper than ASIC designs.
Re-Usability
A single FPGA can be used for various applications, by simply reprogramming it (dumping new
HDL code). By definition ASIC are application specific cannot be reused.
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