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Subject: 15A04802 LOW POWER VLSI CIRCUITS AND SYSTEMS

Class: IV ECE- Sem II

Part A Questions

Unit I

1. Define Sub threshold swing ( April 2019)

2. Define channel length modulation ( April 2019)
3. List the limits of low power design ( July 2019)
4. Write the expression for body effect coefficient ( July 2019)

Unit II

5. What is meant by fringing field capacitance ?( April 2019)

6. What are the disadvantages of resistive load inverter ?( April 2019)
7. Define noise margin of an inverter. ( July 2019)
8. What are the advantages of dynamic logic circuits? ( July 2019)

Unit III

9. What are the drawbacks of parallelism approach ?( April 2019)

10. What is the effect of feature scaling on power dissipation?( April 2019)
11. What is meant by drain induced barrier lowering? ( July 2019)
12. Explain pipelining approach ( July 2019)

Unit IV

13. List out the methods to minimize the switched capacitance( April 2019)
14. What is meant by molecule in transmeta Crusoe Processor? ( April 2019)
15. What is basic assumption of state assignment algorithm ?( July 2019)
16. What are the techniques used to reduce power at the logic level? ( July 2019)

Unit V

17. Draw the AND gate using adiabatic logic ( April 2019)
18. How multiple threshold voltages can be achieved in a circuit? ( April 2019)

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19. List out the approaches to minimizing leakage power. ( July 2019)
20. What are the advantages of dual threshold voltage assignment approach? ( July 2019)

Part B

Unit I

1. Explain the principles and challenges in low power design ( April 2019)
2. List the different sources of dynamic and static power dissipation ( April 2019)
3. Explain the structure and operation of NMOS Transistor and device expression for drain
current ( April 2019)
4. What is the need for low power chip?. Explain the various dynamic and static power
dissipation ( July 2019)
5. Explain the sub threshold swing( July 2019)
6. Explain the effects of short channel length ( July 2019)

Unit II

1. Explain the operation of depletion load nMOS inverter and draw the VTC ( April 2019)
2. Discuss in details about the CMOS transmission gates ( April 2019)
3. Discuss the delay parameters of MOS transistor ( April 2019)
4. Explain the operation of CMOS inverter with neat sketches ( July 2019)
5. Explain about Elmore delay ( July 2019)
6. Design EXOR gate using pass transistor logic ( July 2019)

Unit III

1. Derive the expression for short circuit power dissipation of CMOS inverter ( April 2019)
2. Explain in detail about switching power dissipation( April 2019)
3. Explain the optimization procedures for low power dissipation at algorithm and architecture
level. ( April 2019)
4. Explain the Monte Carlo method for estimating glitch power ( July 2019)
5. What are the factors influencing the leakage current in deep sub micron transistor? ( July
2019)
6. List out he advantages of voltage scaling ( July 2019)
7. Explain the charge sharing phenomena in dynamic circuits ( July 2019)

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Unit IV

1. Explain any three techniques that are used to reduce the power at the logic level ( April 2019)
2. Using Shannon’s expansion principle, explain the pre computation of adder comparator
circuit ( April 2019)
3. Explain the power optimization using operation reduction techniques ( July 2019)
4. Explain the FSM and combinational logic synthesis with suitable state machine representation
( July 2019)

Unit V

1. Explain variable threshold CMOS inverter circuit with a neat sketch ( April 2019)
2. What are the advantages and disadvantages of MTCMOS circuits? ( April 2019)
3. Explain the techniques used to minimize the software contribution to power minimization(
April 2019)
4. Design a full adder using adiabatic logic ( July 2019)
5. Compare and contrast MTCMOS and DTCMOS circuits( July 2019)
6. Explain the techniques used to minimize the software contribution to power dissipation ( July
2019)

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