Microprocessor

❖ “Microprocessor” is a
➢Clock driven ➢Register based

➢Multipurpose ➢Programmable
•Electronic semiconductor device.

•It accepts data from user through storage memory;

processes the data as per the given instruction and gives
the desired output.
 8085 Microprocessor
❖Features :
It is a 8-bit processor. Supply required is of 5 volts
 On chip clock generator, so external clock is not required
 Operating frequency is max.3MHz and min. is 250KHz.
 74 instructions.  16 address lines
 (216 =64K) bytes of memory can be accessed.
 There is 8-bit port address so it can address(28=256)I/O ports.
 It can perform Arithmetic and logical operations.
 Five hardware interrupts available.
 It has six general purpose and three special purpose Registers.
 It provides two serial I/O lines for serial communication (SOD
& SID)
 8086 Microprocessor
❖ Features
➢ It is a 16 – bit processor
➢ data line is 16 – bit
➢ Address line is 20 – bit
accessing 1MB memory locations
➢ Fourteen 16 – bit registers
➢ Arithmetic operation like
multiply/divide are also possible
➢ It follows pipeline design
➢ Concept of Segmentation
➢ Dual mode of operation
(min/max)
➢ Operating frequency is
5MHz/8MHz/10MHz
➢ It can support up to 64K I/O
ports
 Architecture of 8086
❖ It is divided in two groups
➢ Bus Interface Unit : It performs all bus operations and
communicates with external world. Main blocks are
• Instruction Queue
• Segment Register
• Instruction Pointer
➢ Execution Unit : It executes the instructions made available
from Queue. Main blocks
• Register Group
• Flag Register
• ALU
• Control Circuitry
 Bus Interface Unit
Execution Unit

BHE/S7
A16/S3 – A19/S6
AD0 – AD15
INTA
DT/R
DEN
ALE

RQ/GT0 - RQ/GT1

TEST LOCK
INTR
NMI M/IO
HOLD QS0,QS1
HLDA S2, S1, S0

VCC
CLK
RESET READY MN/MX 2 - Gnd RD WR
PIN Description
8086 is a 40 pin DIP
using MOS technology.
It has 2 GND’s as circuit
complexity demands a
large amount of current
0 1
flowing through the
circuits, and multiple
grounds help in
dissipating the
accumulated heat etc.
8086 works on two
modes of operation
namely, Maximum
Mode and Minimum
Mode.
 Power Connections
❖ Pin Description:
GND 1 40 VCC
➢ GND – Pin no. 1, 20
• Ground
➢ CLK – Pin no. 19 – Type I 8086
• Clock: provides the
CLK 19
basic timing for the
processor and bus GND 20
controller. It is
asymmetric with a 33%
duty cycle to provide
optimized internal
timing.
➢ VCC – Pin no. 40
• VCC: +5V power
supply pin
 Address/ Data Lines
AD14 2
39 AD15
AD13 3
AD12 4
AD11 5
AD10 6
AD9 7
AD8 8 8086
AD7 9
AD6 10
AD5 11
AD4 12
AD3 13
AD2 14
AD1 15
AD0 16
 Address Lines
A14 2 39 A15
A13 3
A12 4
38 A 16
A11 5
A10 6
37 A 17
A9 7
A8 8 8086
A7 9 36 A 18
A6 10
A5 11 35 A 19
A4 12
A3 13
A2 14
A1 15
A0 16
 Segments
Segment Starting address is
segment register value MEMORY Address
shifted 4 place to the left. 000000H

CODE

64K Data
Segment
STACK

DATA

EXTRA  CS:0
64K Code
Segment
Segment
Registers

Segments are < or = 64K,

can overlap, start at an address 0FFFFFH
that ends in 0H.
 Segmented Memory
Within the 1 MB of memory, the
8086 defines 4 64KB memory
blocks.

DS: E000 CS: B300

SS: 7000 ES: 5D27
7FFFF

The segment registers point to

location 0 of each segment. (The
base address)

1/2002 JNM 14
 Physical Address generation
000000H

4000H
CS: 0400H

4056H
IP 0056H CS:IP = 400:56
Logical Address
Left-shift 4 bits
Memory
0400 0
Segment Register

Offset + 0056
0FFFFFH
Physical or 04056H
Absolute Address
➢ The offset is the distance in bytes from the start of the segment.
➢ The offset is given by the IP - Code Segment. SP - Stack Segment, EA – Data/Extra Seg.
➢ Instructions are always fetched with using the CS register.
➢ The physical address is also called the absolute address
 S4 S3 Address status
0 0 Alternate(relative to ES segment)

0 1 Stack (relative to SS Segment)

1 0 Code/None (relative to CS segment or a

default zero)
1 1 Data (relative to DS segment)

➢ This information indicates which relocation register

is presently being used for data accessing.
➢ These lines float to 3-state OFF during local bus
“hold acknowledge”.
Status Pins S0-S7

38 S3
37 S4
36 S5

35 S6

34 S7
8086
28 S2 (M/I O )

27 S1 (DT / R )

S 0 ( DEN)
26
❖ These signals float to 3-state OFF in “hold
acknowledge”. These status lines are encoded as
shown.
Characteristics
0(LOW) 0 0 Interrupt acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1(HIGH) 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
S5 ----- Value of Interrupt Enable flag

S6 ----- Always low (logical) indicating 8086 is

on the bus. If it is tristated another bus
master has taken control of the system bus.

S7 ----- Used by 8087 numeric coprocessor to

determine whether the CPU is a 8086 or
8088
 Interrupts
❖NMI – Pin no. 17

8086
NMI 17

INTR 18

INTR – Pin No. 18

 Mode signals
❖MN/MX* - Pin no. 33 – Type - I
➢Minimum / Maximum: indicates what mode
the processor is to operate in.
➢ If this pin is connected to Vcc i.e. +5 volts
then 8086 processor will operate in minimum
mode.
➢ If pin is grounded then 8086 processor will
operate in maximum mode.
Min mode signals

33 VCC MN/ MX

31 HOLD

30 HLDA
29 WR
28 M/I O
8086
27 DT/ R

26 DEN

25 ALE

24 INTA
Max mode signals

33 GND
31 RQ/ GT0

30 RQ/ GT1

29 LOCK
28 S2
8086
27 S1

26 S0

25 QS0

24 QS1
QS1 QS0 Characteristics

0(LOW) 0 No operation

0 1 First Byte of Op Code from Queue

1 (HIGH) 0 Queue is empty

1 1 Subsequent byte from Queue

Common Signals
 Status after Reset
CPU component Contents

Flags Cleared
Instruction Pointer 0000H
CS FFFFH
DS, SS and ES 0000H
Queue Empty
❖ BHE/S7- Pin No. 34 – Type O
➢ Bus High Enable / Status: During T1 the Bus High Enable signal
(BHE*) should be used to enable data onto the most significant
half of the data bus, pins D15-D8. Eight bit oriented devices tied
to the upper half of the bus would normally use BHE* to
condition chip select functions. BHE* is LOW during T1 for read,
write, and interrupt acknowledge cycles when a byte is to be
transferred on the high portion of the bus. The S,7 status
information is available during T2, T3 and T4. The signal is
active LOW and floats to 3-state OFF in “hold”. It is LOW during
T1 for the first interrupt acknowledge cycle.
BHE* A0 Characteristics

0 0 Whole word
0 1 Upper byte from / to odd address
1 0 Lower byte from / to even address
1 1 None
 Flag Register
❖ The EU also contains the Flag Register which is a collection of
condition bits and control bits. The condition bits are set or
cleared by the execution of an instruction. The control bits are set
by instructions to control some operation of the CPU.
• Bit 0 - CF Carry Flag - Set by carry out of msb
• Bit 2 - PF Parity Flag - Set if result has even parity
• Bit 4 - AF Auxiliary Flag - for BCD arithmetic
• Bit 6 - ZF Zero Flag - Set if result is zero
• Bit 7 - SF Sign Flag = MSB of result
• Bit 8 - TF Single Step Trap Flag
• Bit 9 - IF Interrupt Enable Flag
• Bit 10 - DF String Instruction Direction Flag
• Bit 11 - OF Overflow Flag
• Bits 1, 3, 5, 12-15 are undefined.

Bit 15 Bit 14 Bit 13 Bit 12 OF DF IF TF

SF ZF Bit 5 AF Bit 3 PF Bit 1 CF

 Addressing Mode
❖ We have seen how 8086 fetches code from
memory by generating 20-bit physical address
with the help of segment register contents and
offset
❖There are 12 basic Addressing Modes. They are
classified mainly in five groups.
➢ Addressing Mode for accessing immediate and register data.
➢ Addressing Mode for accessing data in Memory (Memory Mode).
➢ Addressing Mode for accessing IO ports (IO Mode).
➢ Relative Addressing Mode.
➢ Implied Addressing Mode.
 IMMEDIATE AND REGISTER DATA
❖ Immediate Addressing:
➢ In this mode, instruction gets its data as a part of instruction
itself. More specifically, the data in instruction is stored in code
segment instead of data segment. In this segment register cannot
be specified.
➢ Exp.:
• MOV BL, 26 H :Copies 8-bit data 26 H into BL
• MOV CX, 4567 H :Copies 16-bit data 4567 H into CX
❖ Register Addressing Mode:
➢ In this mode instruction operates on movement of data between
register of CPU or simply between source and destination of
data and register.
➢ Exp.:
• MOV BX, CX : Copies 16-bit contents of CX into BX
• MOV CL, BL : Copies 8-bit contents of BL into CL
ACCESSING DATA IN MEMORY
(MEMORY MODE)
➢ The EU has direct access to all registers and data for
register and immediate operands. However the EU
cannot directly access the memory operands. It must
use BIU segment register to access memory operands.
➢ When EU needs access to a memory location, it sends
offset value to BIU. This offset is also called as
Effective Address (EA). It is displacement of desired
location from segment base. There are six ways of
specifying EA in an instruction.
• Direct Addressing Mode
• Register Indirect Addressing Mode
• Based Addressing Mode
• Indexed Addressing Mode
• Base Indexed Addressing Mode
• String Addressing Mode
➢ Direct Addressing Mode:
• In this mode the 16-bit EA is taken directly from displacement field
of instruction. The displacement is stored in location following the
instruction Opcode.
➢ Exp:
• MOV CL, [9823 H] :This instruction will copy the
contents of memory location, at displacement of 9823 H from data
segment base, into CL register. Here 9823 is EA, which is directly
written in instruction.
➢ Register Indirect Addressing Mode:
• In this mode EA is specified in either a pointer register or an index
register. The pointer register can be BX or BP and index register can
be SI or DI.
➢ Exp:
• MOV [DI], BX :This instruction copies 16-bit contents
of BX into a memory location offset by the value of EA specified in
DI from current contents of DS, if [DS]=7200 H, [DI]=0030 H and
[BX]=4200 H, then after the instruction contents of BX (4200 H) is
copied to the memory location 72030 H and 72031 H.
➢ Based Addressing Mode:
• In this mode the EA is obtained by adding displacement
value to contents of BX or BP.
➢ Exp:
• MOV AL, DATA [BX or BP] :The source operand in the
given instruction is in based mode EA is obtained by adding
the value of DATA and [BX/BP], The 20-bit physical address
is produced from DS and ES. The 8-bit contents of this
location is copied at AL. The displacement DATA can be 16-
bit or 8-bit.
➢ Indexed Addressing Mode:
• In this EA is obtained by adding the displacement and
contents of SI or DI
➢ Exp:
• MOV BH, DATA [SI or DI] :Copies the contents of the 20-
bit address computed from the displacement DATA, SI/DI
and DS into BH.
➢Based Indexed Addressing Mode:
• In this EA is obtained by adding displacement, Base
register and index register.
➢Exp:
• MOV TOT [SI] [BX], CL :If [BX]=1500 H
TOT = 08 H, [SI] =1200 H , [DI] =4000 H
then contents of CL is copied to address
(40000 H+ 1200H+ 1500 H+0008 H)
➢ String Addressing Mode:
• This mode uses index register. The String instruction automatically
assumes SI to point to the first byte or word of the source operand
and DI to point to the first byte or word of the destination operand.
The contents of SI and DI are automatically incremented (by
clearing DF to ‘0’ by CLD instruction) or decremented (by setting
DF to’1’ by STD instruction) to point to the next byte or word. The
segment register for source is DS and for destination must be ES.
➢ Exp:
• MOVS BYTE :If [DF]=0
[DS]=3000 H
[SI]=0600 H
[ES]=5000 H [50400] H=45 H
[DI]=0400 H [30600] H=38 H
➢ After Execution: [50400] H=38 H, [SI]=0601 H, [DI]=0401 H
 ACCESSING IO PORTS (IO MODE):
❖In this there are two type Direct and Indirect.
➢ In Direct port mode, the port number is 8-bit
immediate operand. This allows fixed access to ports
numbered 0 to 255
➢ Exp:
• OUT 05 H, AL : Sends contents of AL to
8-bit port 05 H
➢ In indirect port mode, the port number is taken from
DX.
➢ Exp:
• IN AL, DX :If [DX]=7890 H then it copies 8-bit contents of
port 7890 H to AL.
• IN AX, DX :Now copies 16-bit contents of port 7890 H into
AL and AH respectively.
RELATIVE & IMPLIED ADDRESSING
MODE
❖In relative mode the operand is signed 8-
bit displacement relative to program
counter.
➢Exp:
• JNZ BACK
❖Instructions used in implied mode have
no operands
➢Exp:
• STC :Sets the carry flag to ‘1’
 INSTRUCTION SET
❖The instructions of 8086 are divided into
six groups
➢Data Transfer Instructions
➢Arithmetic Instructions
➢Bit Manipulation Instruction
➢String Instructions
➢Program Execution Transfer Instructions
➢Processor Control Instructions
 Data Transfer Instructions

➢General Purpose
• MOV,PUSH,POP,XCHG,XLAT
➢Address Object
• LEA,LDS,LES
➢Input/Output
• IN,OUT
➢Flag Transfer
• LAHF,SAHF,PUSHF,POPF
 Arithmetic Instructions
➢Addition
• ADD,ADC,INC,AAA,DAA
➢Subtraction
• SUB,SBB,DEC,NEG,CMP,AAS,DAS
➢Multiplication
• MUL,IMUL,AAM
➢Division
• DIV,IDIV,AAD,CBW,CWD
 Bit Manipulation Instruction
➢Logical
• NOT,AND,OR,XOR,TEST
➢Shifts
• SHL/SAL,SHR,SAR
➢Rotate
• ROL,ROR,RCL,RCR
❖String Instructions
• REP,REPE/REPZ,REPNE/REPNZ,MOVS,MOVSB/
MOVSW,CMPS,SCAS,LODS,STOS
❖ Processor Control Instructions
➢Flag operation
• STC,CLC,CMC,STD,CLD,STI,CLI
➢External Synchronization
• HLT,WAIT,ESC,LOCK
➢No operation
• NOP
 Program Execution Transfer
Instructions
❖ There are two main type of execution transfer
instructions i) Intra-segment ii)
Inter-segment
➢ Intra-Segment :In this the execution transfer is within the
segment and only the effective address changes.
➢ Inter-segment : In this case execution transfer is out of current
segment and new segment base and effective address related to
it is used for address generation.
❖ In case of Program Execution Transfer with the
execution of Opcode, the instruction queue in BIU is
flushed by EU and new queue is generated from new IP
address.
❖ If it is 8 – bit jump then termed as ‘short jump’ if 16 – bit
the ‘near jump’ within the segment.
❖ If jump is out of the segment then it is called ‘far jump’
➢Unconditional
• CALL,RET,JMP
➢Conditional
➢Iteration Control
• LOOP,LOOPE/LOOPZ,LOOPNE/LOOPNZ,JCXZ
➢Interrupt
• INT,INT0,IRET
Comparison of 8086 and 8088
1. In 8088 we have A15-8, instead of AD15-8 of
8086. this is because, the 8088 can
communicate with the outside world using
only 8 bits o data. However, the registers in
8088 and 8086 are same, and the instruction set
is also the same. So, for word operations, the
8088 has to access information twice. Thus the
execution time is increased in the case of 8088.

Continued…
2. In 8086 pin 28 is assigned for the signal M/IO* in the
minimum mode. But in 8088, this pin is assigned to the
signal IO/M* in the minimum mode. This change has been
done in 8088 so that the signal is compatible with 8085 bus
structure.
3. The instruction queue length in the case of 8086 is 6 bytes.
The BIU in 8088 needs more time to fill up the queue a
byte at a time. Thus to prevent overuse of the bus by the
BIU, the instruction queue in 8088 is shortened to 4 bytes.
4. To optimize the working of the queue, the 8086 BIU will
fetch a word into the queue whenever there is a space for
a word in the queue. The 8088 BIU will fetch a byte into
the queue whenever there is space for a byte in the queue.

Continued…
5. Pin number 34 of 8086 is BHE*/S7. BHE* is
irrelevant for 8088, which can only access 8 bits
at a time. Thus pin 34 o 8088 is assigned for the
signal SSO*. This pin acts like SO* status line in
the minimum mode of operation. So, in the
minimum mode, DT/R*, IO/M*, and SSO*
provide the complete bus status as shown.

Continued…
IO/M* DT/R* SSO* Bus Cycle
1 0 0 Interrupt acknowledge
1 0 1 Read I/O port
1 1 0 Write I/O port
1 1 1 Halt
0 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive
Continued…
6. In the maximum mode for 8088 the SSO* (pin 34) signal is
always a 1. In the maximum mode for 8086, the BHE*/S7
(pin 34) will provide BHE* information during the first clock
cycle, and will be 0 during subsequent clock cycles. In
maximum mode, 8087 will monitor this pin to identify the
CPU as a 8088 or a 8086, and accordingly sets its own queue
length to 4 or 6 bytes.