library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity contador3bits is

Port (

Ena : in STD_LOGIC;

X : in STD_LOGIC;

CLK : in STD_LOGIC;

salidaleds: out std_logic_vector ( 6 downto 0 );

Q : inout STD_LOGIC_VECTOR (2 downto 0)

);

end contador3bits ;

architecture Behavioral of contador3bits is

component fflop is

Port ( D : in STD_LOGIC;

en : in STD_LOGIC;

clk: in STD_LOGIC;

Q : out STD_LOGIC := '0');

end component fflop;

component deco7 is

Port (

bcd : in STD_LOGIC_VECTOR (2 downto 0);

outled : out STD_LOGIC_VECTOR (6 downto 0));

end component deco7;

component divclk is

Port ( clk : in STD_LOGIC;

divclk : out STD_LOGIC:='0');

end component divclk;

signal D, Qt: STD_LOGIC_VECTOR (2 downto 0);

signal clk_aux: std_logic :='0';

begin

D(2) <= ((not ena)and qt(2)) or ((not x) and qt(2)and (not qt(1))) or (qt(2) and qt(1) and (not qt(0)))
or ( x and qt(2) and qt(0)) or (ena and (not x) and (not qt(2)) and qt(1) and qt(0)) or (ena and x and
(not qt(2)) and (not qt(1)) and (not qt(0)));

D(1) <= ((not ena) and qt(1)) or ((not x) and qt(1) and (not qt(0))) or ( x and qt(1) and qt(0)) or (ena
and (not x) and (not qt(1)) and qt(0)) or (ena and x and (not qt(1)) and (not qt(0)));

D(0) <= ena xor qt(0);

flipflop2: fflop port map ( D => D (2),

en => ena,

clk => clk_aux,

q => qt(2));

flipflop1: fflop port map ( D=> D (1),

en => ena,

clk => clk_aux,

q => qt(1));

flipflop0: fflop port map ( D => D (0),

en => ena,

clk => clk_aux,

q => qt(0));

div: divclk port map ( clk => clk ,

divclk => clk_aux );

deco: deco7 port map ( bcd => q ,

outled => salidaleds );

q <= qt;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity deco7 is

Port (

bcd : in STD_LOGIC_VECTOR (2 downto 0);

outled : out STD_LOGIC_VECTOR (6 downto 0));

end deco7;

architecture Behavioral of deco7 is

begin

process (bcd)

begin

case bcd is

when "000" => outled <= "0000001";

when "001" => outled <= "1001111";

when "010" => outled <= "0010010";

when "011" => outled <= "0000110";

when "100" => outled <= "1001100";

when "101" => outled <= "0100100";

when "110" => outled <= "0100000";

when "111" => outled <= "0001111";

when others => outled <= "-------";

end case;

end process;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity divclk is

Port ( clk : in STD_LOGIC;

divclk : out STD_LOGIC:='0');

end divclk;

architecture Behavioral of divclk is

signal count_clk1 : INTEGER:=0;

signal div_aux: std_logic :='0';

begin -- YA SE PROGRAMO Y ESTA OK

process(CLK)

begin

if( rising_edge (clk)) then

if (count_clk1 = 50000000) then

count_clk1 <= 0;

div_aux <= not div_aux;

else

count_clk1 <= count_clk1 +1;

end if;

end if;

end process;

divclk <= div_aux;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;
entity fflop is -- ESTA OK TOMANDO COMO EJEMPLO EL DE DOS BITS

Port ( D : in STD_LOGIC;

en : in STD_LOGIC;

clk: in STD_LOGIC;

Q : out STD_LOGIC := '0');

end fflop;

architecture Behavioral of fflop is

begin

process (en, D, clk)

begin

if ( en = '1') then

if (rising_edge (clk) ) then

Q <= D;

end if;

end if;

end process;

end Behavioral;